pcc.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <div64.h>
  7. #include <asm/io.h>
  8. #include <errno.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/pcc.h>
  11. #include <asm/arch/sys_proto.h>
  12. #define PCC_CLKSRC_TYPES 2
  13. #define PCC_CLKSRC_NUM 7
  14. static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = {
  15. { SCG_NIC1_BUS_CLK,
  16. SCG_NIC1_CLK,
  17. SCG_DDR_CLK,
  18. SCG_APLL_PFD2_CLK,
  19. SCG_APLL_PFD1_CLK,
  20. SCG_APLL_PFD0_CLK,
  21. USB_PLL_OUT,
  22. },
  23. { SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */
  24. MIPI_PLL_OUT,
  25. SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */
  26. SCG_ROSC_CLK,
  27. SCG_NIC1_BUS_CLK,
  28. SCG_NIC1_CLK,
  29. SCG_APLL_PFD3_CLK,
  30. },
  31. };
  32. static struct pcc_entry pcc_arrays[] = {
  33. {PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  34. {PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  35. {PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  36. {PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  37. {PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  38. {PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  39. {PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  40. {PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  41. {PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  42. {PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  43. {PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  44. {PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  45. {PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  46. {PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  47. {PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  48. {PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  49. {PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  50. {PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  51. {PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  52. {PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  53. {PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  54. {PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  55. {PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  56. {PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
  57. {PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
  58. {PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  59. {PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  60. {PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  61. {PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  62. {PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  63. {PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  64. {PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  65. {PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
  66. {PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  67. {PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  68. {PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  69. {PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  70. {PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  71. {PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  72. {PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
  73. {PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
  74. };
  75. int pcc_clock_enable(enum pcc_clk clk, bool enable)
  76. {
  77. u32 reg, val;
  78. if (clk >= ARRAY_SIZE(pcc_arrays))
  79. return -EINVAL;
  80. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  81. val = readl(reg);
  82. clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",
  83. clk, reg, val, enable);
  84. if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK))
  85. return -EPERM;
  86. if (enable)
  87. val |= PCC_CGC_MASK;
  88. else
  89. val &= ~PCC_CGC_MASK;
  90. writel(val, reg);
  91. clk_debug("pcc_clock_enable: val 0x%x\n", val);
  92. return 0;
  93. }
  94. /* The clock source select needs clock is disabled */
  95. int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)
  96. {
  97. u32 reg, val, i, clksrc_type;
  98. if (clk >= ARRAY_SIZE(pcc_arrays))
  99. return -EINVAL;
  100. clksrc_type = pcc_arrays[clk].clksrc;
  101. if (clksrc_type >= CLKSRC_NO_PCS) {
  102. printf("No PCS field for the PCC %d, clksrc type %d\n",
  103. clk, clksrc_type);
  104. return -EPERM;
  105. }
  106. for (i = 0; i < PCC_CLKSRC_NUM; i++) {
  107. if (pcc_clksrc[clksrc_type][i] == src) {
  108. /* Find the clock src, then set it to PCS */
  109. break;
  110. }
  111. }
  112. if (i == PCC_CLKSRC_NUM) {
  113. printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
  114. return -EINVAL;
  115. }
  116. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  117. val = readl(reg);
  118. clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",
  119. clk, reg, val, clksrc_type);
  120. if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
  121. (val & PCC_CGC_MASK)) {
  122. printf("Not permit to select clock source val = 0x%x\n", val);
  123. return -EPERM;
  124. }
  125. val &= ~PCC_PCS_MASK;
  126. val |= ((i + 1) << PCC_PCS_OFFSET);
  127. writel(val, reg);
  128. clk_debug("pcc_clock_sel: val 0x%x\n", val);
  129. return 0;
  130. }
  131. int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)
  132. {
  133. u32 reg, val;
  134. if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||
  135. (div == 1 && frac != 0))
  136. return -EINVAL;
  137. if (pcc_arrays[clk].div >= PCC_NO_DIV) {
  138. printf("No DIV/FRAC field for the PCC %d\n", clk);
  139. return -EPERM;
  140. }
  141. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  142. val = readl(reg);
  143. if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
  144. (val & PCC_CGC_MASK)) {
  145. printf("Not permit to set div/frac val = 0x%x\n", val);
  146. return -EPERM;
  147. }
  148. if (frac)
  149. val |= PCC_FRAC_MASK;
  150. else
  151. val &= ~PCC_FRAC_MASK;
  152. val &= ~PCC_PCD_MASK;
  153. val |= (div - 1) & PCC_PCD_MASK;
  154. writel(val, reg);
  155. return 0;
  156. }
  157. bool pcc_clock_is_enable(enum pcc_clk clk)
  158. {
  159. u32 reg, val;
  160. if (clk >= ARRAY_SIZE(pcc_arrays))
  161. return -EINVAL;
  162. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  163. val = readl(reg);
  164. if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK))
  165. return true;
  166. return false;
  167. }
  168. int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
  169. {
  170. u32 reg, val, clksrc_type;
  171. if (clk >= ARRAY_SIZE(pcc_arrays))
  172. return -EINVAL;
  173. clksrc_type = pcc_arrays[clk].clksrc;
  174. if (clksrc_type >= CLKSRC_NO_PCS) {
  175. printf("No PCS field for the PCC %d, clksrc type %d\n",
  176. clk, clksrc_type);
  177. return -EPERM;
  178. }
  179. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  180. val = readl(reg);
  181. clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",
  182. clk, reg, val, clksrc_type);
  183. if (!(val & PCC_PR_MASK)) {
  184. printf("This pcc slot is not present = 0x%x\n", val);
  185. return -EPERM;
  186. }
  187. val &= PCC_PCS_MASK;
  188. val = (val >> PCC_PCS_OFFSET);
  189. if (!val) {
  190. printf("Clock source is off\n");
  191. return -EIO;
  192. }
  193. *src = pcc_clksrc[clksrc_type][val - 1];
  194. clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);
  195. return 0;
  196. }
  197. u32 pcc_clock_get_rate(enum pcc_clk clk)
  198. {
  199. u32 reg, val, rate, frac, div;
  200. enum scg_clk parent;
  201. int ret;
  202. ret = pcc_clock_get_clksrc(clk, &parent);
  203. if (ret)
  204. return 0;
  205. rate = scg_clk_get_rate(parent);
  206. clk_debug("pcc_clock_get_rate: parent rate %u\n", rate);
  207. if (pcc_arrays[clk].div == PCC_HAS_DIV) {
  208. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  209. val = readl(reg);
  210. frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
  211. div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
  212. /*
  213. * Theoretically don't have overflow in the calc,
  214. * the rate won't exceed 2G
  215. */
  216. rate = rate * (frac + 1) / (div + 1);
  217. }
  218. clk_debug("pcc_clock_get_rate: rate %u\n", rate);
  219. return rate;
  220. }