clock.c 8.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <command.h>
  8. #include <div64.h>
  9. #include <asm/io.h>
  10. #include <errno.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/sys_proto.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. int get_clocks(void)
  15. {
  16. #ifdef CONFIG_FSL_ESDHC_IMX
  17. #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
  18. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  19. #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
  20. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  21. #endif
  22. #endif
  23. return 0;
  24. }
  25. static u32 get_fast_plat_clk(void)
  26. {
  27. return scg_clk_get_rate(SCG_NIC0_CLK);
  28. }
  29. static u32 get_slow_plat_clk(void)
  30. {
  31. return scg_clk_get_rate(SCG_NIC1_CLK);
  32. }
  33. static u32 get_ipg_clk(void)
  34. {
  35. return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
  36. }
  37. u32 get_lpuart_clk(void)
  38. {
  39. int index = 0;
  40. const u32 lpuart_array[] = {
  41. LPUART0_RBASE,
  42. LPUART1_RBASE,
  43. LPUART2_RBASE,
  44. LPUART3_RBASE,
  45. LPUART4_RBASE,
  46. LPUART5_RBASE,
  47. LPUART6_RBASE,
  48. LPUART7_RBASE,
  49. };
  50. const enum pcc_clk lpuart_pcc_clks[] = {
  51. PER_CLK_LPUART4,
  52. PER_CLK_LPUART5,
  53. PER_CLK_LPUART6,
  54. PER_CLK_LPUART7,
  55. };
  56. for (index = 0; index < 8; index++) {
  57. if (lpuart_array[index] == LPUART_BASE)
  58. break;
  59. }
  60. if (index < 4 || index > 7)
  61. return 0;
  62. return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
  63. }
  64. #ifdef CONFIG_SYS_I2C_IMX_LPI2C
  65. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  66. {
  67. /* Set parent to FIRC DIV2 clock */
  68. const enum pcc_clk lpi2c_pcc_clks[] = {
  69. PER_CLK_LPI2C4,
  70. PER_CLK_LPI2C5,
  71. PER_CLK_LPI2C6,
  72. PER_CLK_LPI2C7,
  73. };
  74. if (i2c_num < 4 || i2c_num > 7)
  75. return -EINVAL;
  76. if (enable) {
  77. pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
  78. pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
  79. pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
  80. } else {
  81. pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
  82. }
  83. return 0;
  84. }
  85. u32 imx_get_i2cclk(unsigned i2c_num)
  86. {
  87. const enum pcc_clk lpi2c_pcc_clks[] = {
  88. PER_CLK_LPI2C4,
  89. PER_CLK_LPI2C5,
  90. PER_CLK_LPI2C6,
  91. PER_CLK_LPI2C7,
  92. };
  93. if (i2c_num < 4 || i2c_num > 7)
  94. return 0;
  95. return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
  96. }
  97. #endif
  98. unsigned int mxc_get_clock(enum mxc_clock clk)
  99. {
  100. switch (clk) {
  101. case MXC_ARM_CLK:
  102. return scg_clk_get_rate(SCG_CORE_CLK);
  103. case MXC_AXI_CLK:
  104. return get_fast_plat_clk();
  105. case MXC_AHB_CLK:
  106. return get_slow_plat_clk();
  107. case MXC_IPG_CLK:
  108. return get_ipg_clk();
  109. case MXC_I2C_CLK:
  110. return pcc_clock_get_rate(PER_CLK_LPI2C4);
  111. case MXC_UART_CLK:
  112. return get_lpuart_clk();
  113. case MXC_ESDHC_CLK:
  114. return pcc_clock_get_rate(PER_CLK_USDHC0);
  115. case MXC_ESDHC2_CLK:
  116. return pcc_clock_get_rate(PER_CLK_USDHC1);
  117. case MXC_DDR_CLK:
  118. return scg_clk_get_rate(SCG_DDR_CLK);
  119. default:
  120. printf("Unsupported mxc_clock %d\n", clk);
  121. break;
  122. }
  123. return 0;
  124. }
  125. void init_clk_usdhc(u32 index)
  126. {
  127. switch (index) {
  128. case 0:
  129. /*Disable the clock before configure it */
  130. pcc_clock_enable(PER_CLK_USDHC0, false);
  131. /* 158MHz / 1 = 158MHz */
  132. pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
  133. pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
  134. pcc_clock_enable(PER_CLK_USDHC0, true);
  135. break;
  136. case 1:
  137. /*Disable the clock before configure it */
  138. pcc_clock_enable(PER_CLK_USDHC1, false);
  139. /* 158MHz / 1 = 158MHz */
  140. pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
  141. pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
  142. pcc_clock_enable(PER_CLK_USDHC1, true);
  143. break;
  144. default:
  145. printf("Invalid index for USDHC %d\n", index);
  146. break;
  147. }
  148. }
  149. #ifdef CONFIG_MXC_OCOTP
  150. #define OCOTP_CTRL_PCC1_SLOT (38)
  151. #define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
  152. void enable_ocotp_clk(unsigned char enable)
  153. {
  154. u32 val;
  155. /*
  156. * Seems the OCOTP CLOCKs have been enabled at default,
  157. * check its inuse flag
  158. */
  159. val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
  160. if (!(val & PCC_INUSE_MASK))
  161. writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
  162. val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
  163. if (!(val & PCC_INUSE_MASK))
  164. writel(PCC_CGC_MASK,
  165. (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
  166. }
  167. #endif
  168. void enable_usboh3_clk(unsigned char enable)
  169. {
  170. if (enable) {
  171. pcc_clock_enable(PER_CLK_USB0, false);
  172. pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
  173. pcc_clock_enable(PER_CLK_USB0, true);
  174. #ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
  175. if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
  176. pcc_clock_enable(PER_CLK_USB1, false);
  177. pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
  178. pcc_clock_enable(PER_CLK_USB1, true);
  179. }
  180. #endif
  181. pcc_clock_enable(PER_CLK_USB_PHY, true);
  182. pcc_clock_enable(PER_CLK_USB_PL301, true);
  183. } else {
  184. pcc_clock_enable(PER_CLK_USB0, false);
  185. pcc_clock_enable(PER_CLK_USB1, false);
  186. pcc_clock_enable(PER_CLK_USB_PHY, false);
  187. pcc_clock_enable(PER_CLK_USB_PL301, false);
  188. }
  189. }
  190. static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
  191. {
  192. const enum pcc_clk lpuart_pcc_clks[] = {
  193. PER_CLK_LPUART4,
  194. PER_CLK_LPUART5,
  195. PER_CLK_LPUART6,
  196. PER_CLK_LPUART7,
  197. };
  198. if (index < 4 || index > 7)
  199. return;
  200. #ifndef CONFIG_CLK_DEBUG
  201. pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
  202. #endif
  203. pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
  204. pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
  205. }
  206. static void init_clk_lpuart(void)
  207. {
  208. u32 index = 0, i;
  209. const u32 lpuart_array[] = {
  210. LPUART0_RBASE,
  211. LPUART1_RBASE,
  212. LPUART2_RBASE,
  213. LPUART3_RBASE,
  214. LPUART4_RBASE,
  215. LPUART5_RBASE,
  216. LPUART6_RBASE,
  217. LPUART7_RBASE,
  218. };
  219. for (i = 0; i < 8; i++) {
  220. if (lpuart_array[i] == LPUART_BASE) {
  221. index = i;
  222. break;
  223. }
  224. }
  225. lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
  226. }
  227. static void init_clk_rgpio2p(void)
  228. {
  229. /*Enable RGPIO2P1 clock */
  230. pcc_clock_enable(PER_CLK_RGPIO2P1, true);
  231. /*
  232. * Hard code to enable RGPIO2P0 clock since it is not
  233. * in clock frame for A7 domain
  234. */
  235. writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
  236. }
  237. /* Configure PLL/PFD freq */
  238. void clock_init(void)
  239. {
  240. /*
  241. * ROM has enabled clocks:
  242. * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
  243. * Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
  244. * A7 side: SPLL PFD0 (scs selected, 413Mhz),
  245. * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
  246. * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
  247. * IP BUS (NIC1_BUS) = 58.6Mhz
  248. *
  249. * In u-boot:
  250. * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
  251. * 2. Enable USB PLL
  252. * 3. Init the clocks of peripherals used in u-boot bu
  253. * without set rate interface.The clocks for these
  254. * peripherals are enabled in this intialization.
  255. * 4.Other peripherals with set clock rate interface
  256. * does not be set in this function.
  257. */
  258. scg_a7_firc_init();
  259. scg_a7_soscdiv_init();
  260. scg_a7_init_core_clk();
  261. /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
  262. scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
  263. scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
  264. scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
  265. init_clk_lpuart();
  266. init_clk_rgpio2p();
  267. enable_usboh3_clk(1);
  268. }
  269. #ifdef CONFIG_IMX_HAB
  270. void hab_caam_clock_enable(unsigned char enable)
  271. {
  272. if (enable)
  273. pcc_clock_enable(PER_CLK_CAAM, true);
  274. else
  275. pcc_clock_enable(PER_CLK_CAAM, false);
  276. }
  277. #endif
  278. #ifndef CONFIG_SPL_BUILD
  279. /*
  280. * Dump some core clockes.
  281. */
  282. int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  283. char *const argv[])
  284. {
  285. u32 addr = 0;
  286. u32 freq;
  287. freq = decode_pll(PLL_A7_SPLL);
  288. printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
  289. freq = decode_pll(PLL_A7_APLL);
  290. printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
  291. freq = decode_pll(PLL_USB);
  292. printf("PLL_USB %8d MHz\n", freq / 1000000);
  293. printf("\n");
  294. printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
  295. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  296. printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  297. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  298. printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  299. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  300. printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  301. printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  302. printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
  303. addr = (u32) clock_init;
  304. printf("[%s] addr = 0x%08X\r\n", __func__, addr);
  305. scg_a7_info();
  306. return 0;
  307. }
  308. U_BOOT_CMD(
  309. clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
  310. "display clocks",
  311. ""
  312. );
  313. #endif