clock.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Author:
  6. * Peng Fan <Peng.Fan@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <command.h>
  11. #include <div64.h>
  12. #include <asm/io.h>
  13. #include <linux/errno.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/crm_regs.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/sys_proto.h>
  18. struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
  19. ANATOP_BASE_ADDR;
  20. struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  21. #ifdef CONFIG_FSL_ESDHC_IMX
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #endif
  24. int get_clocks(void)
  25. {
  26. #ifdef CONFIG_FSL_ESDHC_IMX
  27. #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
  28. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  29. #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
  30. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  31. #else
  32. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  33. #endif
  34. #endif
  35. return 0;
  36. }
  37. u32 get_ahb_clk(void)
  38. {
  39. return get_root_clk(AHB_CLK_ROOT);
  40. }
  41. static u32 get_ipg_clk(void)
  42. {
  43. /*
  44. * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
  45. * each other.
  46. */
  47. return get_ahb_clk() / 2;
  48. }
  49. u32 imx_get_uartclk(void)
  50. {
  51. return get_root_clk(UART_CLK_ROOT);
  52. }
  53. u32 imx_get_fecclk(void)
  54. {
  55. return get_root_clk(ENET_AXI_CLK_ROOT);
  56. }
  57. #ifdef CONFIG_MXC_OCOTP
  58. void enable_ocotp_clk(unsigned char enable)
  59. {
  60. clock_enable(CCGR_OCOTP, enable);
  61. }
  62. void enable_thermal_clk(void)
  63. {
  64. enable_ocotp_clk(1);
  65. }
  66. #endif
  67. void enable_usboh3_clk(unsigned char enable)
  68. {
  69. u32 target;
  70. if (enable) {
  71. /* disable the clock gate first */
  72. clock_enable(CCGR_USB_HSIC, 0);
  73. /* 120Mhz */
  74. target = CLK_ROOT_ON |
  75. USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
  76. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  77. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  78. clock_set_target_val(USB_HSIC_CLK_ROOT, target);
  79. /* enable the clock gate */
  80. clock_enable(CCGR_USB_CTRL, 1);
  81. clock_enable(CCGR_USB_HSIC, 1);
  82. clock_enable(CCGR_USB_PHY1, 1);
  83. clock_enable(CCGR_USB_PHY2, 1);
  84. } else {
  85. clock_enable(CCGR_USB_CTRL, 0);
  86. clock_enable(CCGR_USB_HSIC, 0);
  87. clock_enable(CCGR_USB_PHY1, 0);
  88. clock_enable(CCGR_USB_PHY2, 0);
  89. }
  90. }
  91. static u32 decode_pll(enum pll_clocks pll, u32 infreq)
  92. {
  93. u32 reg, div_sel;
  94. u32 num, denom;
  95. /*
  96. * Alought there are four choices for the bypass src,
  97. * we choose OSC_24M which is the default set in ROM.
  98. */
  99. switch (pll) {
  100. case PLL_CORE:
  101. reg = readl(&ccm_anatop->pll_arm);
  102. if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
  103. return 0;
  104. if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
  105. return MXC_HCLK;
  106. div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
  107. CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
  108. return (infreq * div_sel) / 2;
  109. case PLL_SYS:
  110. reg = readl(&ccm_anatop->pll_480);
  111. if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
  112. return 0;
  113. if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
  114. return MXC_HCLK;
  115. if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
  116. CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
  117. return 480000000u;
  118. else
  119. return 528000000u;
  120. case PLL_ENET:
  121. reg = readl(&ccm_anatop->pll_enet);
  122. if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
  123. return 0;
  124. if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
  125. return MXC_HCLK;
  126. return 1000000000u;
  127. case PLL_DDR:
  128. reg = readl(&ccm_anatop->pll_ddr);
  129. if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
  130. return 0;
  131. num = ccm_anatop->pll_ddr_num;
  132. denom = ccm_anatop->pll_ddr_denom;
  133. if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
  134. return MXC_HCLK;
  135. div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
  136. CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
  137. return infreq * (div_sel + num / denom);
  138. case PLL_USB:
  139. return 480000000u;
  140. default:
  141. printf("Unsupported pll clocks %d\n", pll);
  142. break;
  143. }
  144. return 0;
  145. }
  146. static u32 mxc_get_pll_sys_derive(int derive)
  147. {
  148. u32 freq, div, frac;
  149. u32 reg;
  150. div = 1;
  151. reg = readl(&ccm_anatop->pll_480);
  152. freq = decode_pll(PLL_SYS, MXC_HCLK);
  153. switch (derive) {
  154. case PLL_SYS_MAIN_480M_CLK:
  155. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
  156. return 0;
  157. else
  158. return freq;
  159. case PLL_SYS_MAIN_240M_CLK:
  160. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
  161. return 0;
  162. else
  163. return freq / 2;
  164. case PLL_SYS_MAIN_120M_CLK:
  165. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
  166. return 0;
  167. else
  168. return freq / 4;
  169. case PLL_SYS_PFD0_392M_CLK:
  170. reg = readl(&ccm_anatop->pfd_480a);
  171. if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
  172. return 0;
  173. frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
  174. CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
  175. break;
  176. case PLL_SYS_PFD0_196M_CLK:
  177. if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
  178. return 0;
  179. reg = readl(&ccm_anatop->pfd_480a);
  180. frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
  181. CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
  182. div = 2;
  183. break;
  184. case PLL_SYS_PFD1_332M_CLK:
  185. reg = readl(&ccm_anatop->pfd_480a);
  186. if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
  187. return 0;
  188. frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
  189. CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
  190. break;
  191. case PLL_SYS_PFD1_166M_CLK:
  192. if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
  193. return 0;
  194. reg = readl(&ccm_anatop->pfd_480a);
  195. frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
  196. CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
  197. div = 2;
  198. break;
  199. case PLL_SYS_PFD2_270M_CLK:
  200. reg = readl(&ccm_anatop->pfd_480a);
  201. if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
  202. return 0;
  203. frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
  204. CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
  205. break;
  206. case PLL_SYS_PFD2_135M_CLK:
  207. if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
  208. return 0;
  209. reg = readl(&ccm_anatop->pfd_480a);
  210. frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
  211. CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
  212. div = 2;
  213. break;
  214. case PLL_SYS_PFD3_CLK:
  215. reg = readl(&ccm_anatop->pfd_480a);
  216. if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
  217. return 0;
  218. frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
  219. CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
  220. break;
  221. case PLL_SYS_PFD4_CLK:
  222. reg = readl(&ccm_anatop->pfd_480b);
  223. if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
  224. return 0;
  225. frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
  226. CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
  227. break;
  228. case PLL_SYS_PFD5_CLK:
  229. reg = readl(&ccm_anatop->pfd_480b);
  230. if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
  231. return 0;
  232. frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
  233. CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
  234. break;
  235. case PLL_SYS_PFD6_CLK:
  236. reg = readl(&ccm_anatop->pfd_480b);
  237. if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
  238. return 0;
  239. frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
  240. CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
  241. break;
  242. case PLL_SYS_PFD7_CLK:
  243. reg = readl(&ccm_anatop->pfd_480b);
  244. if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
  245. return 0;
  246. frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
  247. CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
  248. break;
  249. default:
  250. printf("Error derived pll_sys clock %d\n", derive);
  251. return 0;
  252. }
  253. return ((freq / frac) * 18) / div;
  254. }
  255. static u32 mxc_get_pll_enet_derive(int derive)
  256. {
  257. u32 freq, reg;
  258. freq = decode_pll(PLL_ENET, MXC_HCLK);
  259. reg = readl(&ccm_anatop->pll_enet);
  260. switch (derive) {
  261. case PLL_ENET_MAIN_500M_CLK:
  262. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
  263. return freq / 2;
  264. break;
  265. case PLL_ENET_MAIN_250M_CLK:
  266. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
  267. return freq / 4;
  268. break;
  269. case PLL_ENET_MAIN_125M_CLK:
  270. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
  271. return freq / 8;
  272. break;
  273. case PLL_ENET_MAIN_100M_CLK:
  274. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
  275. return freq / 10;
  276. break;
  277. case PLL_ENET_MAIN_50M_CLK:
  278. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
  279. return freq / 20;
  280. break;
  281. case PLL_ENET_MAIN_40M_CLK:
  282. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
  283. return freq / 25;
  284. break;
  285. case PLL_ENET_MAIN_25M_CLK:
  286. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
  287. return freq / 40;
  288. break;
  289. default:
  290. printf("Error derived pll_enet clock %d\n", derive);
  291. break;
  292. }
  293. return 0;
  294. }
  295. static u32 mxc_get_pll_ddr_derive(int derive)
  296. {
  297. u32 freq, reg;
  298. freq = decode_pll(PLL_DDR, MXC_HCLK);
  299. reg = readl(&ccm_anatop->pll_ddr);
  300. switch (derive) {
  301. case PLL_DRAM_MAIN_1066M_CLK:
  302. return freq;
  303. case PLL_DRAM_MAIN_533M_CLK:
  304. if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
  305. return freq / 2;
  306. break;
  307. default:
  308. printf("Error derived pll_ddr clock %d\n", derive);
  309. break;
  310. }
  311. return 0;
  312. }
  313. static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
  314. {
  315. switch (pll) {
  316. case PLL_SYS:
  317. return mxc_get_pll_sys_derive(derive);
  318. case PLL_ENET:
  319. return mxc_get_pll_enet_derive(derive);
  320. case PLL_DDR:
  321. return mxc_get_pll_ddr_derive(derive);
  322. default:
  323. printf("Error pll.\n");
  324. return 0;
  325. }
  326. }
  327. static u32 get_root_src_clk(enum clk_root_src root_src)
  328. {
  329. switch (root_src) {
  330. case OSC_24M_CLK:
  331. return 24000000u;
  332. case PLL_ARM_MAIN_800M_CLK:
  333. return decode_pll(PLL_CORE, MXC_HCLK);
  334. case PLL_SYS_MAIN_480M_CLK:
  335. case PLL_SYS_MAIN_240M_CLK:
  336. case PLL_SYS_MAIN_120M_CLK:
  337. case PLL_SYS_PFD0_392M_CLK:
  338. case PLL_SYS_PFD0_196M_CLK:
  339. case PLL_SYS_PFD1_332M_CLK:
  340. case PLL_SYS_PFD1_166M_CLK:
  341. case PLL_SYS_PFD2_270M_CLK:
  342. case PLL_SYS_PFD2_135M_CLK:
  343. case PLL_SYS_PFD3_CLK:
  344. case PLL_SYS_PFD4_CLK:
  345. case PLL_SYS_PFD5_CLK:
  346. case PLL_SYS_PFD6_CLK:
  347. case PLL_SYS_PFD7_CLK:
  348. return mxc_get_pll_derive(PLL_SYS, root_src);
  349. case PLL_ENET_MAIN_500M_CLK:
  350. case PLL_ENET_MAIN_250M_CLK:
  351. case PLL_ENET_MAIN_125M_CLK:
  352. case PLL_ENET_MAIN_100M_CLK:
  353. case PLL_ENET_MAIN_50M_CLK:
  354. case PLL_ENET_MAIN_40M_CLK:
  355. case PLL_ENET_MAIN_25M_CLK:
  356. return mxc_get_pll_derive(PLL_ENET, root_src);
  357. case PLL_DRAM_MAIN_1066M_CLK:
  358. case PLL_DRAM_MAIN_533M_CLK:
  359. return mxc_get_pll_derive(PLL_DDR, root_src);
  360. case PLL_AUDIO_MAIN_CLK:
  361. return decode_pll(PLL_AUDIO, MXC_HCLK);
  362. case PLL_VIDEO_MAIN_CLK:
  363. return decode_pll(PLL_VIDEO, MXC_HCLK);
  364. case PLL_USB_MAIN_480M_CLK:
  365. return decode_pll(PLL_USB, MXC_HCLK);
  366. case REF_1M_CLK:
  367. return 1000000;
  368. case OSC_32K_CLK:
  369. return MXC_CLK32;
  370. case EXT_CLK_1:
  371. case EXT_CLK_2:
  372. case EXT_CLK_3:
  373. case EXT_CLK_4:
  374. printf("No EXT CLK supported??\n");
  375. break;
  376. };
  377. return 0;
  378. }
  379. u32 get_root_clk(enum clk_root_index clock_id)
  380. {
  381. enum clk_root_src root_src;
  382. u32 post_podf, pre_podf, auto_podf, root_src_clk;
  383. int auto_en;
  384. if (clock_root_enabled(clock_id) <= 0)
  385. return 0;
  386. if (clock_get_prediv(clock_id, &pre_podf) < 0)
  387. return 0;
  388. if (clock_get_postdiv(clock_id, &post_podf) < 0)
  389. return 0;
  390. if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
  391. return 0;
  392. if (auto_en == 0)
  393. auto_podf = 0;
  394. if (clock_get_src(clock_id, &root_src) < 0)
  395. return 0;
  396. root_src_clk = get_root_src_clk(root_src);
  397. /*
  398. * bypass clk is ignored.
  399. */
  400. return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
  401. (auto_podf + 1);
  402. }
  403. static u32 get_ddrc_clk(void)
  404. {
  405. u32 reg, freq;
  406. enum root_post_div post_div;
  407. reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
  408. if (reg & CLK_ROOT_MUX_MASK)
  409. /* DRAM_ALT_CLK_ROOT */
  410. freq = get_root_clk(DRAM_ALT_CLK_ROOT);
  411. else
  412. /* PLL_DRAM_MAIN_1066M_CLK */
  413. freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
  414. post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
  415. return freq / (post_div + 1) / 2;
  416. }
  417. unsigned int mxc_get_clock(enum mxc_clock clk)
  418. {
  419. switch (clk) {
  420. case MXC_ARM_CLK:
  421. return get_root_clk(ARM_A7_CLK_ROOT);
  422. case MXC_AXI_CLK:
  423. return get_root_clk(MAIN_AXI_CLK_ROOT);
  424. case MXC_AHB_CLK:
  425. return get_root_clk(AHB_CLK_ROOT);
  426. case MXC_IPG_CLK:
  427. return get_ipg_clk();
  428. case MXC_I2C_CLK:
  429. return get_root_clk(I2C1_CLK_ROOT);
  430. case MXC_UART_CLK:
  431. return get_root_clk(UART1_CLK_ROOT);
  432. case MXC_CSPI_CLK:
  433. return get_root_clk(ECSPI1_CLK_ROOT);
  434. case MXC_DDR_CLK:
  435. return get_ddrc_clk();
  436. case MXC_ESDHC_CLK:
  437. return get_root_clk(USDHC1_CLK_ROOT);
  438. case MXC_ESDHC2_CLK:
  439. return get_root_clk(USDHC2_CLK_ROOT);
  440. case MXC_ESDHC3_CLK:
  441. return get_root_clk(USDHC3_CLK_ROOT);
  442. default:
  443. printf("Unsupported mxc_clock %d\n", clk);
  444. break;
  445. }
  446. return 0;
  447. }
  448. #ifdef CONFIG_SYS_I2C_MXC
  449. /* i2c_num can be 0 - 3 */
  450. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  451. {
  452. u32 target;
  453. if (i2c_num >= 4)
  454. return -EINVAL;
  455. if (enable) {
  456. clock_enable(CCGR_I2C1 + i2c_num, 0);
  457. /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
  458. target = CLK_ROOT_ON |
  459. I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
  460. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  461. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  462. clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
  463. clock_enable(CCGR_I2C1 + i2c_num, 1);
  464. } else {
  465. clock_enable(CCGR_I2C1 + i2c_num, 0);
  466. }
  467. return 0;
  468. }
  469. #endif
  470. static void init_clk_esdhc(void)
  471. {
  472. u32 target;
  473. /* disable the clock gate first */
  474. clock_enable(CCGR_USDHC1, 0);
  475. clock_enable(CCGR_USDHC2, 0);
  476. clock_enable(CCGR_USDHC3, 0);
  477. /* 196: 392/2 */
  478. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  479. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  480. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  481. clock_set_target_val(USDHC1_CLK_ROOT, target);
  482. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  483. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  484. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  485. clock_set_target_val(USDHC2_CLK_ROOT, target);
  486. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  487. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  488. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  489. clock_set_target_val(USDHC3_CLK_ROOT, target);
  490. /* enable the clock gate */
  491. clock_enable(CCGR_USDHC1, 1);
  492. clock_enable(CCGR_USDHC2, 1);
  493. clock_enable(CCGR_USDHC3, 1);
  494. }
  495. static void init_clk_uart(void)
  496. {
  497. u32 target;
  498. /* disable the clock gate first */
  499. clock_enable(CCGR_UART1, 0);
  500. clock_enable(CCGR_UART2, 0);
  501. clock_enable(CCGR_UART3, 0);
  502. clock_enable(CCGR_UART4, 0);
  503. clock_enable(CCGR_UART5, 0);
  504. clock_enable(CCGR_UART6, 0);
  505. clock_enable(CCGR_UART7, 0);
  506. /* 24Mhz */
  507. target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
  508. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  509. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  510. clock_set_target_val(UART1_CLK_ROOT, target);
  511. target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
  512. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  513. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  514. clock_set_target_val(UART2_CLK_ROOT, target);
  515. target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
  516. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  517. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  518. clock_set_target_val(UART3_CLK_ROOT, target);
  519. target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
  520. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  521. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  522. clock_set_target_val(UART4_CLK_ROOT, target);
  523. target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
  524. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  525. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  526. clock_set_target_val(UART5_CLK_ROOT, target);
  527. target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
  528. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  529. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  530. clock_set_target_val(UART6_CLK_ROOT, target);
  531. target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
  532. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  533. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  534. clock_set_target_val(UART7_CLK_ROOT, target);
  535. /* enable the clock gate */
  536. clock_enable(CCGR_UART1, 1);
  537. clock_enable(CCGR_UART2, 1);
  538. clock_enable(CCGR_UART3, 1);
  539. clock_enable(CCGR_UART4, 1);
  540. clock_enable(CCGR_UART5, 1);
  541. clock_enable(CCGR_UART6, 1);
  542. clock_enable(CCGR_UART7, 1);
  543. }
  544. static void init_clk_weim(void)
  545. {
  546. u32 target;
  547. /* disable the clock gate first */
  548. clock_enable(CCGR_WEIM, 0);
  549. /* 120Mhz */
  550. target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
  551. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  552. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  553. clock_set_target_val(EIM_CLK_ROOT, target);
  554. /* enable the clock gate */
  555. clock_enable(CCGR_WEIM, 1);
  556. }
  557. static void init_clk_ecspi(void)
  558. {
  559. u32 target;
  560. /* disable the clock gate first */
  561. clock_enable(CCGR_ECSPI1, 0);
  562. clock_enable(CCGR_ECSPI2, 0);
  563. clock_enable(CCGR_ECSPI3, 0);
  564. clock_enable(CCGR_ECSPI4, 0);
  565. /* 60Mhz: 240/4 */
  566. target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  567. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  568. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  569. clock_set_target_val(ECSPI1_CLK_ROOT, target);
  570. target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  571. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  572. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  573. clock_set_target_val(ECSPI2_CLK_ROOT, target);
  574. target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  575. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  576. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  577. clock_set_target_val(ECSPI3_CLK_ROOT, target);
  578. target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  579. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  580. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  581. clock_set_target_val(ECSPI4_CLK_ROOT, target);
  582. /* enable the clock gate */
  583. clock_enable(CCGR_ECSPI1, 1);
  584. clock_enable(CCGR_ECSPI2, 1);
  585. clock_enable(CCGR_ECSPI3, 1);
  586. clock_enable(CCGR_ECSPI4, 1);
  587. }
  588. static void init_clk_wdog(void)
  589. {
  590. u32 target;
  591. /* disable the clock gate first */
  592. clock_enable(CCGR_WDOG1, 0);
  593. clock_enable(CCGR_WDOG2, 0);
  594. clock_enable(CCGR_WDOG3, 0);
  595. clock_enable(CCGR_WDOG4, 0);
  596. /* 24Mhz */
  597. target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
  598. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  599. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  600. clock_set_target_val(WDOG_CLK_ROOT, target);
  601. /* enable the clock gate */
  602. clock_enable(CCGR_WDOG1, 1);
  603. clock_enable(CCGR_WDOG2, 1);
  604. clock_enable(CCGR_WDOG3, 1);
  605. clock_enable(CCGR_WDOG4, 1);
  606. }
  607. #ifdef CONFIG_MXC_EPDC
  608. static void init_clk_epdc(void)
  609. {
  610. u32 target;
  611. /* disable the clock gate first */
  612. clock_enable(CCGR_EPDC, 0);
  613. /* 24Mhz */
  614. target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
  615. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  616. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
  617. clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
  618. /* enable the clock gate */
  619. clock_enable(CCGR_EPDC, 1);
  620. }
  621. #endif
  622. static int enable_pll_enet(void)
  623. {
  624. u32 reg;
  625. s32 timeout = 100000;
  626. reg = readl(&ccm_anatop->pll_enet);
  627. /* If pll_enet powered up, no need to set it again */
  628. if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
  629. reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
  630. writel(reg, &ccm_anatop->pll_enet);
  631. while (timeout--) {
  632. if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
  633. break;
  634. }
  635. if (timeout <= 0) {
  636. /* If timeout, we set pwdn for pll_enet. */
  637. reg |= ANADIG_PLL_ENET_PWDN_MASK;
  638. return -ETIME;
  639. }
  640. }
  641. /* Clear bypass */
  642. writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
  643. writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
  644. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
  645. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
  646. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
  647. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
  648. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
  649. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
  650. &ccm_anatop->pll_enet_set);
  651. return 0;
  652. }
  653. static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
  654. u32 post_div)
  655. {
  656. u32 reg = 0;
  657. ulong start;
  658. debug("pll5 div = %d, num = %d, denom = %d\n",
  659. pll_div, pll_num, pll_denom);
  660. /* Power up PLL5 video and disable its output */
  661. writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
  662. CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
  663. CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
  664. CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
  665. CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
  666. CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
  667. &ccm_anatop->pll_video_clr);
  668. /* Set div, num and denom */
  669. switch (post_div) {
  670. case 1:
  671. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  672. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
  673. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  674. &ccm_anatop->pll_video_set);
  675. break;
  676. case 2:
  677. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  678. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  679. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  680. &ccm_anatop->pll_video_set);
  681. break;
  682. case 3:
  683. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  684. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  685. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
  686. &ccm_anatop->pll_video_set);
  687. break;
  688. case 4:
  689. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  690. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  691. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
  692. &ccm_anatop->pll_video_set);
  693. break;
  694. case 0:
  695. default:
  696. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  697. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
  698. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  699. &ccm_anatop->pll_video_set);
  700. break;
  701. }
  702. writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
  703. &ccm_anatop->pll_video_num);
  704. writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
  705. &ccm_anatop->pll_video_denom);
  706. /* Wait PLL5 lock */
  707. start = get_timer(0); /* Get current timestamp */
  708. do {
  709. reg = readl(&ccm_anatop->pll_video);
  710. if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
  711. /* Enable PLL out */
  712. writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
  713. &ccm_anatop->pll_video_set);
  714. return 0;
  715. }
  716. } while (get_timer(0) < (start + 10)); /* Wait 10ms */
  717. printf("Lock PLL5 timeout\n");
  718. return 1;
  719. }
  720. int set_clk_qspi(void)
  721. {
  722. u32 target;
  723. /* disable the clock gate first */
  724. clock_enable(CCGR_QSPI, 0);
  725. /* 49M: 392/2/4 */
  726. target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
  727. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  728. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  729. clock_set_target_val(QSPI_CLK_ROOT, target);
  730. /* enable the clock gate */
  731. clock_enable(CCGR_QSPI, 1);
  732. return 0;
  733. }
  734. int set_clk_nand(void)
  735. {
  736. u32 target;
  737. /* disable the clock gate first */
  738. clock_enable(CCGR_RAWNAND, 0);
  739. enable_pll_enet();
  740. /* 100: 500/5 */
  741. target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
  742. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  743. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
  744. clock_set_target_val(NAND_CLK_ROOT, target);
  745. /* enable the clock gate */
  746. clock_enable(CCGR_RAWNAND, 1);
  747. return 0;
  748. }
  749. void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
  750. {
  751. u32 hck = MXC_HCLK/1000;
  752. u32 min = hck * 27;
  753. u32 max = hck * 54;
  754. u32 temp, best = 0;
  755. u32 i, j, pred = 1, postd = 1;
  756. u32 pll_div, pll_num, pll_denom, post_div = 0;
  757. u32 target;
  758. debug("mxs_set_lcdclk, freq = %d\n", freq);
  759. clock_enable(CCGR_LCDIF, 0);
  760. temp = (freq * 8 * 8);
  761. if (temp < min) {
  762. for (i = 1; i <= 4; i++) {
  763. if ((temp * (1 << i)) > min) {
  764. post_div = i;
  765. freq = (freq * (1 << i));
  766. break;
  767. }
  768. }
  769. if (5 == i) {
  770. printf("Fail to set rate to %dkhz", freq);
  771. return;
  772. }
  773. }
  774. for (i = 1; i <= 8; i++) {
  775. for (j = 1; j <= 8; j++) {
  776. temp = freq * i * j;
  777. if (temp > max || temp < min)
  778. continue;
  779. if (best == 0 || temp < best) {
  780. best = temp;
  781. pred = i;
  782. postd = j;
  783. }
  784. }
  785. }
  786. if (best == 0) {
  787. printf("Fail to set rate to %dkhz", freq);
  788. return;
  789. }
  790. debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
  791. pll_div = best / hck;
  792. pll_denom = 1000000;
  793. pll_num = (best - hck * pll_div) * pll_denom / hck;
  794. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  795. return;
  796. target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
  797. CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
  798. clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
  799. clock_enable(CCGR_LCDIF, 1);
  800. }
  801. #ifdef CONFIG_FEC_MXC
  802. int set_clk_enet(enum enet_freq type)
  803. {
  804. u32 target;
  805. int ret;
  806. u32 enet1_ref, enet2_ref;
  807. /* disable the clock first */
  808. clock_enable(CCGR_ENET1, 0);
  809. clock_enable(CCGR_ENET2, 0);
  810. switch (type) {
  811. case ENET_125MHZ:
  812. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  813. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  814. break;
  815. case ENET_50MHZ:
  816. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  817. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  818. break;
  819. case ENET_25MHZ:
  820. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  821. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  822. break;
  823. default:
  824. return -EINVAL;
  825. }
  826. ret = enable_pll_enet();
  827. if (ret != 0)
  828. return ret;
  829. /* set enet axi clock 196M: 392/2 */
  830. target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
  831. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  832. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  833. clock_set_target_val(ENET_AXI_CLK_ROOT, target);
  834. target = CLK_ROOT_ON | enet1_ref |
  835. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  836. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  837. clock_set_target_val(ENET1_REF_CLK_ROOT, target);
  838. target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  839. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  840. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  841. clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
  842. target = CLK_ROOT_ON | enet2_ref |
  843. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  844. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  845. clock_set_target_val(ENET2_REF_CLK_ROOT, target);
  846. target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  847. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  848. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  849. clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
  850. #ifdef CONFIG_FEC_MXC_25M_REF_CLK
  851. target = CLK_ROOT_ON |
  852. ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
  853. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  854. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  855. clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
  856. #endif
  857. /* enable clock */
  858. clock_enable(CCGR_ENET1, 1);
  859. clock_enable(CCGR_ENET2, 1);
  860. return 0;
  861. }
  862. #endif
  863. /* Configure PLL/PFD freq */
  864. void clock_init(void)
  865. {
  866. /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
  867. * In u-boot, we have to:
  868. * 1. Configure PFD3- PFD7 for freq we needed in u-boot
  869. * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
  870. * interface. The clocks for these peripherals are enabled after this intialization.
  871. * 3. Other peripherals with set clock rate interface does not be set in this function.
  872. */
  873. u32 reg;
  874. /*
  875. * Configure PFD4 to 392M
  876. * 480M * 18 / 0x16 = 392M
  877. */
  878. reg = readl(&ccm_anatop->pfd_480b);
  879. reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
  880. CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
  881. reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
  882. writel(reg, &ccm_anatop->pfd_480b);
  883. init_clk_esdhc();
  884. init_clk_uart();
  885. init_clk_weim();
  886. init_clk_ecspi();
  887. init_clk_wdog();
  888. #ifdef CONFIG_MXC_EPDC
  889. init_clk_epdc();
  890. #endif
  891. enable_usboh3_clk(1);
  892. clock_enable(CCGR_SNVS, 1);
  893. #ifdef CONFIG_NAND_MXS
  894. clock_enable(CCGR_RAWNAND, 1);
  895. #endif
  896. if (IS_ENABLED(CONFIG_IMX_RDC)) {
  897. clock_enable(CCGR_RDC, 1);
  898. clock_enable(CCGR_SEMA1, 1);
  899. clock_enable(CCGR_SEMA2, 1);
  900. }
  901. }
  902. #ifdef CONFIG_IMX_HAB
  903. void hab_caam_clock_enable(unsigned char enable)
  904. {
  905. if (enable)
  906. clock_enable(CCGR_CAAM, 1);
  907. else
  908. clock_enable(CCGR_CAAM, 0);
  909. }
  910. #endif
  911. #ifdef CONFIG_MXC_EPDC
  912. void epdc_clock_enable(void)
  913. {
  914. clock_enable(CCGR_EPDC, 1);
  915. }
  916. void epdc_clock_disable(void)
  917. {
  918. clock_enable(CCGR_EPDC, 0);
  919. }
  920. #endif
  921. #ifndef CONFIG_SPL_BUILD
  922. /*
  923. * Dump some core clockes.
  924. */
  925. int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  926. char *const argv[])
  927. {
  928. u32 freq;
  929. freq = decode_pll(PLL_CORE, MXC_HCLK);
  930. printf("PLL_CORE %8d MHz\n", freq / 1000000);
  931. freq = decode_pll(PLL_SYS, MXC_HCLK);
  932. printf("PLL_SYS %8d MHz\n", freq / 1000000);
  933. freq = decode_pll(PLL_ENET, MXC_HCLK);
  934. printf("PLL_NET %8d MHz\n", freq / 1000000);
  935. printf("\n");
  936. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  937. printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  938. #ifdef CONFIG_MXC_SPI
  939. printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
  940. #endif
  941. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  942. printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  943. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  944. printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  945. printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  946. printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
  947. return 0;
  948. }
  949. U_BOOT_CMD(
  950. clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
  951. "display clocks",
  952. ""
  953. );
  954. #endif