clock.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <div64.h>
  8. #include <asm/io.h>
  9. #include <linux/errno.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/crm_regs.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/sys_proto.h>
  14. enum pll_clocks {
  15. PLL_SYS, /* System PLL */
  16. PLL_BUS, /* System Bus PLL*/
  17. PLL_USBOTG, /* OTG USB PLL */
  18. PLL_ENET, /* ENET PLL */
  19. PLL_AUDIO, /* AUDIO PLL */
  20. PLL_VIDEO, /* VIDEO PLL */
  21. };
  22. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  23. #ifdef CONFIG_MXC_OCOTP
  24. void enable_ocotp_clk(unsigned char enable)
  25. {
  26. u32 reg;
  27. reg = __raw_readl(&imx_ccm->CCGR2);
  28. if (enable)
  29. reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  30. else
  31. reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  32. __raw_writel(reg, &imx_ccm->CCGR2);
  33. }
  34. #endif
  35. #ifdef CONFIG_NAND_MXS
  36. void setup_gpmi_io_clk(u32 cfg)
  37. {
  38. /* Disable clocks per ERR007177 from MX6 errata */
  39. clrbits_le32(&imx_ccm->CCGR4,
  40. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  41. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  42. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  43. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  44. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  45. #if defined(CONFIG_MX6SX)
  46. clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  47. clrsetbits_le32(&imx_ccm->cs2cdr,
  48. MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  49. MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  50. MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
  51. cfg);
  52. setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  53. #else
  54. clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  55. clrsetbits_le32(&imx_ccm->cs2cdr,
  56. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  57. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  58. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  59. cfg);
  60. setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  61. #endif
  62. setbits_le32(&imx_ccm->CCGR4,
  63. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  64. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  65. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  66. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  67. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  68. }
  69. #endif
  70. void enable_usboh3_clk(unsigned char enable)
  71. {
  72. u32 reg;
  73. reg = __raw_readl(&imx_ccm->CCGR6);
  74. if (enable)
  75. reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  76. else
  77. reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  78. __raw_writel(reg, &imx_ccm->CCGR6);
  79. }
  80. #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  81. void enable_enet_clk(unsigned char enable)
  82. {
  83. u32 mask, *addr;
  84. if (is_mx6ull()) {
  85. mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
  86. addr = &imx_ccm->CCGR0;
  87. } else if (is_mx6ul()) {
  88. mask = MXC_CCM_CCGR3_ENET_MASK;
  89. addr = &imx_ccm->CCGR3;
  90. } else {
  91. mask = MXC_CCM_CCGR1_ENET_MASK;
  92. addr = &imx_ccm->CCGR1;
  93. }
  94. if (enable)
  95. setbits_le32(addr, mask);
  96. else
  97. clrbits_le32(addr, mask);
  98. }
  99. #endif
  100. #ifdef CONFIG_MXC_UART
  101. void enable_uart_clk(unsigned char enable)
  102. {
  103. u32 mask;
  104. if (is_mx6ul() || is_mx6ull())
  105. mask = MXC_CCM_CCGR5_UART_MASK;
  106. else
  107. mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
  108. if (enable)
  109. setbits_le32(&imx_ccm->CCGR5, mask);
  110. else
  111. clrbits_le32(&imx_ccm->CCGR5, mask);
  112. }
  113. #endif
  114. #ifdef CONFIG_MMC
  115. int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
  116. {
  117. u32 mask;
  118. if (bus_num > 3)
  119. return -EINVAL;
  120. mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
  121. if (enable)
  122. setbits_le32(&imx_ccm->CCGR6, mask);
  123. else
  124. clrbits_le32(&imx_ccm->CCGR6, mask);
  125. return 0;
  126. }
  127. #endif
  128. #ifdef CONFIG_SYS_I2C_MXC
  129. /* i2c_num can be from 0 - 3 */
  130. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  131. {
  132. u32 reg;
  133. u32 mask;
  134. u32 *addr;
  135. if (i2c_num > 3)
  136. return -EINVAL;
  137. if (i2c_num < 3) {
  138. mask = MXC_CCM_CCGR_CG_MASK
  139. << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
  140. + (i2c_num << 1));
  141. reg = __raw_readl(&imx_ccm->CCGR2);
  142. if (enable)
  143. reg |= mask;
  144. else
  145. reg &= ~mask;
  146. __raw_writel(reg, &imx_ccm->CCGR2);
  147. } else {
  148. if (is_mx6sll())
  149. return -EINVAL;
  150. if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
  151. mask = MXC_CCM_CCGR6_I2C4_MASK;
  152. addr = &imx_ccm->CCGR6;
  153. } else {
  154. mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
  155. addr = &imx_ccm->CCGR1;
  156. }
  157. reg = __raw_readl(addr);
  158. if (enable)
  159. reg |= mask;
  160. else
  161. reg &= ~mask;
  162. __raw_writel(reg, addr);
  163. }
  164. return 0;
  165. }
  166. #endif
  167. /* spi_num can be from 0 - SPI_MAX_NUM */
  168. int enable_spi_clk(unsigned char enable, unsigned spi_num)
  169. {
  170. u32 reg;
  171. u32 mask;
  172. if (spi_num > SPI_MAX_NUM)
  173. return -EINVAL;
  174. mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
  175. reg = __raw_readl(&imx_ccm->CCGR1);
  176. if (enable)
  177. reg |= mask;
  178. else
  179. reg &= ~mask;
  180. __raw_writel(reg, &imx_ccm->CCGR1);
  181. return 0;
  182. }
  183. static u32 decode_pll(enum pll_clocks pll, u32 infreq)
  184. {
  185. u32 div, test_div, pll_num, pll_denom;
  186. switch (pll) {
  187. case PLL_SYS:
  188. div = __raw_readl(&imx_ccm->analog_pll_sys);
  189. div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
  190. return (infreq * div) >> 1;
  191. case PLL_BUS:
  192. div = __raw_readl(&imx_ccm->analog_pll_528);
  193. div &= BM_ANADIG_PLL_528_DIV_SELECT;
  194. return infreq * (20 + (div << 1));
  195. case PLL_USBOTG:
  196. div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
  197. div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
  198. return infreq * (20 + (div << 1));
  199. case PLL_ENET:
  200. div = __raw_readl(&imx_ccm->analog_pll_enet);
  201. div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
  202. return 25000000 * (div + (div >> 1) + 1);
  203. case PLL_AUDIO:
  204. div = __raw_readl(&imx_ccm->analog_pll_audio);
  205. if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
  206. return 0;
  207. /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
  208. if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
  209. return MXC_HCLK;
  210. pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
  211. pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
  212. test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
  213. BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
  214. div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
  215. if (test_div == 3) {
  216. debug("Error test_div\n");
  217. return 0;
  218. }
  219. test_div = 1 << (2 - test_div);
  220. return infreq * (div + pll_num / pll_denom) / test_div;
  221. case PLL_VIDEO:
  222. div = __raw_readl(&imx_ccm->analog_pll_video);
  223. if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
  224. return 0;
  225. /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
  226. if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
  227. return MXC_HCLK;
  228. pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
  229. pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
  230. test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
  231. BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  232. div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  233. if (test_div == 3) {
  234. debug("Error test_div\n");
  235. return 0;
  236. }
  237. test_div = 1 << (2 - test_div);
  238. return infreq * (div + pll_num / pll_denom) / test_div;
  239. default:
  240. return 0;
  241. }
  242. /* NOTREACHED */
  243. }
  244. static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
  245. {
  246. u32 div;
  247. u64 freq;
  248. switch (pll) {
  249. case PLL_BUS:
  250. if (!is_mx6ul() && !is_mx6ull()) {
  251. if (pfd_num == 3) {
  252. /* No PFD3 on PLL2 */
  253. return 0;
  254. }
  255. }
  256. div = __raw_readl(&imx_ccm->analog_pfd_528);
  257. freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
  258. break;
  259. case PLL_USBOTG:
  260. div = __raw_readl(&imx_ccm->analog_pfd_480);
  261. freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
  262. break;
  263. default:
  264. /* No PFD on other PLL */
  265. return 0;
  266. }
  267. return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
  268. ANATOP_PFD_FRAC_SHIFT(pfd_num));
  269. }
  270. static u32 get_mcu_main_clk(void)
  271. {
  272. u32 reg, freq;
  273. reg = __raw_readl(&imx_ccm->cacrr);
  274. reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
  275. reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
  276. freq = decode_pll(PLL_SYS, MXC_HCLK);
  277. return freq / (reg + 1);
  278. }
  279. u32 get_periph_clk(void)
  280. {
  281. u32 reg, div = 0, freq = 0;
  282. reg = __raw_readl(&imx_ccm->cbcdr);
  283. if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
  284. div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
  285. MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
  286. reg = __raw_readl(&imx_ccm->cbcmr);
  287. reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
  288. reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
  289. switch (reg) {
  290. case 0:
  291. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  292. break;
  293. case 1:
  294. case 2:
  295. freq = MXC_HCLK;
  296. break;
  297. default:
  298. break;
  299. }
  300. } else {
  301. reg = __raw_readl(&imx_ccm->cbcmr);
  302. reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
  303. reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
  304. switch (reg) {
  305. case 0:
  306. freq = decode_pll(PLL_BUS, MXC_HCLK);
  307. break;
  308. case 1:
  309. freq = mxc_get_pll_pfd(PLL_BUS, 2);
  310. break;
  311. case 2:
  312. freq = mxc_get_pll_pfd(PLL_BUS, 0);
  313. break;
  314. case 3:
  315. /* static / 2 divider */
  316. freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
  317. break;
  318. default:
  319. break;
  320. }
  321. }
  322. return freq / (div + 1);
  323. }
  324. static u32 get_ipg_clk(void)
  325. {
  326. u32 reg, ipg_podf;
  327. reg = __raw_readl(&imx_ccm->cbcdr);
  328. reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
  329. ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
  330. return get_ahb_clk() / (ipg_podf + 1);
  331. }
  332. static u32 get_ipg_per_clk(void)
  333. {
  334. u32 reg, perclk_podf;
  335. reg = __raw_readl(&imx_ccm->cscmr1);
  336. if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
  337. is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
  338. if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
  339. return MXC_HCLK; /* OSC 24Mhz */
  340. }
  341. perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
  342. return get_ipg_clk() / (perclk_podf + 1);
  343. }
  344. static u32 get_uart_clk(void)
  345. {
  346. u32 reg, uart_podf;
  347. u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
  348. reg = __raw_readl(&imx_ccm->cscdr1);
  349. if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
  350. is_mx6sll() || is_mx6ull()) {
  351. if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
  352. freq = MXC_HCLK;
  353. }
  354. reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
  355. uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
  356. return freq / (uart_podf + 1);
  357. }
  358. static u32 get_cspi_clk(void)
  359. {
  360. u32 reg, cspi_podf;
  361. reg = __raw_readl(&imx_ccm->cscdr2);
  362. cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
  363. MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
  364. if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
  365. is_mx6sll() || is_mx6ull()) {
  366. if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
  367. return MXC_HCLK / (cspi_podf + 1);
  368. }
  369. return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
  370. }
  371. static u32 get_axi_clk(void)
  372. {
  373. u32 root_freq, axi_podf;
  374. u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
  375. axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
  376. axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
  377. if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
  378. if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
  379. root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
  380. else
  381. root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
  382. } else
  383. root_freq = get_periph_clk();
  384. return root_freq / (axi_podf + 1);
  385. }
  386. static u32 get_emi_slow_clk(void)
  387. {
  388. u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
  389. cscmr1 = __raw_readl(&imx_ccm->cscmr1);
  390. emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
  391. emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
  392. emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
  393. emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
  394. switch (emi_clk_sel) {
  395. case 0:
  396. root_freq = get_axi_clk();
  397. break;
  398. case 1:
  399. root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  400. break;
  401. case 2:
  402. root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
  403. break;
  404. case 3:
  405. root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
  406. break;
  407. }
  408. return root_freq / (emi_slow_podf + 1);
  409. }
  410. static u32 get_mmdc_ch0_clk(void)
  411. {
  412. u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
  413. u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
  414. u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
  415. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
  416. is_mx6sll()) {
  417. podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
  418. MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
  419. if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
  420. per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
  421. MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
  422. if (is_mx6sl()) {
  423. if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
  424. freq = MXC_HCLK;
  425. else
  426. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  427. } else {
  428. if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
  429. freq = decode_pll(PLL_BUS, MXC_HCLK);
  430. else
  431. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  432. }
  433. } else {
  434. per2_clk2_podf = 0;
  435. switch ((cbcmr &
  436. MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
  437. MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
  438. case 0:
  439. freq = decode_pll(PLL_BUS, MXC_HCLK);
  440. break;
  441. case 1:
  442. freq = mxc_get_pll_pfd(PLL_BUS, 2);
  443. break;
  444. case 2:
  445. freq = mxc_get_pll_pfd(PLL_BUS, 0);
  446. break;
  447. case 3:
  448. if (is_mx6sl()) {
  449. freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
  450. break;
  451. }
  452. pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
  453. switch (pmu_misc2_audio_div) {
  454. case 0:
  455. case 2:
  456. pmu_misc2_audio_div = 1;
  457. break;
  458. case 1:
  459. pmu_misc2_audio_div = 2;
  460. break;
  461. case 3:
  462. pmu_misc2_audio_div = 4;
  463. break;
  464. }
  465. freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
  466. pmu_misc2_audio_div;
  467. break;
  468. }
  469. }
  470. return freq / (podf + 1) / (per2_clk2_podf + 1);
  471. } else {
  472. podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
  473. MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
  474. return get_periph_clk() / (podf + 1);
  475. }
  476. }
  477. #if defined(CONFIG_VIDEO_MXS)
  478. static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
  479. u32 post_div)
  480. {
  481. u32 reg = 0;
  482. ulong start;
  483. debug("pll5 div = %d, num = %d, denom = %d\n",
  484. pll_div, pll_num, pll_denom);
  485. /* Power up PLL5 video */
  486. writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
  487. BM_ANADIG_PLL_VIDEO_BYPASS |
  488. BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  489. BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  490. &imx_ccm->analog_pll_video_clr);
  491. /* Set div, num and denom */
  492. switch (post_div) {
  493. case 1:
  494. writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  495. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
  496. &imx_ccm->analog_pll_video_set);
  497. break;
  498. case 2:
  499. writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  500. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
  501. &imx_ccm->analog_pll_video_set);
  502. break;
  503. case 4:
  504. writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  505. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
  506. &imx_ccm->analog_pll_video_set);
  507. break;
  508. default:
  509. puts("Wrong test_div!\n");
  510. return -EINVAL;
  511. }
  512. writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
  513. &imx_ccm->analog_pll_video_num);
  514. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
  515. &imx_ccm->analog_pll_video_denom);
  516. /* Wait PLL5 lock */
  517. start = get_timer(0); /* Get current timestamp */
  518. do {
  519. reg = readl(&imx_ccm->analog_pll_video);
  520. if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
  521. /* Enable PLL out */
  522. writel(BM_ANADIG_PLL_VIDEO_ENABLE,
  523. &imx_ccm->analog_pll_video_set);
  524. return 0;
  525. }
  526. } while (get_timer(0) < (start + 10)); /* Wait 10ms */
  527. puts("Lock PLL5 timeout\n");
  528. return -ETIME;
  529. }
  530. /*
  531. * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
  532. *
  533. * 'freq' using KHz as unit, see driver/video/mxsfb.c.
  534. */
  535. void mxs_set_lcdclk(u32 base_addr, u32 freq)
  536. {
  537. u32 reg = 0;
  538. u32 hck = MXC_HCLK / 1000;
  539. /* DIV_SELECT ranges from 27 to 54 */
  540. u32 min = hck * 27;
  541. u32 max = hck * 54;
  542. u32 temp, best = 0;
  543. u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
  544. u32 pll_div, pll_num, pll_denom, post_div = 1;
  545. debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
  546. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
  547. !is_mx6sll()) {
  548. debug("This chip not support lcd!\n");
  549. return;
  550. }
  551. if (!is_mx6sl()) {
  552. if (base_addr == LCDIF1_BASE_ADDR) {
  553. reg = readl(&imx_ccm->cscdr2);
  554. /* Can't change clocks when clock not from pre-mux */
  555. if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
  556. return;
  557. }
  558. }
  559. if (is_mx6sx()) {
  560. reg = readl(&imx_ccm->cscdr2);
  561. /* Can't change clocks when clock not from pre-mux */
  562. if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
  563. return;
  564. }
  565. temp = freq * max_pred * max_postd;
  566. if (temp < min) {
  567. /*
  568. * Register: PLL_VIDEO
  569. * Bit Field: POST_DIV_SELECT
  570. * 00 — Divide by 4.
  571. * 01 — Divide by 2.
  572. * 10 — Divide by 1.
  573. * 11 — Reserved
  574. * No need to check post_div(1)
  575. */
  576. for (post_div = 2; post_div <= 4; post_div <<= 1) {
  577. if ((temp * post_div) > min) {
  578. freq *= post_div;
  579. break;
  580. }
  581. }
  582. if (post_div > 4) {
  583. printf("Fail to set rate to %dkhz", freq);
  584. return;
  585. }
  586. }
  587. /* Choose the best pred and postd to match freq for lcd */
  588. for (i = 1; i <= max_pred; i++) {
  589. for (j = 1; j <= max_postd; j++) {
  590. temp = freq * i * j;
  591. if (temp > max || temp < min)
  592. continue;
  593. if (best == 0 || temp < best) {
  594. best = temp;
  595. pred = i;
  596. postd = j;
  597. }
  598. }
  599. }
  600. if (best == 0) {
  601. printf("Fail to set rate to %dKHz", freq);
  602. return;
  603. }
  604. debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
  605. pll_div = best / hck;
  606. pll_denom = 1000000;
  607. pll_num = (best - hck * pll_div) * pll_denom / hck;
  608. /*
  609. * pll_num
  610. * (24MHz * (pll_div + --------- ))
  611. * pll_denom
  612. *freq KHz = --------------------------------
  613. * post_div * pred * postd * 1000
  614. */
  615. if (base_addr == LCDIF1_BASE_ADDR) {
  616. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  617. return;
  618. enable_lcdif_clock(base_addr, 0);
  619. if (!is_mx6sl()) {
  620. /* Select pre-lcd clock to PLL5 and set pre divider */
  621. clrsetbits_le32(&imx_ccm->cscdr2,
  622. MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
  623. MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
  624. (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
  625. ((pred - 1) <<
  626. MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
  627. /* Set the post divider */
  628. clrsetbits_le32(&imx_ccm->cbcmr,
  629. MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
  630. ((postd - 1) <<
  631. MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
  632. } else {
  633. /* Select pre-lcd clock to PLL5 and set pre divider */
  634. clrsetbits_le32(&imx_ccm->cscdr2,
  635. MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
  636. MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
  637. (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
  638. ((pred - 1) <<
  639. MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
  640. /* Set the post divider */
  641. clrsetbits_le32(&imx_ccm->cscmr1,
  642. MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
  643. (((postd - 1)^0x6) <<
  644. MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
  645. }
  646. enable_lcdif_clock(base_addr, 1);
  647. } else if (is_mx6sx()) {
  648. /* Setting LCDIF2 for i.MX6SX */
  649. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  650. return;
  651. enable_lcdif_clock(base_addr, 0);
  652. /* Select pre-lcd clock to PLL5 and set pre divider */
  653. clrsetbits_le32(&imx_ccm->cscdr2,
  654. MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
  655. MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
  656. (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
  657. ((pred - 1) <<
  658. MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
  659. /* Set the post divider */
  660. clrsetbits_le32(&imx_ccm->cscmr1,
  661. MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
  662. ((postd - 1) <<
  663. MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
  664. enable_lcdif_clock(base_addr, 1);
  665. }
  666. }
  667. int enable_lcdif_clock(u32 base_addr, bool enable)
  668. {
  669. u32 reg = 0;
  670. u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
  671. if (is_mx6sx()) {
  672. if ((base_addr != LCDIF1_BASE_ADDR) &&
  673. (base_addr != LCDIF2_BASE_ADDR)) {
  674. puts("Wrong LCD interface!\n");
  675. return -EINVAL;
  676. }
  677. /* Set to pre-mux clock at default */
  678. lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
  679. MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
  680. MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  681. lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
  682. (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
  683. MXC_CCM_CCGR3_DISP_AXI_MASK) :
  684. (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
  685. MXC_CCM_CCGR3_DISP_AXI_MASK);
  686. } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
  687. if (base_addr != LCDIF1_BASE_ADDR) {
  688. puts("Wrong LCD interface!\n");
  689. return -EINVAL;
  690. }
  691. /* Set to pre-mux clock at default */
  692. lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  693. lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
  694. } else if (is_mx6sl()) {
  695. if (base_addr != LCDIF1_BASE_ADDR) {
  696. puts("Wrong LCD interface!\n");
  697. return -EINVAL;
  698. }
  699. reg = readl(&imx_ccm->CCGR3);
  700. reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
  701. MXC_CCM_CCGR3_LCDIF_PIX_MASK);
  702. writel(reg, &imx_ccm->CCGR3);
  703. if (enable) {
  704. reg = readl(&imx_ccm->cscdr3);
  705. reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
  706. reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
  707. writel(reg, &imx_ccm->cscdr3);
  708. reg = readl(&imx_ccm->CCGR3);
  709. reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
  710. MXC_CCM_CCGR3_LCDIF_PIX_MASK;
  711. writel(reg, &imx_ccm->CCGR3);
  712. }
  713. return 0;
  714. } else {
  715. return 0;
  716. }
  717. /* Gate LCDIF clock first */
  718. reg = readl(&imx_ccm->CCGR3);
  719. reg &= ~lcdif_ccgr3_mask;
  720. writel(reg, &imx_ccm->CCGR3);
  721. reg = readl(&imx_ccm->CCGR2);
  722. reg &= ~MXC_CCM_CCGR2_LCD_MASK;
  723. writel(reg, &imx_ccm->CCGR2);
  724. if (enable) {
  725. /* Select pre-mux */
  726. reg = readl(&imx_ccm->cscdr2);
  727. reg &= ~lcdif_clk_sel_mask;
  728. writel(reg, &imx_ccm->cscdr2);
  729. /* Enable the LCDIF pix clock */
  730. reg = readl(&imx_ccm->CCGR3);
  731. reg |= lcdif_ccgr3_mask;
  732. writel(reg, &imx_ccm->CCGR3);
  733. reg = readl(&imx_ccm->CCGR2);
  734. reg |= MXC_CCM_CCGR2_LCD_MASK;
  735. writel(reg, &imx_ccm->CCGR2);
  736. }
  737. return 0;
  738. }
  739. #endif
  740. #ifdef CONFIG_FSL_QSPI
  741. /* qspi_num can be from 0 - 1 */
  742. void enable_qspi_clk(int qspi_num)
  743. {
  744. u32 reg = 0;
  745. /* Enable QuadSPI clock */
  746. switch (qspi_num) {
  747. case 0:
  748. /* disable the clock gate */
  749. clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
  750. /* set 50M : (50 = 396 / 2 / 4) */
  751. reg = readl(&imx_ccm->cscmr1);
  752. reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
  753. MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
  754. reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
  755. (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
  756. writel(reg, &imx_ccm->cscmr1);
  757. /* enable the clock gate */
  758. setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
  759. break;
  760. case 1:
  761. /*
  762. * disable the clock gate
  763. * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
  764. * disable both of them.
  765. */
  766. clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
  767. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
  768. /* set 50M : (50 = 396 / 2 / 4) */
  769. reg = readl(&imx_ccm->cs2cdr);
  770. reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  771. MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  772. MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
  773. reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
  774. MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
  775. writel(reg, &imx_ccm->cs2cdr);
  776. /*enable the clock gate*/
  777. setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
  778. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
  779. break;
  780. default:
  781. break;
  782. }
  783. }
  784. #endif
  785. #ifdef CONFIG_FEC_MXC
  786. int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
  787. {
  788. u32 reg = 0;
  789. s32 timeout = 100000;
  790. struct anatop_regs __iomem *anatop =
  791. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  792. if (freq < ENET_25MHZ || freq > ENET_125MHZ)
  793. return -EINVAL;
  794. reg = readl(&anatop->pll_enet);
  795. if (fec_id == 0) {
  796. reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
  797. reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
  798. } else if (fec_id == 1) {
  799. /* Only i.MX6SX/UL support ENET2 */
  800. if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
  801. return -EINVAL;
  802. reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
  803. reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
  804. } else {
  805. return -EINVAL;
  806. }
  807. if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
  808. (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
  809. reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
  810. writel(reg, &anatop->pll_enet);
  811. while (timeout--) {
  812. if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
  813. break;
  814. }
  815. if (timeout < 0)
  816. return -ETIMEDOUT;
  817. }
  818. /* Enable FEC clock */
  819. if (fec_id == 0)
  820. reg |= BM_ANADIG_PLL_ENET_ENABLE;
  821. else
  822. reg |= BM_ANADIG_PLL_ENET2_ENABLE;
  823. reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
  824. writel(reg, &anatop->pll_enet);
  825. #ifdef CONFIG_MX6SX
  826. /* Disable enet system clcok before switching clock parent */
  827. reg = readl(&imx_ccm->CCGR3);
  828. reg &= ~MXC_CCM_CCGR3_ENET_MASK;
  829. writel(reg, &imx_ccm->CCGR3);
  830. /*
  831. * Set enet ahb clock to 200MHz
  832. * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
  833. */
  834. reg = readl(&imx_ccm->chsccdr);
  835. reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
  836. | MXC_CCM_CHSCCDR_ENET_PODF_MASK
  837. | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
  838. /* PLL2 PFD2 */
  839. reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
  840. /* Div = 2*/
  841. reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
  842. reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
  843. writel(reg, &imx_ccm->chsccdr);
  844. /* Enable enet system clock */
  845. reg = readl(&imx_ccm->CCGR3);
  846. reg |= MXC_CCM_CCGR3_ENET_MASK;
  847. writel(reg, &imx_ccm->CCGR3);
  848. #endif
  849. return 0;
  850. }
  851. #endif
  852. static u32 get_usdhc_clk(u32 port)
  853. {
  854. u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
  855. u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
  856. u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
  857. if (is_mx6ul() || is_mx6ull()) {
  858. if (port > 1)
  859. return 0;
  860. }
  861. if (is_mx6sll()) {
  862. if (port > 2)
  863. return 0;
  864. }
  865. switch (port) {
  866. case 0:
  867. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
  868. MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
  869. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
  870. break;
  871. case 1:
  872. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
  873. MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
  874. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
  875. break;
  876. case 2:
  877. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
  878. MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
  879. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
  880. break;
  881. case 3:
  882. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
  883. MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
  884. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
  885. break;
  886. default:
  887. break;
  888. }
  889. if (clk_sel)
  890. root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
  891. else
  892. root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
  893. return root_freq / (usdhc_podf + 1);
  894. }
  895. u32 imx_get_uartclk(void)
  896. {
  897. return get_uart_clk();
  898. }
  899. u32 imx_get_fecclk(void)
  900. {
  901. return mxc_get_clock(MXC_IPG_CLK);
  902. }
  903. #if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
  904. static int enable_enet_pll(uint32_t en)
  905. {
  906. struct mxc_ccm_reg *const imx_ccm
  907. = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
  908. s32 timeout = 100000;
  909. u32 reg = 0;
  910. /* Enable PLLs */
  911. reg = readl(&imx_ccm->analog_pll_enet);
  912. reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
  913. writel(reg, &imx_ccm->analog_pll_enet);
  914. reg |= BM_ANADIG_PLL_SYS_ENABLE;
  915. while (timeout--) {
  916. if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
  917. break;
  918. }
  919. if (timeout <= 0)
  920. return -EIO;
  921. reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
  922. writel(reg, &imx_ccm->analog_pll_enet);
  923. reg |= en;
  924. writel(reg, &imx_ccm->analog_pll_enet);
  925. return 0;
  926. }
  927. #endif
  928. #ifdef CONFIG_SATA
  929. static void ungate_sata_clock(void)
  930. {
  931. struct mxc_ccm_reg *const imx_ccm =
  932. (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  933. /* Enable SATA clock. */
  934. setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
  935. }
  936. int enable_sata_clock(void)
  937. {
  938. ungate_sata_clock();
  939. return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
  940. }
  941. void disable_sata_clock(void)
  942. {
  943. struct mxc_ccm_reg *const imx_ccm =
  944. (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  945. clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
  946. }
  947. #endif
  948. #ifdef CONFIG_PCIE_IMX
  949. static void ungate_pcie_clock(void)
  950. {
  951. struct mxc_ccm_reg *const imx_ccm =
  952. (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  953. /* Enable PCIe clock. */
  954. setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
  955. }
  956. int enable_pcie_clock(void)
  957. {
  958. struct anatop_regs *anatop_regs =
  959. (struct anatop_regs *)ANATOP_BASE_ADDR;
  960. struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  961. u32 lvds1_clk_sel;
  962. /*
  963. * Here be dragons!
  964. *
  965. * The register ANATOP_MISC1 is not documented in the Freescale
  966. * MX6RM. The register that is mapped in the ANATOP space and
  967. * marked as ANATOP_MISC1 is actually documented in the PMU section
  968. * of the datasheet as PMU_MISC1.
  969. *
  970. * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
  971. * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
  972. * for PCI express link that is clocked from the i.MX6.
  973. */
  974. #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
  975. #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
  976. #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
  977. #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
  978. #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
  979. if (is_mx6sx())
  980. lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
  981. else
  982. lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
  983. clrsetbits_le32(&anatop_regs->ana_misc1,
  984. ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
  985. ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
  986. ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
  987. /* PCIe reference clock sourced from AXI. */
  988. clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
  989. /* Party time! Ungate the clock to the PCIe. */
  990. #ifdef CONFIG_SATA
  991. ungate_sata_clock();
  992. #endif
  993. ungate_pcie_clock();
  994. return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
  995. BM_ANADIG_PLL_ENET_ENABLE_PCIE);
  996. }
  997. #endif
  998. #ifdef CONFIG_IMX_HAB
  999. void hab_caam_clock_enable(unsigned char enable)
  1000. {
  1001. u32 reg;
  1002. if (is_mx6ull() || is_mx6sll()) {
  1003. /* CG5, DCP clock */
  1004. reg = __raw_readl(&imx_ccm->CCGR0);
  1005. if (enable)
  1006. reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
  1007. else
  1008. reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
  1009. __raw_writel(reg, &imx_ccm->CCGR0);
  1010. } else {
  1011. /* CG4 ~ CG6, CAAM clocks */
  1012. reg = __raw_readl(&imx_ccm->CCGR0);
  1013. if (enable)
  1014. reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
  1015. MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
  1016. MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
  1017. else
  1018. reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
  1019. MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
  1020. MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
  1021. __raw_writel(reg, &imx_ccm->CCGR0);
  1022. }
  1023. /* EMI slow clk */
  1024. reg = __raw_readl(&imx_ccm->CCGR6);
  1025. if (enable)
  1026. reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1027. else
  1028. reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1029. __raw_writel(reg, &imx_ccm->CCGR6);
  1030. }
  1031. #endif
  1032. static void enable_pll3(void)
  1033. {
  1034. struct anatop_regs __iomem *anatop =
  1035. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  1036. /* make sure pll3 is enabled */
  1037. if ((readl(&anatop->usb1_pll_480_ctrl) &
  1038. BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
  1039. /* enable pll's power */
  1040. writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
  1041. &anatop->usb1_pll_480_ctrl_set);
  1042. writel(0x80, &anatop->ana_misc2_clr);
  1043. /* wait for pll lock */
  1044. while ((readl(&anatop->usb1_pll_480_ctrl) &
  1045. BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
  1046. ;
  1047. /* disable bypass */
  1048. writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
  1049. &anatop->usb1_pll_480_ctrl_clr);
  1050. /* enable pll output */
  1051. writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
  1052. &anatop->usb1_pll_480_ctrl_set);
  1053. }
  1054. }
  1055. void enable_thermal_clk(void)
  1056. {
  1057. enable_pll3();
  1058. }
  1059. #ifdef CONFIG_MTD_NOR_FLASH
  1060. void enable_eim_clk(unsigned char enable)
  1061. {
  1062. u32 reg;
  1063. reg = __raw_readl(&imx_ccm->CCGR6);
  1064. if (enable)
  1065. reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1066. else
  1067. reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1068. __raw_writel(reg, &imx_ccm->CCGR6);
  1069. }
  1070. #endif
  1071. unsigned int mxc_get_clock(enum mxc_clock clk)
  1072. {
  1073. switch (clk) {
  1074. case MXC_ARM_CLK:
  1075. return get_mcu_main_clk();
  1076. case MXC_PER_CLK:
  1077. return get_periph_clk();
  1078. case MXC_AHB_CLK:
  1079. return get_ahb_clk();
  1080. case MXC_IPG_CLK:
  1081. return get_ipg_clk();
  1082. case MXC_IPG_PERCLK:
  1083. case MXC_I2C_CLK:
  1084. return get_ipg_per_clk();
  1085. case MXC_UART_CLK:
  1086. return get_uart_clk();
  1087. case MXC_CSPI_CLK:
  1088. return get_cspi_clk();
  1089. case MXC_AXI_CLK:
  1090. return get_axi_clk();
  1091. case MXC_EMI_SLOW_CLK:
  1092. return get_emi_slow_clk();
  1093. case MXC_DDR_CLK:
  1094. return get_mmdc_ch0_clk();
  1095. case MXC_ESDHC_CLK:
  1096. return get_usdhc_clk(0);
  1097. case MXC_ESDHC2_CLK:
  1098. return get_usdhc_clk(1);
  1099. case MXC_ESDHC3_CLK:
  1100. return get_usdhc_clk(2);
  1101. case MXC_ESDHC4_CLK:
  1102. return get_usdhc_clk(3);
  1103. case MXC_SATA_CLK:
  1104. return get_ahb_clk();
  1105. default:
  1106. printf("Unsupported MXC CLK: %d\n", clk);
  1107. break;
  1108. }
  1109. return 0;
  1110. }
  1111. #ifndef CONFIG_MX6SX
  1112. void enable_ipu_clock(void)
  1113. {
  1114. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1115. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
  1116. if (is_mx6dqp()) {
  1117. setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
  1118. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
  1119. }
  1120. }
  1121. void disable_ipu_clock(void)
  1122. {
  1123. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1124. clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
  1125. if (is_mx6dqp()) {
  1126. clrbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
  1127. clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
  1128. }
  1129. }
  1130. #endif
  1131. #ifndef CONFIG_SPL_BUILD
  1132. /*
  1133. * Dump some core clockes.
  1134. */
  1135. int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  1136. char *const argv[])
  1137. {
  1138. u32 freq;
  1139. freq = decode_pll(PLL_SYS, MXC_HCLK);
  1140. printf("PLL_SYS %8d MHz\n", freq / 1000000);
  1141. freq = decode_pll(PLL_BUS, MXC_HCLK);
  1142. printf("PLL_BUS %8d MHz\n", freq / 1000000);
  1143. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  1144. printf("PLL_OTG %8d MHz\n", freq / 1000000);
  1145. freq = decode_pll(PLL_ENET, MXC_HCLK);
  1146. printf("PLL_NET %8d MHz\n", freq / 1000000);
  1147. printf("\n");
  1148. printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
  1149. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  1150. printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  1151. #ifdef CONFIG_MXC_SPI
  1152. printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
  1153. #endif
  1154. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  1155. printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  1156. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  1157. printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  1158. printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  1159. printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
  1160. printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
  1161. printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
  1162. printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
  1163. return 0;
  1164. }
  1165. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
  1166. defined(CONFIG_MX6S)
  1167. static void disable_ldb_di_clock_sources(void)
  1168. {
  1169. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1170. int reg;
  1171. /* Make sure PFDs are disabled at boot. */
  1172. reg = readl(&mxc_ccm->analog_pfd_528);
  1173. /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
  1174. if (is_mx6sdl())
  1175. reg |= 0x80008080;
  1176. else
  1177. reg |= 0x80808080;
  1178. writel(reg, &mxc_ccm->analog_pfd_528);
  1179. /* Disable PLL3 PFDs */
  1180. reg = readl(&mxc_ccm->analog_pfd_480);
  1181. reg |= 0x80808080;
  1182. writel(reg, &mxc_ccm->analog_pfd_480);
  1183. /* Disable PLL5 */
  1184. reg = readl(&mxc_ccm->analog_pll_video);
  1185. reg &= ~(1 << 13);
  1186. writel(reg, &mxc_ccm->analog_pll_video);
  1187. }
  1188. static void enable_ldb_di_clock_sources(void)
  1189. {
  1190. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1191. int reg;
  1192. reg = readl(&mxc_ccm->analog_pfd_528);
  1193. if (is_mx6sdl())
  1194. reg &= ~(0x80008080);
  1195. else
  1196. reg &= ~(0x80808080);
  1197. writel(reg, &mxc_ccm->analog_pfd_528);
  1198. reg = readl(&mxc_ccm->analog_pfd_480);
  1199. reg &= ~(0x80808080);
  1200. writel(reg, &mxc_ccm->analog_pfd_480);
  1201. }
  1202. /*
  1203. * Try call this function as early in the boot process as possible since the
  1204. * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
  1205. */
  1206. void select_ldb_di_clock_source(enum ldb_di_clock clk)
  1207. {
  1208. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1209. int reg;
  1210. /*
  1211. * Need to follow a strict procedure when changing the LDB
  1212. * clock, else we can introduce a glitch. Things to keep in
  1213. * mind:
  1214. * 1. The current and new parent clocks must be disabled.
  1215. * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
  1216. * no CG bit.
  1217. * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
  1218. * the top four options are in one mux and the PLL3 option along
  1219. * with another option is in the second mux. There is third mux
  1220. * used to decide between the first and second mux.
  1221. * The code below switches the parent to the bottom mux first
  1222. * and then manipulates the top mux. This ensures that no glitch
  1223. * will enter the divider.
  1224. *
  1225. * Need to disable MMDC_CH1 clock manually as there is no CG bit
  1226. * for this clock. The only way to disable this clock is to move
  1227. * it to pll3_sw_clk and then to disable pll3_sw_clk
  1228. * Make sure periph2_clk2_sel is set to pll3_sw_clk
  1229. */
  1230. /* Disable all ldb_di clock parents */
  1231. disable_ldb_di_clock_sources();
  1232. /* Set MMDC_CH1 mask bit */
  1233. reg = readl(&mxc_ccm->ccdr);
  1234. reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
  1235. writel(reg, &mxc_ccm->ccdr);
  1236. /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
  1237. reg = readl(&mxc_ccm->cbcmr);
  1238. reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
  1239. writel(reg, &mxc_ccm->cbcmr);
  1240. /*
  1241. * Set the periph2_clk_sel to the top mux so that
  1242. * mmdc_ch1 is from pll3_sw_clk.
  1243. */
  1244. reg = readl(&mxc_ccm->cbcdr);
  1245. reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
  1246. writel(reg, &mxc_ccm->cbcdr);
  1247. /* Wait for the clock switch */
  1248. while (readl(&mxc_ccm->cdhipr))
  1249. ;
  1250. /* Disable pll3_sw_clk by selecting bypass clock source */
  1251. reg = readl(&mxc_ccm->ccsr);
  1252. reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
  1253. writel(reg, &mxc_ccm->ccsr);
  1254. /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
  1255. reg = readl(&mxc_ccm->cs2cdr);
  1256. reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  1257. | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  1258. writel(reg, &mxc_ccm->cs2cdr);
  1259. /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
  1260. reg = readl(&mxc_ccm->cs2cdr);
  1261. reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
  1262. | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
  1263. reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  1264. | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  1265. writel(reg, &mxc_ccm->cs2cdr);
  1266. /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
  1267. reg = readl(&mxc_ccm->cs2cdr);
  1268. reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
  1269. | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
  1270. reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  1271. | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  1272. writel(reg, &mxc_ccm->cs2cdr);
  1273. /* Unbypass pll3_sw_clk */
  1274. reg = readl(&mxc_ccm->ccsr);
  1275. reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
  1276. writel(reg, &mxc_ccm->ccsr);
  1277. /*
  1278. * Set the periph2_clk_sel back to the bottom mux so that
  1279. * mmdc_ch1 is from its original parent.
  1280. */
  1281. reg = readl(&mxc_ccm->cbcdr);
  1282. reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
  1283. writel(reg, &mxc_ccm->cbcdr);
  1284. /* Wait for the clock switch */
  1285. while (readl(&mxc_ccm->cdhipr))
  1286. ;
  1287. /* Clear MMDC_CH1 mask bit */
  1288. reg = readl(&mxc_ccm->ccdr);
  1289. reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
  1290. writel(reg, &mxc_ccm->ccdr);
  1291. enable_ldb_di_clock_sources();
  1292. }
  1293. #endif
  1294. /***************************************************/
  1295. U_BOOT_CMD(
  1296. clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
  1297. "display clocks",
  1298. ""
  1299. );
  1300. #endif