clock.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <asm/io.h>
  11. #include <linux/errno.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <div64.h>
  16. #include <asm/arch/sys_proto.h>
  17. enum pll_clocks {
  18. PLL1_CLOCK = 0,
  19. PLL2_CLOCK,
  20. PLL3_CLOCK,
  21. #ifdef CONFIG_MX53
  22. PLL4_CLOCK,
  23. #endif
  24. PLL_CLOCKS,
  25. };
  26. struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
  27. [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
  28. [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
  29. [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
  30. #ifdef CONFIG_MX53
  31. [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
  32. #endif
  33. };
  34. #define AHB_CLK_ROOT 133333333
  35. #define SZ_DEC_1M 1000000
  36. #define PLL_PD_MAX 16 /* Actual pd+1 */
  37. #define PLL_MFI_MAX 15
  38. #define PLL_MFI_MIN 5
  39. #define ARM_DIV_MAX 8
  40. #define IPG_DIV_MAX 4
  41. #define AHB_DIV_MAX 8
  42. #define EMI_DIV_MAX 8
  43. #define NFC_DIV_MAX 8
  44. #define MX5_CBCMR 0x00015154
  45. #define MX5_CBCDR 0x02888945
  46. struct fixed_pll_mfd {
  47. u32 ref_clk_hz;
  48. u32 mfd;
  49. };
  50. const struct fixed_pll_mfd fixed_mfd[] = {
  51. {MXC_HCLK, 24 * 16},
  52. };
  53. struct pll_param {
  54. u32 pd;
  55. u32 mfi;
  56. u32 mfn;
  57. u32 mfd;
  58. };
  59. #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
  60. #define PLL_FREQ_MIN(ref_clk) \
  61. ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
  62. #define MAX_DDR_CLK 420000000
  63. #define NFC_CLK_MAX 34000000
  64. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
  65. void set_usboh3_clk(void)
  66. {
  67. clrsetbits_le32(&mxc_ccm->cscmr1,
  68. MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
  69. MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
  70. clrsetbits_le32(&mxc_ccm->cscdr1,
  71. MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
  72. MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
  73. MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
  74. MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
  75. }
  76. void enable_usboh3_clk(bool enable)
  77. {
  78. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  79. clrsetbits_le32(&mxc_ccm->CCGR2,
  80. MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
  81. MXC_CCM_CCGR2_USBOH3_60M(cg));
  82. }
  83. #ifdef CONFIG_SYS_I2C_MXC
  84. /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
  85. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  86. {
  87. u32 mask;
  88. #if defined(CONFIG_MX51)
  89. if (i2c_num > 1)
  90. #elif defined(CONFIG_MX53)
  91. if (i2c_num > 2)
  92. #endif
  93. return -EINVAL;
  94. mask = MXC_CCM_CCGR_CG_MASK <<
  95. (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
  96. if (enable)
  97. setbits_le32(&mxc_ccm->CCGR1, mask);
  98. else
  99. clrbits_le32(&mxc_ccm->CCGR1, mask);
  100. return 0;
  101. }
  102. #endif
  103. void set_usb_phy_clk(void)
  104. {
  105. clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
  106. }
  107. #if defined(CONFIG_MX51)
  108. void enable_usb_phy1_clk(bool enable)
  109. {
  110. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  111. clrsetbits_le32(&mxc_ccm->CCGR2,
  112. MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
  113. MXC_CCM_CCGR2_USB_PHY(cg));
  114. }
  115. void enable_usb_phy2_clk(bool enable)
  116. {
  117. /* i.MX51 has a single USB PHY clock, so do nothing here. */
  118. }
  119. #elif defined(CONFIG_MX53)
  120. void enable_usb_phy1_clk(bool enable)
  121. {
  122. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  123. clrsetbits_le32(&mxc_ccm->CCGR4,
  124. MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
  125. MXC_CCM_CCGR4_USB_PHY1(cg));
  126. }
  127. void enable_usb_phy2_clk(bool enable)
  128. {
  129. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  130. clrsetbits_le32(&mxc_ccm->CCGR4,
  131. MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
  132. MXC_CCM_CCGR4_USB_PHY2(cg));
  133. }
  134. #endif
  135. /*
  136. * Calculate the frequency of PLLn.
  137. */
  138. static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
  139. {
  140. uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
  141. uint64_t refclk, temp;
  142. int32_t mfn_abs;
  143. ctrl = readl(&pll->ctrl);
  144. if (ctrl & MXC_DPLLC_CTL_HFSM) {
  145. mfn = readl(&pll->hfs_mfn);
  146. mfd = readl(&pll->hfs_mfd);
  147. op = readl(&pll->hfs_op);
  148. } else {
  149. mfn = readl(&pll->mfn);
  150. mfd = readl(&pll->mfd);
  151. op = readl(&pll->op);
  152. }
  153. mfd &= MXC_DPLLC_MFD_MFD_MASK;
  154. mfn &= MXC_DPLLC_MFN_MFN_MASK;
  155. pdf = op & MXC_DPLLC_OP_PDF_MASK;
  156. mfi = MXC_DPLLC_OP_MFI_RD(op);
  157. /* 21.2.3 */
  158. if (mfi < 5)
  159. mfi = 5;
  160. /* Sign extend */
  161. if (mfn >= 0x04000000) {
  162. mfn |= 0xfc000000;
  163. mfn_abs = -mfn;
  164. } else
  165. mfn_abs = mfn;
  166. refclk = infreq * 2;
  167. if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
  168. refclk *= 2;
  169. do_div(refclk, pdf + 1);
  170. temp = refclk * mfn_abs;
  171. do_div(temp, mfd + 1);
  172. ret = refclk * mfi;
  173. if ((int)mfn < 0)
  174. ret -= temp;
  175. else
  176. ret += temp;
  177. return ret;
  178. }
  179. #ifdef CONFIG_MX51
  180. /*
  181. * This function returns the Frequency Pre-Multiplier clock.
  182. */
  183. static u32 get_fpm(void)
  184. {
  185. u32 mult;
  186. u32 ccr = readl(&mxc_ccm->ccr);
  187. if (ccr & MXC_CCM_CCR_FPM_MULT)
  188. mult = 1024;
  189. else
  190. mult = 512;
  191. return MXC_CLK32 * mult;
  192. }
  193. #endif
  194. /*
  195. * This function returns the low power audio clock.
  196. */
  197. static u32 get_lp_apm(void)
  198. {
  199. u32 ret_val = 0;
  200. u32 ccsr = readl(&mxc_ccm->ccsr);
  201. if (ccsr & MXC_CCM_CCSR_LP_APM)
  202. #if defined(CONFIG_MX51)
  203. ret_val = get_fpm();
  204. #elif defined(CONFIG_MX53)
  205. ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
  206. #endif
  207. else
  208. ret_val = MXC_HCLK;
  209. return ret_val;
  210. }
  211. /*
  212. * Get mcu main rate
  213. */
  214. u32 get_mcu_main_clk(void)
  215. {
  216. u32 reg, freq;
  217. reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
  218. freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  219. return freq / (reg + 1);
  220. }
  221. /*
  222. * Get the rate of peripheral's root clock.
  223. */
  224. u32 get_periph_clk(void)
  225. {
  226. u32 reg;
  227. reg = readl(&mxc_ccm->cbcdr);
  228. if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
  229. return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
  230. reg = readl(&mxc_ccm->cbcmr);
  231. switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
  232. case 0:
  233. return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  234. case 1:
  235. return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
  236. case 2:
  237. return get_lp_apm();
  238. default:
  239. return 0;
  240. }
  241. /* NOTREACHED */
  242. }
  243. /*
  244. * Get the rate of ipg clock.
  245. */
  246. static u32 get_ipg_clk(void)
  247. {
  248. uint32_t freq, reg, div;
  249. freq = get_ahb_clk();
  250. reg = readl(&mxc_ccm->cbcdr);
  251. div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
  252. return freq / div;
  253. }
  254. /*
  255. * Get the rate of ipg_per clock.
  256. */
  257. static u32 get_ipg_per_clk(void)
  258. {
  259. u32 freq, pred1, pred2, podf;
  260. if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
  261. return get_ipg_clk();
  262. if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
  263. freq = get_lp_apm();
  264. else
  265. freq = get_periph_clk();
  266. podf = readl(&mxc_ccm->cbcdr);
  267. pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
  268. pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
  269. podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
  270. return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
  271. }
  272. /* Get the output clock rate of a standard PLL MUX for peripherals. */
  273. static u32 get_standard_pll_sel_clk(u32 clk_sel)
  274. {
  275. u32 freq = 0;
  276. switch (clk_sel & 0x3) {
  277. case 0:
  278. freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  279. break;
  280. case 1:
  281. freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
  282. break;
  283. case 2:
  284. freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
  285. break;
  286. case 3:
  287. freq = get_lp_apm();
  288. break;
  289. }
  290. return freq;
  291. }
  292. /*
  293. * Get the rate of uart clk.
  294. */
  295. static u32 get_uart_clk(void)
  296. {
  297. unsigned int clk_sel, freq, reg, pred, podf;
  298. reg = readl(&mxc_ccm->cscmr1);
  299. clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
  300. freq = get_standard_pll_sel_clk(clk_sel);
  301. reg = readl(&mxc_ccm->cscdr1);
  302. pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
  303. podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
  304. freq /= (pred + 1) * (podf + 1);
  305. return freq;
  306. }
  307. /*
  308. * get cspi clock rate.
  309. */
  310. static u32 imx_get_cspiclk(void)
  311. {
  312. u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
  313. u32 cscmr1 = readl(&mxc_ccm->cscmr1);
  314. u32 cscdr2 = readl(&mxc_ccm->cscdr2);
  315. pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
  316. pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
  317. clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
  318. freq = get_standard_pll_sel_clk(clk_sel);
  319. ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
  320. return ret_val;
  321. }
  322. /*
  323. * get esdhc clock rate.
  324. */
  325. static u32 get_esdhc_clk(u32 port)
  326. {
  327. u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
  328. u32 cscmr1 = readl(&mxc_ccm->cscmr1);
  329. u32 cscdr1 = readl(&mxc_ccm->cscdr1);
  330. switch (port) {
  331. case 0:
  332. clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
  333. pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
  334. podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
  335. break;
  336. case 1:
  337. clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
  338. pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
  339. podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
  340. break;
  341. case 2:
  342. if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
  343. return get_esdhc_clk(1);
  344. else
  345. return get_esdhc_clk(0);
  346. case 3:
  347. if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
  348. return get_esdhc_clk(1);
  349. else
  350. return get_esdhc_clk(0);
  351. default:
  352. break;
  353. }
  354. freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
  355. return freq;
  356. }
  357. static u32 get_axi_a_clk(void)
  358. {
  359. u32 cbcdr = readl(&mxc_ccm->cbcdr);
  360. u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
  361. return get_periph_clk() / (pdf + 1);
  362. }
  363. static u32 get_axi_b_clk(void)
  364. {
  365. u32 cbcdr = readl(&mxc_ccm->cbcdr);
  366. u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
  367. return get_periph_clk() / (pdf + 1);
  368. }
  369. static u32 get_emi_slow_clk(void)
  370. {
  371. u32 cbcdr = readl(&mxc_ccm->cbcdr);
  372. u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
  373. u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
  374. if (emi_clk_sel)
  375. return get_ahb_clk() / (pdf + 1);
  376. return get_periph_clk() / (pdf + 1);
  377. }
  378. static u32 get_ddr_clk(void)
  379. {
  380. u32 ret_val = 0;
  381. u32 cbcmr = readl(&mxc_ccm->cbcmr);
  382. u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
  383. #ifdef CONFIG_MX51
  384. u32 cbcdr = readl(&mxc_ccm->cbcdr);
  385. if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
  386. u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
  387. ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  388. ret_val /= ddr_clk_podf + 1;
  389. return ret_val;
  390. }
  391. #endif
  392. switch (ddr_clk_sel) {
  393. case 0:
  394. ret_val = get_axi_a_clk();
  395. break;
  396. case 1:
  397. ret_val = get_axi_b_clk();
  398. break;
  399. case 2:
  400. ret_val = get_emi_slow_clk();
  401. break;
  402. case 3:
  403. ret_val = get_ahb_clk();
  404. break;
  405. default:
  406. break;
  407. }
  408. return ret_val;
  409. }
  410. /*
  411. * The API of get mxc clocks.
  412. */
  413. unsigned int mxc_get_clock(enum mxc_clock clk)
  414. {
  415. switch (clk) {
  416. case MXC_ARM_CLK:
  417. return get_mcu_main_clk();
  418. case MXC_AHB_CLK:
  419. return get_ahb_clk();
  420. case MXC_IPG_CLK:
  421. return get_ipg_clk();
  422. case MXC_IPG_PERCLK:
  423. case MXC_I2C_CLK:
  424. return get_ipg_per_clk();
  425. case MXC_UART_CLK:
  426. return get_uart_clk();
  427. case MXC_CSPI_CLK:
  428. return imx_get_cspiclk();
  429. case MXC_ESDHC_CLK:
  430. return get_esdhc_clk(0);
  431. case MXC_ESDHC2_CLK:
  432. return get_esdhc_clk(1);
  433. case MXC_ESDHC3_CLK:
  434. return get_esdhc_clk(2);
  435. case MXC_ESDHC4_CLK:
  436. return get_esdhc_clk(3);
  437. case MXC_FEC_CLK:
  438. return get_ipg_clk();
  439. case MXC_SATA_CLK:
  440. return get_ahb_clk();
  441. case MXC_DDR_CLK:
  442. return get_ddr_clk();
  443. default:
  444. break;
  445. }
  446. return -EINVAL;
  447. }
  448. u32 imx_get_uartclk(void)
  449. {
  450. return get_uart_clk();
  451. }
  452. u32 imx_get_fecclk(void)
  453. {
  454. return get_ipg_clk();
  455. }
  456. static int gcd(int m, int n)
  457. {
  458. int t;
  459. while (m > 0) {
  460. if (n > m) {
  461. t = m;
  462. m = n;
  463. n = t;
  464. } /* swap */
  465. m -= n;
  466. }
  467. return n;
  468. }
  469. /*
  470. * This is to calculate various parameters based on reference clock and
  471. * targeted clock based on the equation:
  472. * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
  473. * This calculation is based on a fixed MFD value for simplicity.
  474. */
  475. static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
  476. {
  477. u64 pd, mfi = 1, mfn, mfd, t1;
  478. u32 n_target = target;
  479. u32 n_ref = ref, i;
  480. /*
  481. * Make sure targeted freq is in the valid range.
  482. * Otherwise the following calculation might be wrong!!!
  483. */
  484. if (n_target < PLL_FREQ_MIN(ref) ||
  485. n_target > PLL_FREQ_MAX(ref)) {
  486. printf("Targeted peripheral clock should be"
  487. "within [%d - %d]\n",
  488. PLL_FREQ_MIN(ref) / SZ_DEC_1M,
  489. PLL_FREQ_MAX(ref) / SZ_DEC_1M);
  490. return -EINVAL;
  491. }
  492. for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
  493. if (fixed_mfd[i].ref_clk_hz == ref) {
  494. mfd = fixed_mfd[i].mfd;
  495. break;
  496. }
  497. }
  498. if (i == ARRAY_SIZE(fixed_mfd))
  499. return -EINVAL;
  500. /* Use n_target and n_ref to avoid overflow */
  501. for (pd = 1; pd <= PLL_PD_MAX; pd++) {
  502. t1 = n_target * pd;
  503. do_div(t1, (4 * n_ref));
  504. mfi = t1;
  505. if (mfi > PLL_MFI_MAX)
  506. return -EINVAL;
  507. else if (mfi < 5)
  508. continue;
  509. break;
  510. }
  511. /*
  512. * Now got pd and mfi already
  513. *
  514. * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
  515. */
  516. t1 = n_target * pd;
  517. do_div(t1, 4);
  518. t1 -= n_ref * mfi;
  519. t1 *= mfd;
  520. do_div(t1, n_ref);
  521. mfn = t1;
  522. debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
  523. ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
  524. i = 1;
  525. if (mfn != 0)
  526. i = gcd(mfd, mfn);
  527. pll->pd = (u32)pd;
  528. pll->mfi = (u32)mfi;
  529. do_div(mfn, i);
  530. pll->mfn = (u32)mfn;
  531. do_div(mfd, i);
  532. pll->mfd = (u32)mfd;
  533. return 0;
  534. }
  535. #define calc_div(tgt_clk, src_clk, limit) ({ \
  536. u32 v = 0; \
  537. if (((src_clk) % (tgt_clk)) <= 100) \
  538. v = (src_clk) / (tgt_clk); \
  539. else \
  540. v = ((src_clk) / (tgt_clk)) + 1;\
  541. if (v > limit) \
  542. v = limit; \
  543. (v - 1); \
  544. })
  545. #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
  546. { \
  547. writel(0x1232, &pll->ctrl); \
  548. writel(0x2, &pll->config); \
  549. writel((((pd) - 1) << 0) | ((fi) << 4), \
  550. &pll->op); \
  551. writel(fn, &(pll->mfn)); \
  552. writel((fd) - 1, &pll->mfd); \
  553. writel((((pd) - 1) << 0) | ((fi) << 4), \
  554. &pll->hfs_op); \
  555. writel(fn, &pll->hfs_mfn); \
  556. writel((fd) - 1, &pll->hfs_mfd); \
  557. writel(0x1232, &pll->ctrl); \
  558. while (!readl(&pll->ctrl) & 0x1) \
  559. ;\
  560. }
  561. static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
  562. {
  563. u32 ccsr = readl(&mxc_ccm->ccsr);
  564. struct mxc_pll_reg *pll = mxc_plls[index];
  565. switch (index) {
  566. case PLL1_CLOCK:
  567. /* Switch ARM to PLL2 clock */
  568. writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
  569. &mxc_ccm->ccsr);
  570. CHANGE_PLL_SETTINGS(pll, pll_param->pd,
  571. pll_param->mfi, pll_param->mfn,
  572. pll_param->mfd);
  573. /* Switch back */
  574. writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
  575. &mxc_ccm->ccsr);
  576. break;
  577. case PLL2_CLOCK:
  578. /* Switch to pll2 bypass clock */
  579. writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
  580. &mxc_ccm->ccsr);
  581. CHANGE_PLL_SETTINGS(pll, pll_param->pd,
  582. pll_param->mfi, pll_param->mfn,
  583. pll_param->mfd);
  584. /* Switch back */
  585. writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
  586. &mxc_ccm->ccsr);
  587. break;
  588. case PLL3_CLOCK:
  589. /* Switch to pll3 bypass clock */
  590. writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
  591. &mxc_ccm->ccsr);
  592. CHANGE_PLL_SETTINGS(pll, pll_param->pd,
  593. pll_param->mfi, pll_param->mfn,
  594. pll_param->mfd);
  595. /* Switch back */
  596. writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
  597. &mxc_ccm->ccsr);
  598. break;
  599. #ifdef CONFIG_MX53
  600. case PLL4_CLOCK:
  601. /* Switch to pll4 bypass clock */
  602. writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
  603. &mxc_ccm->ccsr);
  604. CHANGE_PLL_SETTINGS(pll, pll_param->pd,
  605. pll_param->mfi, pll_param->mfn,
  606. pll_param->mfd);
  607. /* Switch back */
  608. writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
  609. &mxc_ccm->ccsr);
  610. break;
  611. #endif
  612. default:
  613. return -EINVAL;
  614. }
  615. return 0;
  616. }
  617. /* Config CPU clock */
  618. static int config_core_clk(u32 ref, u32 freq)
  619. {
  620. int ret = 0;
  621. struct pll_param pll_param;
  622. memset(&pll_param, 0, sizeof(struct pll_param));
  623. /* The case that periph uses PLL1 is not considered here */
  624. ret = calc_pll_params(ref, freq, &pll_param);
  625. if (ret != 0) {
  626. printf("Error:Can't find pll parameters: %d\n", ret);
  627. return ret;
  628. }
  629. return config_pll_clk(PLL1_CLOCK, &pll_param);
  630. }
  631. static int config_nfc_clk(u32 nfc_clk)
  632. {
  633. u32 parent_rate = get_emi_slow_clk();
  634. u32 div;
  635. if (nfc_clk == 0)
  636. return -EINVAL;
  637. div = parent_rate / nfc_clk;
  638. if (div == 0)
  639. div++;
  640. if (parent_rate / div > NFC_CLK_MAX)
  641. div++;
  642. clrsetbits_le32(&mxc_ccm->cbcdr,
  643. MXC_CCM_CBCDR_NFC_PODF_MASK,
  644. MXC_CCM_CBCDR_NFC_PODF(div - 1));
  645. while (readl(&mxc_ccm->cdhipr) != 0)
  646. ;
  647. return 0;
  648. }
  649. void enable_nfc_clk(unsigned char enable)
  650. {
  651. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  652. clrsetbits_le32(&mxc_ccm->CCGR5,
  653. MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
  654. MXC_CCM_CCGR5_EMI_ENFC(cg));
  655. }
  656. #ifdef CONFIG_FSL_IIM
  657. void enable_efuse_prog_supply(bool enable)
  658. {
  659. if (enable)
  660. setbits_le32(&mxc_ccm->cgpr,
  661. MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
  662. else
  663. clrbits_le32(&mxc_ccm->cgpr,
  664. MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
  665. }
  666. #endif
  667. /* Config main_bus_clock for periphs */
  668. static int config_periph_clk(u32 ref, u32 freq)
  669. {
  670. int ret = 0;
  671. struct pll_param pll_param;
  672. memset(&pll_param, 0, sizeof(struct pll_param));
  673. if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
  674. ret = calc_pll_params(ref, freq, &pll_param);
  675. if (ret != 0) {
  676. printf("Error:Can't find pll parameters: %d\n",
  677. ret);
  678. return ret;
  679. }
  680. switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
  681. readl(&mxc_ccm->cbcmr))) {
  682. case 0:
  683. return config_pll_clk(PLL1_CLOCK, &pll_param);
  684. break;
  685. case 1:
  686. return config_pll_clk(PLL3_CLOCK, &pll_param);
  687. break;
  688. default:
  689. return -EINVAL;
  690. }
  691. }
  692. return 0;
  693. }
  694. static int config_ddr_clk(u32 emi_clk)
  695. {
  696. u32 clk_src;
  697. s32 shift = 0, clk_sel, div = 1;
  698. u32 cbcmr = readl(&mxc_ccm->cbcmr);
  699. if (emi_clk > MAX_DDR_CLK) {
  700. printf("Warning:DDR clock should not exceed %d MHz\n",
  701. MAX_DDR_CLK / SZ_DEC_1M);
  702. emi_clk = MAX_DDR_CLK;
  703. }
  704. clk_src = get_periph_clk();
  705. /* Find DDR clock input */
  706. clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
  707. switch (clk_sel) {
  708. case 0:
  709. shift = 16;
  710. break;
  711. case 1:
  712. shift = 19;
  713. break;
  714. case 2:
  715. shift = 22;
  716. break;
  717. case 3:
  718. shift = 10;
  719. break;
  720. default:
  721. return -EINVAL;
  722. }
  723. if ((clk_src % emi_clk) < 10000000)
  724. div = clk_src / emi_clk;
  725. else
  726. div = (clk_src / emi_clk) + 1;
  727. if (div > 8)
  728. div = 8;
  729. clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
  730. while (readl(&mxc_ccm->cdhipr) != 0)
  731. ;
  732. writel(0x0, &mxc_ccm->ccdr);
  733. return 0;
  734. }
  735. #ifdef CONFIG_MX53
  736. static int config_ldb_clk(u32 ref, u32 freq)
  737. {
  738. int ret = 0;
  739. struct pll_param pll_param;
  740. memset(&pll_param, 0, sizeof(struct pll_param));
  741. ret = calc_pll_params(ref, freq, &pll_param);
  742. if (ret != 0) {
  743. printf("Error:Can't find pll parameters: %d\n",
  744. ret);
  745. return ret;
  746. }
  747. return config_pll_clk(PLL4_CLOCK, &pll_param);
  748. }
  749. #else
  750. static int config_ldb_clk(u32 ref, u32 freq)
  751. {
  752. /* Platform not supported */
  753. return -EINVAL;
  754. }
  755. #endif
  756. /*
  757. * This function assumes the expected core clock has to be changed by
  758. * modifying the PLL. This is NOT true always but for most of the times,
  759. * it is. So it assumes the PLL output freq is the same as the expected
  760. * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
  761. * In the latter case, it will try to increase the presc value until
  762. * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
  763. * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
  764. * on the targeted PLL and reference input clock to the PLL. Lastly,
  765. * it sets the register based on these values along with the dividers.
  766. * Note 1) There is no value checking for the passed-in divider values
  767. * so the caller has to make sure those values are sensible.
  768. * 2) Also adjust the NFC divider such that the NFC clock doesn't
  769. * exceed NFC_CLK_MAX.
  770. * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
  771. * 177MHz for higher voltage, this function fixes the max to 133MHz.
  772. * 4) This function should not have allowed diag_printf() calls since
  773. * the serial driver has been stoped. But leave then here to allow
  774. * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
  775. */
  776. int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
  777. {
  778. freq *= SZ_DEC_1M;
  779. switch (clk) {
  780. case MXC_ARM_CLK:
  781. if (config_core_clk(ref, freq))
  782. return -EINVAL;
  783. break;
  784. case MXC_PERIPH_CLK:
  785. if (config_periph_clk(ref, freq))
  786. return -EINVAL;
  787. break;
  788. case MXC_DDR_CLK:
  789. if (config_ddr_clk(freq))
  790. return -EINVAL;
  791. break;
  792. case MXC_NFC_CLK:
  793. if (config_nfc_clk(freq))
  794. return -EINVAL;
  795. break;
  796. case MXC_LDB_CLK:
  797. if (config_ldb_clk(ref, freq))
  798. return -EINVAL;
  799. break;
  800. default:
  801. printf("Warning:Unsupported or invalid clock type\n");
  802. }
  803. return 0;
  804. }
  805. #ifdef CONFIG_MX53
  806. /*
  807. * The clock for the external interface can be set to use internal clock
  808. * if fuse bank 4, row 3, bit 2 is set.
  809. * This is an undocumented feature and it was confirmed by Freescale's support:
  810. * Fuses (but not pins) may be used to configure SATA clocks.
  811. * Particularly the i.MX53 Fuse_Map contains the next information
  812. * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
  813. * '00' - 100MHz (External)
  814. * '01' - 50MHz (External)
  815. * '10' - 120MHz, internal (USB PHY)
  816. * '11' - Reserved
  817. */
  818. void mxc_set_sata_internal_clock(void)
  819. {
  820. u32 *tmp_base =
  821. (u32 *)(IIM_BASE_ADDR + 0x180c);
  822. set_usb_phy_clk();
  823. clrsetbits_le32(tmp_base, 0x6, 0x4);
  824. }
  825. #endif
  826. #ifndef CONFIG_SPL_BUILD
  827. /*
  828. * Dump some core clockes.
  829. */
  830. static int do_mx5_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  831. char *const argv[])
  832. {
  833. u32 freq;
  834. freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  835. printf("PLL1 %8d MHz\n", freq / 1000000);
  836. freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
  837. printf("PLL2 %8d MHz\n", freq / 1000000);
  838. freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
  839. printf("PLL3 %8d MHz\n", freq / 1000000);
  840. #ifdef CONFIG_MX53
  841. freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
  842. printf("PLL4 %8d MHz\n", freq / 1000000);
  843. #endif
  844. printf("\n");
  845. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  846. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  847. printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
  848. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  849. #ifdef CONFIG_MXC_SPI
  850. printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
  851. #endif
  852. return 0;
  853. }
  854. /***************************************************/
  855. U_BOOT_CMD(
  856. clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
  857. "display clocks",
  858. ""
  859. );
  860. #endif