imx_bootaux.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/mach-imx/sys_proto.h>
  8. #include <command.h>
  9. #include <elf.h>
  10. #include <imx_sip.h>
  11. #include <linux/compiler.h>
  12. #include <cpu_func.h>
  13. int arch_auxiliary_core_up(u32 core_id, ulong addr)
  14. {
  15. ulong stack, pc;
  16. if (!addr)
  17. return -EINVAL;
  18. #ifdef CONFIG_IMX8M
  19. stack = *(u32 *)addr;
  20. pc = *(u32 *)(addr + 4);
  21. #else
  22. /*
  23. * handling ELF64 binaries
  24. * isn't supported yet.
  25. */
  26. if (valid_elf_image(addr)) {
  27. stack = 0x0;
  28. pc = load_elf_image_phdr(addr);
  29. if (!pc)
  30. return CMD_RET_FAILURE;
  31. } else {
  32. /*
  33. * Assume binary file with vector table at the beginning.
  34. * Cortex-M4 vector tables start with the stack pointer (SP)
  35. * and reset vector (initial PC).
  36. */
  37. stack = *(u32 *)addr;
  38. pc = *(u32 *)(addr + 4);
  39. }
  40. #endif
  41. printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
  42. stack, pc);
  43. /* Set the stack and pc to M4 bootROM */
  44. writel(stack, M4_BOOTROM_BASE_ADDR);
  45. writel(pc, M4_BOOTROM_BASE_ADDR + 4);
  46. flush_dcache_all();
  47. /* Enable M4 */
  48. #ifdef CONFIG_IMX8M
  49. call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0);
  50. #else
  51. clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
  52. SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
  53. #endif
  54. return 0;
  55. }
  56. int arch_auxiliary_core_check_up(u32 core_id)
  57. {
  58. #ifdef CONFIG_IMX8M
  59. return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0);
  60. #else
  61. unsigned int val;
  62. val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
  63. if (val & SRC_M4C_NON_SCLR_RST_MASK)
  64. return 0; /* assert in reset */
  65. return 1;
  66. #endif
  67. }
  68. /*
  69. * To i.MX6SX and i.MX7D, the image supported by bootaux needs
  70. * the reset vector at the head for the image, with SP and PC
  71. * as the first two words.
  72. *
  73. * Per the cortex-M reference manual, the reset vector of M4 needs
  74. * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
  75. * of that vector. So to boot M4, the A core must build the M4's reset
  76. * vector with getting the PC and SP from image and filling them to
  77. * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
  78. * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
  79. * accessing the M4 TCMUL.
  80. */
  81. static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
  82. char *const argv[])
  83. {
  84. ulong addr;
  85. int ret, up;
  86. if (argc < 2)
  87. return CMD_RET_USAGE;
  88. up = arch_auxiliary_core_check_up(0);
  89. if (up) {
  90. printf("## Auxiliary core is already up\n");
  91. return CMD_RET_SUCCESS;
  92. }
  93. addr = simple_strtoul(argv[1], NULL, 16);
  94. if (!addr)
  95. return CMD_RET_FAILURE;
  96. ret = arch_auxiliary_core_up(0, addr);
  97. if (ret)
  98. return CMD_RET_FAILURE;
  99. return CMD_RET_SUCCESS;
  100. }
  101. U_BOOT_CMD(
  102. bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
  103. "Start auxiliary core",
  104. ""
  105. );