clock_imx8mq.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <errno.h>
  14. #include <linux/iopoll.h>
  15. static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  16. static u32 get_root_clk(enum clk_root_index clock_id);
  17. static u32 decode_frac_pll(enum clk_root_src frac_pll)
  18. {
  19. u32 pll_cfg0, pll_cfg1, pllout;
  20. u32 pll_refclk_sel, pll_refclk;
  21. u32 divr_val, divq_val, divf_val, divff, divfi;
  22. u32 pllout_div_shift, pllout_div_mask, pllout_div;
  23. switch (frac_pll) {
  24. case ARM_PLL_CLK:
  25. pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
  26. pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
  27. pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
  28. pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
  29. break;
  30. default:
  31. printf("Frac PLL %d not supporte\n", frac_pll);
  32. return 0;
  33. }
  34. pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
  35. pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  36. /* Power down */
  37. if (pll_cfg0 & FRAC_PLL_PD_MASK)
  38. return 0;
  39. /* output not enabled */
  40. if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
  41. return 0;
  42. pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
  43. if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
  44. pll_refclk = 25000000u;
  45. else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
  46. pll_refclk = 27000000u;
  47. else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
  48. pll_refclk = 27000000u;
  49. else
  50. pll_refclk = 0;
  51. if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
  52. return pll_refclk;
  53. divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
  54. FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
  55. divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
  56. divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
  57. FRAC_PLL_FRAC_DIV_CTL_SHIFT;
  58. divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
  59. divf_val = 1 + divfi + divff / (1 << 24);
  60. pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
  61. ((divq_val + 1) * 2);
  62. return pllout / (pllout_div + 1);
  63. }
  64. static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
  65. {
  66. u32 pll_cfg0, pll_cfg1, pll_cfg2;
  67. u32 pll_refclk_sel, pll_refclk;
  68. u32 divr1, divr2, divf1, divf2, divq, div;
  69. u32 sse;
  70. u32 pll_clke;
  71. u32 pllout_div_shift, pllout_div_mask, pllout_div;
  72. u32 pllout;
  73. switch (sscg_pll) {
  74. case SYSTEM_PLL1_800M_CLK:
  75. case SYSTEM_PLL1_400M_CLK:
  76. case SYSTEM_PLL1_266M_CLK:
  77. case SYSTEM_PLL1_200M_CLK:
  78. case SYSTEM_PLL1_160M_CLK:
  79. case SYSTEM_PLL1_133M_CLK:
  80. case SYSTEM_PLL1_100M_CLK:
  81. case SYSTEM_PLL1_80M_CLK:
  82. case SYSTEM_PLL1_40M_CLK:
  83. pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
  84. pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
  85. pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
  86. pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
  87. pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
  88. break;
  89. case SYSTEM_PLL2_1000M_CLK:
  90. case SYSTEM_PLL2_500M_CLK:
  91. case SYSTEM_PLL2_333M_CLK:
  92. case SYSTEM_PLL2_250M_CLK:
  93. case SYSTEM_PLL2_200M_CLK:
  94. case SYSTEM_PLL2_166M_CLK:
  95. case SYSTEM_PLL2_125M_CLK:
  96. case SYSTEM_PLL2_100M_CLK:
  97. case SYSTEM_PLL2_50M_CLK:
  98. pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
  99. pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
  100. pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
  101. pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
  102. pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
  103. break;
  104. case SYSTEM_PLL3_CLK:
  105. pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
  106. pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
  107. pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
  108. pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
  109. pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
  110. break;
  111. case DRAM_PLL1_CLK:
  112. pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
  113. pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
  114. pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
  115. pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
  116. pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
  117. break;
  118. default:
  119. printf("sscg pll %d not supporte\n", sscg_pll);
  120. return 0;
  121. }
  122. switch (sscg_pll) {
  123. case DRAM_PLL1_CLK:
  124. pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
  125. div = 1;
  126. break;
  127. case SYSTEM_PLL3_CLK:
  128. pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
  129. div = 1;
  130. break;
  131. case SYSTEM_PLL2_1000M_CLK:
  132. case SYSTEM_PLL1_800M_CLK:
  133. pll_clke = SSCG_PLL_CLKE_MASK;
  134. div = 1;
  135. break;
  136. case SYSTEM_PLL2_500M_CLK:
  137. case SYSTEM_PLL1_400M_CLK:
  138. pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
  139. div = 2;
  140. break;
  141. case SYSTEM_PLL2_333M_CLK:
  142. case SYSTEM_PLL1_266M_CLK:
  143. pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
  144. div = 3;
  145. break;
  146. case SYSTEM_PLL2_250M_CLK:
  147. case SYSTEM_PLL1_200M_CLK:
  148. pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
  149. div = 4;
  150. break;
  151. case SYSTEM_PLL2_200M_CLK:
  152. case SYSTEM_PLL1_160M_CLK:
  153. pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
  154. div = 5;
  155. break;
  156. case SYSTEM_PLL2_166M_CLK:
  157. case SYSTEM_PLL1_133M_CLK:
  158. pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
  159. div = 6;
  160. break;
  161. case SYSTEM_PLL2_125M_CLK:
  162. case SYSTEM_PLL1_100M_CLK:
  163. pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
  164. div = 8;
  165. break;
  166. case SYSTEM_PLL2_100M_CLK:
  167. case SYSTEM_PLL1_80M_CLK:
  168. pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
  169. div = 10;
  170. break;
  171. case SYSTEM_PLL2_50M_CLK:
  172. case SYSTEM_PLL1_40M_CLK:
  173. pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
  174. div = 20;
  175. break;
  176. default:
  177. printf("sscg pll %d not supporte\n", sscg_pll);
  178. return 0;
  179. }
  180. /* Power down */
  181. if (pll_cfg0 & SSCG_PLL_PD_MASK)
  182. return 0;
  183. /* output not enabled */
  184. if ((pll_cfg0 & pll_clke) == 0)
  185. return 0;
  186. pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
  187. pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  188. pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
  189. if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
  190. pll_refclk = 25000000u;
  191. else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
  192. pll_refclk = 27000000u;
  193. else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
  194. pll_refclk = 27000000u;
  195. else
  196. pll_refclk = 0;
  197. /* We assume bypass1/2 are the same value */
  198. if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
  199. (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
  200. return pll_refclk;
  201. divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
  202. SSCG_PLL_REF_DIVR1_SHIFT;
  203. divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
  204. SSCG_PLL_REF_DIVR2_SHIFT;
  205. divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
  206. SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
  207. divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
  208. SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
  209. divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
  210. SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
  211. sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
  212. if (sse)
  213. sse = 8;
  214. else
  215. sse = 2;
  216. pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
  217. (divr2 + 1) * (divf2 + 1) / (divq + 1);
  218. return pllout / (pllout_div + 1) / div;
  219. }
  220. static u32 get_root_src_clk(enum clk_root_src root_src)
  221. {
  222. switch (root_src) {
  223. case OSC_25M_CLK:
  224. return 25000000;
  225. case OSC_27M_CLK:
  226. return 27000000;
  227. case OSC_32K_CLK:
  228. return 32768;
  229. case ARM_PLL_CLK:
  230. return decode_frac_pll(root_src);
  231. case SYSTEM_PLL1_800M_CLK:
  232. case SYSTEM_PLL1_400M_CLK:
  233. case SYSTEM_PLL1_266M_CLK:
  234. case SYSTEM_PLL1_200M_CLK:
  235. case SYSTEM_PLL1_160M_CLK:
  236. case SYSTEM_PLL1_133M_CLK:
  237. case SYSTEM_PLL1_100M_CLK:
  238. case SYSTEM_PLL1_80M_CLK:
  239. case SYSTEM_PLL1_40M_CLK:
  240. case SYSTEM_PLL2_1000M_CLK:
  241. case SYSTEM_PLL2_500M_CLK:
  242. case SYSTEM_PLL2_333M_CLK:
  243. case SYSTEM_PLL2_250M_CLK:
  244. case SYSTEM_PLL2_200M_CLK:
  245. case SYSTEM_PLL2_166M_CLK:
  246. case SYSTEM_PLL2_125M_CLK:
  247. case SYSTEM_PLL2_100M_CLK:
  248. case SYSTEM_PLL2_50M_CLK:
  249. case SYSTEM_PLL3_CLK:
  250. return decode_sscg_pll(root_src);
  251. case ARM_A53_ALT_CLK:
  252. return get_root_clk(ARM_A53_CLK_ROOT);
  253. default:
  254. return 0;
  255. }
  256. return 0;
  257. }
  258. static u32 get_root_clk(enum clk_root_index clock_id)
  259. {
  260. enum clk_root_src root_src;
  261. u32 post_podf, pre_podf, root_src_clk;
  262. if (clock_root_enabled(clock_id) <= 0)
  263. return 0;
  264. if (clock_get_prediv(clock_id, &pre_podf) < 0)
  265. return 0;
  266. if (clock_get_postdiv(clock_id, &post_podf) < 0)
  267. return 0;
  268. if (clock_get_src(clock_id, &root_src) < 0)
  269. return 0;
  270. root_src_clk = get_root_src_clk(root_src);
  271. return root_src_clk / (post_podf + 1) / (pre_podf + 1);
  272. }
  273. #ifdef CONFIG_MXC_OCOTP
  274. void enable_ocotp_clk(unsigned char enable)
  275. {
  276. clock_enable(CCGR_OCOTP, !!enable);
  277. }
  278. #endif
  279. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  280. {
  281. /* 0 - 3 is valid i2c num */
  282. if (i2c_num > 3)
  283. return -EINVAL;
  284. clock_enable(CCGR_I2C1 + i2c_num, !!enable);
  285. return 0;
  286. }
  287. u32 get_arm_core_clk(void)
  288. {
  289. enum clk_root_src root_src;
  290. u32 root_src_clk;
  291. if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
  292. return 0;
  293. root_src_clk = get_root_src_clk(root_src);
  294. return root_src_clk;
  295. }
  296. unsigned int mxc_get_clock(enum mxc_clock clk)
  297. {
  298. u32 val;
  299. switch (clk) {
  300. case MXC_ARM_CLK:
  301. return get_arm_core_clk();
  302. case MXC_IPG_CLK:
  303. clock_get_target_val(IPG_CLK_ROOT, &val);
  304. val = val & 0x3;
  305. return get_root_clk(AHB_CLK_ROOT) / (val + 1);
  306. case MXC_ESDHC_CLK:
  307. return get_root_clk(USDHC1_CLK_ROOT);
  308. case MXC_ESDHC2_CLK:
  309. return get_root_clk(USDHC2_CLK_ROOT);
  310. default:
  311. return get_root_clk(clk);
  312. }
  313. }
  314. u32 imx_get_uartclk(void)
  315. {
  316. return mxc_get_clock(UART1_CLK_ROOT);
  317. }
  318. void mxs_set_lcdclk(u32 base_addr, u32 freq)
  319. {
  320. /*
  321. * LCDIF_PIXEL_CLK: select 800MHz root clock,
  322. * select pre divider 8, output is 100 MHz
  323. */
  324. clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
  325. CLK_ROOT_SOURCE_SEL(4) |
  326. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
  327. }
  328. void init_wdog_clk(void)
  329. {
  330. clock_enable(CCGR_WDOG1, 0);
  331. clock_enable(CCGR_WDOG2, 0);
  332. clock_enable(CCGR_WDOG3, 0);
  333. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  334. CLK_ROOT_SOURCE_SEL(0));
  335. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  336. CLK_ROOT_SOURCE_SEL(0));
  337. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  338. CLK_ROOT_SOURCE_SEL(0));
  339. clock_enable(CCGR_WDOG1, 1);
  340. clock_enable(CCGR_WDOG2, 1);
  341. clock_enable(CCGR_WDOG3, 1);
  342. }
  343. void init_nand_clk(void)
  344. {
  345. clock_enable(CCGR_RAWNAND, 0);
  346. clock_set_target_val(NAND_CLK_ROOT,
  347. CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
  348. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
  349. clock_enable(CCGR_RAWNAND, 1);
  350. }
  351. void init_uart_clk(u32 index)
  352. {
  353. /* Set uart clock root 25M OSC */
  354. switch (index) {
  355. case 0:
  356. clock_enable(CCGR_UART1, 0);
  357. clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
  358. CLK_ROOT_SOURCE_SEL(0));
  359. clock_enable(CCGR_UART1, 1);
  360. return;
  361. case 1:
  362. clock_enable(CCGR_UART2, 0);
  363. clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
  364. CLK_ROOT_SOURCE_SEL(0));
  365. clock_enable(CCGR_UART2, 1);
  366. return;
  367. case 2:
  368. clock_enable(CCGR_UART3, 0);
  369. clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
  370. CLK_ROOT_SOURCE_SEL(0));
  371. clock_enable(CCGR_UART3, 1);
  372. return;
  373. case 3:
  374. clock_enable(CCGR_UART4, 0);
  375. clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
  376. CLK_ROOT_SOURCE_SEL(0));
  377. clock_enable(CCGR_UART4, 1);
  378. return;
  379. default:
  380. printf("Invalid uart index\n");
  381. return;
  382. }
  383. }
  384. void init_clk_usdhc(u32 index)
  385. {
  386. /*
  387. * set usdhc clock root
  388. * sys pll1 400M
  389. */
  390. switch (index) {
  391. case 0:
  392. clock_enable(CCGR_USDHC1, 0);
  393. clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
  394. CLK_ROOT_SOURCE_SEL(1));
  395. clock_enable(CCGR_USDHC1, 1);
  396. return;
  397. case 1:
  398. clock_enable(CCGR_USDHC2, 0);
  399. clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
  400. CLK_ROOT_SOURCE_SEL(1));
  401. clock_enable(CCGR_USDHC2, 1);
  402. return;
  403. default:
  404. printf("Invalid usdhc index\n");
  405. return;
  406. }
  407. }
  408. int set_clk_qspi(void)
  409. {
  410. /*
  411. * set qspi root
  412. * sys pll1 100M
  413. */
  414. clock_enable(CCGR_QSPI, 0);
  415. clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
  416. CLK_ROOT_SOURCE_SEL(7));
  417. clock_enable(CCGR_QSPI, 1);
  418. return 0;
  419. }
  420. #ifdef CONFIG_FEC_MXC
  421. int set_clk_enet(enum enet_freq type)
  422. {
  423. u32 target;
  424. u32 enet1_ref;
  425. switch (type) {
  426. case ENET_125MHZ:
  427. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  428. break;
  429. case ENET_50MHZ:
  430. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  431. break;
  432. case ENET_25MHZ:
  433. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  434. break;
  435. default:
  436. return -EINVAL;
  437. }
  438. /* disable the clock first */
  439. clock_enable(CCGR_ENET1, 0);
  440. clock_enable(CCGR_SIM_ENET, 0);
  441. /* set enet axi clock 266Mhz */
  442. target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
  443. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  444. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  445. clock_set_target_val(ENET_AXI_CLK_ROOT, target);
  446. target = CLK_ROOT_ON | enet1_ref |
  447. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  448. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  449. clock_set_target_val(ENET_REF_CLK_ROOT, target);
  450. target = CLK_ROOT_ON |
  451. ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  452. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  453. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  454. clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
  455. /* enable clock */
  456. clock_enable(CCGR_SIM_ENET, 1);
  457. clock_enable(CCGR_ENET1, 1);
  458. return 0;
  459. }
  460. #endif
  461. u32 imx_get_fecclk(void)
  462. {
  463. return get_root_clk(ENET_AXI_CLK_ROOT);
  464. }
  465. static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
  466. DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
  467. CLK_ROOT_PRE_DIV2),
  468. DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
  469. CLK_ROOT_PRE_DIV2),
  470. DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
  471. CLK_ROOT_PRE_DIV2),
  472. };
  473. void dram_enable_bypass(ulong clk_val)
  474. {
  475. int i;
  476. struct dram_bypass_clk_setting *config;
  477. for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
  478. if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
  479. break;
  480. }
  481. if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
  482. printf("No matched freq table %lu\n", clk_val);
  483. return;
  484. }
  485. config = &imx8mq_dram_bypass_tbl[i];
  486. clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
  487. CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
  488. CLK_ROOT_PRE_DIV(config->alt_pre_div));
  489. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  490. CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
  491. CLK_ROOT_PRE_DIV(config->apb_pre_div));
  492. clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
  493. CLK_ROOT_SOURCE_SEL(1));
  494. }
  495. void dram_disable_bypass(void)
  496. {
  497. clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
  498. CLK_ROOT_SOURCE_SEL(0));
  499. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  500. CLK_ROOT_SOURCE_SEL(4) |
  501. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
  502. }
  503. #ifdef CONFIG_SPL_BUILD
  504. void dram_pll_init(ulong pll_val)
  505. {
  506. u32 val;
  507. void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
  508. void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
  509. /* Bypass */
  510. setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
  511. setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
  512. switch (pll_val) {
  513. case MHZ(800):
  514. val = readl(pll_cfg_reg2);
  515. val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
  516. SSCG_PLL_FEEDBACK_DIV_F2_MASK |
  517. SSCG_PLL_FEEDBACK_DIV_F1_MASK |
  518. SSCG_PLL_REF_DIVR2_MASK);
  519. val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
  520. val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
  521. val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
  522. val |= SSCG_PLL_REF_DIVR2_VAL(29);
  523. writel(val, pll_cfg_reg2);
  524. break;
  525. case MHZ(600):
  526. val = readl(pll_cfg_reg2);
  527. val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
  528. SSCG_PLL_FEEDBACK_DIV_F2_MASK |
  529. SSCG_PLL_FEEDBACK_DIV_F1_MASK |
  530. SSCG_PLL_REF_DIVR2_MASK);
  531. val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
  532. val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
  533. val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
  534. val |= SSCG_PLL_REF_DIVR2_VAL(29);
  535. writel(val, pll_cfg_reg2);
  536. break;
  537. case MHZ(400):
  538. val = readl(pll_cfg_reg2);
  539. val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
  540. SSCG_PLL_FEEDBACK_DIV_F2_MASK |
  541. SSCG_PLL_FEEDBACK_DIV_F1_MASK |
  542. SSCG_PLL_REF_DIVR2_MASK);
  543. val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
  544. val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
  545. val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
  546. val |= SSCG_PLL_REF_DIVR2_VAL(29);
  547. writel(val, pll_cfg_reg2);
  548. break;
  549. case MHZ(167):
  550. val = readl(pll_cfg_reg2);
  551. val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
  552. SSCG_PLL_FEEDBACK_DIV_F2_MASK |
  553. SSCG_PLL_FEEDBACK_DIV_F1_MASK |
  554. SSCG_PLL_REF_DIVR2_MASK);
  555. val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
  556. val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
  557. val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
  558. val |= SSCG_PLL_REF_DIVR2_VAL(30);
  559. writel(val, pll_cfg_reg2);
  560. break;
  561. default:
  562. break;
  563. }
  564. /* Clear power down bit */
  565. clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
  566. /* Eanble ARM_PLL/SYS_PLL */
  567. setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
  568. /* Clear bypass */
  569. clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
  570. __udelay(100);
  571. clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
  572. /* Wait lock */
  573. while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
  574. ;
  575. }
  576. static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
  577. {
  578. void __iomem *pll_cfg0, __iomem *pll_cfg1;
  579. u32 val_cfg0, val_cfg1, divq;
  580. int ret;
  581. switch (pll) {
  582. case ANATOP_ARM_PLL:
  583. pll_cfg0 = &ana_pll->arm_pll_cfg0;
  584. pll_cfg1 = &ana_pll->arm_pll_cfg1;
  585. if (val == FRAC_PLL_OUT_1000M) {
  586. val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
  587. divq = 0;
  588. } else {
  589. val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
  590. divq = 1;
  591. }
  592. val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
  593. FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
  594. FRAC_PLL_REFCLK_DIV_VAL(4) |
  595. FRAC_PLL_OUTPUT_DIV_VAL(divq);
  596. break;
  597. default:
  598. return -EINVAL;
  599. }
  600. /* bypass the clock */
  601. setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
  602. /* Set the value */
  603. writel(val_cfg1, pll_cfg1);
  604. writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
  605. val_cfg0 = readl(pll_cfg0);
  606. /* unbypass the clock */
  607. clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
  608. ret = readl_poll_timeout(pll_cfg0, val_cfg0,
  609. val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
  610. if (ret)
  611. printf("%s timeout\n", __func__);
  612. clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
  613. return 0;
  614. }
  615. int clock_init(void)
  616. {
  617. u32 grade;
  618. clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  619. CLK_ROOT_SOURCE_SEL(0));
  620. /*
  621. * 8MQ only supports two grades: consumer and industrial.
  622. * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
  623. */
  624. grade = get_cpu_temp_grade(NULL, NULL);
  625. if (!grade)
  626. frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
  627. else
  628. frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M);
  629. /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
  630. clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
  631. /*
  632. * According to ANAMIX SPEC
  633. * sys pll1 fixed at 800MHz
  634. * sys pll2 fixed at 1GHz
  635. * Here we only enable the outputs.
  636. */
  637. setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
  638. SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
  639. SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
  640. SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
  641. SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
  642. setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
  643. SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
  644. SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
  645. SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
  646. SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
  647. clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
  648. CLK_ROOT_SOURCE_SEL(1));
  649. init_wdog_clk();
  650. clock_enable(CCGR_TSENSOR, 1);
  651. clock_enable(CCGR_OCOTP, 1);
  652. /* config GIC ROOT to sys_pll2_200m */
  653. clock_enable(CCGR_GIC, 0);
  654. clock_set_target_val(GIC_CLK_ROOT,
  655. CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
  656. clock_enable(CCGR_GIC, 1);
  657. return 0;
  658. }
  659. #endif
  660. /*
  661. * Dump some clockes.
  662. */
  663. #ifndef CONFIG_SPL_BUILD
  664. static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  665. char *const argv[])
  666. {
  667. u32 freq;
  668. freq = decode_frac_pll(ARM_PLL_CLK);
  669. printf("ARM_PLL %8d MHz\n", freq / 1000000);
  670. freq = decode_sscg_pll(DRAM_PLL1_CLK);
  671. printf("DRAM_PLL %8d MHz\n", freq / 1000000);
  672. freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
  673. printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
  674. freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
  675. printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
  676. freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
  677. printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
  678. freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
  679. printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
  680. freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
  681. printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
  682. freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
  683. printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
  684. freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
  685. printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
  686. freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
  687. printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
  688. freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
  689. printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
  690. freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
  691. printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
  692. freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
  693. printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
  694. freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
  695. printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
  696. freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
  697. printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
  698. freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
  699. printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
  700. freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
  701. printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
  702. freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
  703. printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
  704. freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
  705. printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
  706. freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
  707. printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
  708. freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
  709. printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
  710. freq = mxc_get_clock(UART1_CLK_ROOT);
  711. printf("UART1 %8d MHz\n", freq / 1000000);
  712. freq = mxc_get_clock(USDHC1_CLK_ROOT);
  713. printf("USDHC1 %8d MHz\n", freq / 1000000);
  714. freq = mxc_get_clock(QSPI_CLK_ROOT);
  715. printf("QSPI %8d MHz\n", freq / 1000000);
  716. return 0;
  717. }
  718. U_BOOT_CMD(
  719. clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
  720. "display clocks",
  721. ""
  722. );
  723. #endif