emif.h 40 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303
  1. /*
  2. * OMAP44xx EMIF header
  3. *
  4. * Copyright (C) 2009-2010 Texas Instruments, Inc.
  5. *
  6. * Aneesh V <aneesh@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef _EMIF_H_
  13. #define _EMIF_H_
  14. #include <asm/types.h>
  15. #include <asm/io.h>
  16. /* Base address */
  17. #ifndef EMIF1_BASE
  18. #define EMIF1_BASE 0x4c000000
  19. #endif
  20. #define EMIF2_BASE 0x4d000000
  21. #define EMIF_4D 0x4
  22. #define EMIF_4D5 0x5
  23. /* Registers shifts, masks and values */
  24. /* EMIF_MOD_ID_REV */
  25. #define EMIF_REG_SCHEME_SHIFT 30
  26. #define EMIF_REG_SCHEME_MASK (0x3 << 30)
  27. #define EMIF_REG_MODULE_ID_SHIFT 16
  28. #define EMIF_REG_MODULE_ID_MASK (0xfff << 16)
  29. #define EMIF_REG_RTL_VERSION_SHIFT 11
  30. #define EMIF_REG_RTL_VERSION_MASK (0x1f << 11)
  31. #define EMIF_REG_MAJOR_REVISION_SHIFT 8
  32. #define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8)
  33. #define EMIF_REG_MINOR_REVISION_SHIFT 0
  34. #define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0)
  35. /* STATUS */
  36. #define EMIF_REG_BE_SHIFT 31
  37. #define EMIF_REG_BE_MASK (1 << 31)
  38. #define EMIF_REG_DUAL_CLK_MODE_SHIFT 30
  39. #define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30)
  40. #define EMIF_REG_FAST_INIT_SHIFT 29
  41. #define EMIF_REG_FAST_INIT_MASK (1 << 29)
  42. #define EMIF_REG_LEVLING_TO_SHIFT 4
  43. #define EMIF_REG_LEVELING_TO_MASK (7 << 4)
  44. #define EMIF_REG_PHY_DLL_READY_SHIFT 2
  45. #define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
  46. /* SDRAM_CONFIG */
  47. #define EMIF_REG_SDRAM_TYPE_SHIFT 29
  48. #define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29)
  49. #define EMIF_REG_SDRAM_TYPE_DDR1 0
  50. #define EMIF_REG_SDRAM_TYPE_LPDDR1 1
  51. #define EMIF_REG_SDRAM_TYPE_DDR2 2
  52. #define EMIF_REG_SDRAM_TYPE_DDR3 3
  53. #define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4
  54. #define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5
  55. #define EMIF_REG_IBANK_POS_SHIFT 27
  56. #define EMIF_REG_IBANK_POS_MASK (0x3 << 27)
  57. #define EMIF_REG_DDR_TERM_SHIFT 24
  58. #define EMIF_REG_DDR_TERM_MASK (0x7 << 24)
  59. #define EMIF_REG_DDR2_DDQS_SHIFT 23
  60. #define EMIF_REG_DDR2_DDQS_MASK (1 << 23)
  61. #define EMIF_REG_DYN_ODT_SHIFT 21
  62. #define EMIF_REG_DYN_ODT_MASK (0x3 << 21)
  63. #define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20
  64. #define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20)
  65. #define EMIF_REG_SDRAM_DRIVE_SHIFT 18
  66. #define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18)
  67. #define EMIF_REG_CWL_SHIFT 16
  68. #define EMIF_REG_CWL_MASK (0x3 << 16)
  69. #define EMIF_REG_NARROW_MODE_SHIFT 14
  70. #define EMIF_REG_NARROW_MODE_MASK (0x3 << 14)
  71. #define EMIF_REG_CL_SHIFT 10
  72. #define EMIF_REG_CL_MASK (0xf << 10)
  73. #define EMIF_REG_ROWSIZE_SHIFT 7
  74. #define EMIF_REG_ROWSIZE_MASK (0x7 << 7)
  75. #define EMIF_REG_IBANK_SHIFT 4
  76. #define EMIF_REG_IBANK_MASK (0x7 << 4)
  77. #define EMIF_REG_EBANK_SHIFT 3
  78. #define EMIF_REG_EBANK_MASK (1 << 3)
  79. #define EMIF_REG_PAGESIZE_SHIFT 0
  80. #define EMIF_REG_PAGESIZE_MASK (0x7 << 0)
  81. /* SDRAM_CONFIG_2 */
  82. #define EMIF_REG_CS1NVMEN_SHIFT 30
  83. #define EMIF_REG_CS1NVMEN_MASK (1 << 30)
  84. #define EMIF_REG_EBANK_POS_SHIFT 27
  85. #define EMIF_REG_EBANK_POS_MASK (1 << 27)
  86. #define EMIF_REG_RDBNUM_SHIFT 4
  87. #define EMIF_REG_RDBNUM_MASK (0x3 << 4)
  88. #define EMIF_REG_RDBSIZE_SHIFT 0
  89. #define EMIF_REG_RDBSIZE_MASK (0x7 << 0)
  90. /* SDRAM_REF_CTRL */
  91. #define EMIF_REG_INITREF_DIS_SHIFT 31
  92. #define EMIF_REG_INITREF_DIS_MASK (1 << 31)
  93. #define EMIF_REG_SRT_SHIFT 29
  94. #define EMIF_REG_SRT_MASK (1 << 29)
  95. #define EMIF_REG_ASR_SHIFT 28
  96. #define EMIF_REG_ASR_MASK (1 << 28)
  97. #define EMIF_REG_PASR_SHIFT 24
  98. #define EMIF_REG_PASR_MASK (0x7 << 24)
  99. #define EMIF_REG_REFRESH_RATE_SHIFT 0
  100. #define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0)
  101. /* SDRAM_REF_CTRL_SHDW */
  102. #define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0
  103. #define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0)
  104. /* SDRAM_TIM_1 */
  105. #define EMIF_REG_T_RP_SHIFT 25
  106. #define EMIF_REG_T_RP_MASK (0xf << 25)
  107. #define EMIF_REG_T_RCD_SHIFT 21
  108. #define EMIF_REG_T_RCD_MASK (0xf << 21)
  109. #define EMIF_REG_T_WR_SHIFT 17
  110. #define EMIF_REG_T_WR_MASK (0xf << 17)
  111. #define EMIF_REG_T_RAS_SHIFT 12
  112. #define EMIF_REG_T_RAS_MASK (0x1f << 12)
  113. #define EMIF_REG_T_RC_SHIFT 6
  114. #define EMIF_REG_T_RC_MASK (0x3f << 6)
  115. #define EMIF_REG_T_RRD_SHIFT 3
  116. #define EMIF_REG_T_RRD_MASK (0x7 << 3)
  117. #define EMIF_REG_T_WTR_SHIFT 0
  118. #define EMIF_REG_T_WTR_MASK (0x7 << 0)
  119. /* SDRAM_TIM_1_SHDW */
  120. #define EMIF_REG_T_RP_SHDW_SHIFT 25
  121. #define EMIF_REG_T_RP_SHDW_MASK (0xf << 25)
  122. #define EMIF_REG_T_RCD_SHDW_SHIFT 21
  123. #define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21)
  124. #define EMIF_REG_T_WR_SHDW_SHIFT 17
  125. #define EMIF_REG_T_WR_SHDW_MASK (0xf << 17)
  126. #define EMIF_REG_T_RAS_SHDW_SHIFT 12
  127. #define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12)
  128. #define EMIF_REG_T_RC_SHDW_SHIFT 6
  129. #define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6)
  130. #define EMIF_REG_T_RRD_SHDW_SHIFT 3
  131. #define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3)
  132. #define EMIF_REG_T_WTR_SHDW_SHIFT 0
  133. #define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0)
  134. /* SDRAM_TIM_2 */
  135. #define EMIF_REG_T_XP_SHIFT 28
  136. #define EMIF_REG_T_XP_MASK (0x7 << 28)
  137. #define EMIF_REG_T_ODT_SHIFT 25
  138. #define EMIF_REG_T_ODT_MASK (0x7 << 25)
  139. #define EMIF_REG_T_XSNR_SHIFT 16
  140. #define EMIF_REG_T_XSNR_MASK (0x1ff << 16)
  141. #define EMIF_REG_T_XSRD_SHIFT 6
  142. #define EMIF_REG_T_XSRD_MASK (0x3ff << 6)
  143. #define EMIF_REG_T_RTP_SHIFT 3
  144. #define EMIF_REG_T_RTP_MASK (0x7 << 3)
  145. #define EMIF_REG_T_CKE_SHIFT 0
  146. #define EMIF_REG_T_CKE_MASK (0x7 << 0)
  147. /* SDRAM_TIM_2_SHDW */
  148. #define EMIF_REG_T_XP_SHDW_SHIFT 28
  149. #define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28)
  150. #define EMIF_REG_T_ODT_SHDW_SHIFT 25
  151. #define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25)
  152. #define EMIF_REG_T_XSNR_SHDW_SHIFT 16
  153. #define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16)
  154. #define EMIF_REG_T_XSRD_SHDW_SHIFT 6
  155. #define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6)
  156. #define EMIF_REG_T_RTP_SHDW_SHIFT 3
  157. #define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3)
  158. #define EMIF_REG_T_CKE_SHDW_SHIFT 0
  159. #define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0)
  160. /* SDRAM_TIM_3 */
  161. #define EMIF_REG_T_CKESR_SHIFT 21
  162. #define EMIF_REG_T_CKESR_MASK (0x7 << 21)
  163. #define EMIF_REG_ZQ_ZQCS_SHIFT 15
  164. #define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15)
  165. #define EMIF_REG_T_TDQSCKMAX_SHIFT 13
  166. #define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13)
  167. #define EMIF_REG_T_RFC_SHIFT 4
  168. #define EMIF_REG_T_RFC_MASK (0x1ff << 4)
  169. #define EMIF_REG_T_RAS_MAX_SHIFT 0
  170. #define EMIF_REG_T_RAS_MAX_MASK (0xf << 0)
  171. /* SDRAM_TIM_3_SHDW */
  172. #define EMIF_REG_T_CKESR_SHDW_SHIFT 21
  173. #define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21)
  174. #define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15
  175. #define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15)
  176. #define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13
  177. #define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13)
  178. #define EMIF_REG_T_RFC_SHDW_SHIFT 4
  179. #define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4)
  180. #define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0
  181. #define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0)
  182. /* LPDDR2_NVM_TIM */
  183. #define EMIF_REG_NVM_T_XP_SHIFT 28
  184. #define EMIF_REG_NVM_T_XP_MASK (0x7 << 28)
  185. #define EMIF_REG_NVM_T_WTR_SHIFT 24
  186. #define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24)
  187. #define EMIF_REG_NVM_T_RP_SHIFT 20
  188. #define EMIF_REG_NVM_T_RP_MASK (0xf << 20)
  189. #define EMIF_REG_NVM_T_WRA_SHIFT 16
  190. #define EMIF_REG_NVM_T_WRA_MASK (0xf << 16)
  191. #define EMIF_REG_NVM_T_RRD_SHIFT 8
  192. #define EMIF_REG_NVM_T_RRD_MASK (0xff << 8)
  193. #define EMIF_REG_NVM_T_RCDMIN_SHIFT 0
  194. #define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0)
  195. /* LPDDR2_NVM_TIM_SHDW */
  196. #define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28
  197. #define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28)
  198. #define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24
  199. #define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24)
  200. #define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20
  201. #define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20)
  202. #define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16
  203. #define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16)
  204. #define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8
  205. #define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8)
  206. #define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0
  207. #define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0)
  208. /* PWR_MGMT_CTRL */
  209. #define EMIF_REG_IDLEMODE_SHIFT 30
  210. #define EMIF_REG_IDLEMODE_MASK (0x3 << 30)
  211. #define EMIF_REG_PD_TIM_SHIFT 12
  212. #define EMIF_REG_PD_TIM_MASK (0xf << 12)
  213. #define EMIF_REG_DPD_EN_SHIFT 11
  214. #define EMIF_REG_DPD_EN_MASK (1 << 11)
  215. #define EMIF_REG_LP_MODE_SHIFT 8
  216. #define EMIF_REG_LP_MODE_MASK (0x7 << 8)
  217. #define EMIF_REG_SR_TIM_SHIFT 4
  218. #define EMIF_REG_SR_TIM_MASK (0xf << 4)
  219. #define EMIF_REG_CS_TIM_SHIFT 0
  220. #define EMIF_REG_CS_TIM_MASK (0xf << 0)
  221. /* PWR_MGMT_CTRL_SHDW */
  222. #define EMIF_REG_PD_TIM_SHDW_SHIFT 12
  223. #define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12)
  224. #define EMIF_REG_SR_TIM_SHDW_SHIFT 4
  225. #define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4)
  226. #define EMIF_REG_CS_TIM_SHDW_SHIFT 0
  227. #define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0)
  228. /* LPDDR2_MODE_REG_DATA */
  229. #define EMIF_REG_VALUE_0_SHIFT 0
  230. #define EMIF_REG_VALUE_0_MASK (0x7f << 0)
  231. /* LPDDR2_MODE_REG_CFG */
  232. #define EMIF_REG_CS_SHIFT 31
  233. #define EMIF_REG_CS_MASK (1 << 31)
  234. #define EMIF_REG_REFRESH_EN_SHIFT 30
  235. #define EMIF_REG_REFRESH_EN_MASK (1 << 30)
  236. #define EMIF_REG_ADDRESS_SHIFT 0
  237. #define EMIF_REG_ADDRESS_MASK (0xff << 0)
  238. /* OCP_CONFIG */
  239. #define EMIF_REG_SYS_THRESH_MAX_SHIFT 24
  240. #define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24)
  241. #define EMIF_REG_MPU_THRESH_MAX_SHIFT 20
  242. #define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20)
  243. #define EMIF_REG_LL_THRESH_MAX_SHIFT 16
  244. #define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16)
  245. #define EMIF_REG_PR_OLD_COUNT_SHIFT 0
  246. #define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0)
  247. /* OCP_CFG_VAL_1 */
  248. #define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30
  249. #define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30)
  250. #define EMIF_REG_LL_BUS_WIDTH_SHIFT 28
  251. #define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28)
  252. #define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8
  253. #define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8)
  254. #define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0
  255. #define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0)
  256. /* OCP_CFG_VAL_2 */
  257. #define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16
  258. #define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16)
  259. #define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8
  260. #define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8)
  261. #define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0
  262. #define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0)
  263. /* IODFT_TLGC */
  264. #define EMIF_REG_TLEC_SHIFT 16
  265. #define EMIF_REG_TLEC_MASK (0xffff << 16)
  266. #define EMIF_REG_MT_SHIFT 14
  267. #define EMIF_REG_MT_MASK (1 << 14)
  268. #define EMIF_REG_ACT_CAP_EN_SHIFT 13
  269. #define EMIF_REG_ACT_CAP_EN_MASK (1 << 13)
  270. #define EMIF_REG_OPG_LD_SHIFT 12
  271. #define EMIF_REG_OPG_LD_MASK (1 << 12)
  272. #define EMIF_REG_RESET_PHY_SHIFT 10
  273. #define EMIF_REG_RESET_PHY_MASK (1 << 10)
  274. #define EMIF_REG_MMS_SHIFT 8
  275. #define EMIF_REG_MMS_MASK (1 << 8)
  276. #define EMIF_REG_MC_SHIFT 4
  277. #define EMIF_REG_MC_MASK (0x3 << 4)
  278. #define EMIF_REG_PC_SHIFT 1
  279. #define EMIF_REG_PC_MASK (0x7 << 1)
  280. #define EMIF_REG_TM_SHIFT 0
  281. #define EMIF_REG_TM_MASK (1 << 0)
  282. /* IODFT_CTRL_MISR_RSLT */
  283. #define EMIF_REG_DQM_TLMR_SHIFT 16
  284. #define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16)
  285. #define EMIF_REG_CTL_TLMR_SHIFT 0
  286. #define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0)
  287. /* IODFT_ADDR_MISR_RSLT */
  288. #define EMIF_REG_ADDR_TLMR_SHIFT 0
  289. #define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0)
  290. /* IODFT_DATA_MISR_RSLT_1 */
  291. #define EMIF_REG_DATA_TLMR_31_0_SHIFT 0
  292. #define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0)
  293. /* IODFT_DATA_MISR_RSLT_2 */
  294. #define EMIF_REG_DATA_TLMR_63_32_SHIFT 0
  295. #define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0)
  296. /* IODFT_DATA_MISR_RSLT_3 */
  297. #define EMIF_REG_DATA_TLMR_66_64_SHIFT 0
  298. #define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0)
  299. /* PERF_CNT_1 */
  300. #define EMIF_REG_COUNTER1_SHIFT 0
  301. #define EMIF_REG_COUNTER1_MASK (0xffffffff << 0)
  302. /* PERF_CNT_2 */
  303. #define EMIF_REG_COUNTER2_SHIFT 0
  304. #define EMIF_REG_COUNTER2_MASK (0xffffffff << 0)
  305. /* PERF_CNT_CFG */
  306. #define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31
  307. #define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31)
  308. #define EMIF_REG_CNTR2_REGION_EN_SHIFT 30
  309. #define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30)
  310. #define EMIF_REG_CNTR2_CFG_SHIFT 16
  311. #define EMIF_REG_CNTR2_CFG_MASK (0xf << 16)
  312. #define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15
  313. #define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15)
  314. #define EMIF_REG_CNTR1_REGION_EN_SHIFT 14
  315. #define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14)
  316. #define EMIF_REG_CNTR1_CFG_SHIFT 0
  317. #define EMIF_REG_CNTR1_CFG_MASK (0xf << 0)
  318. /* PERF_CNT_SEL */
  319. #define EMIF_REG_MCONNID2_SHIFT 24
  320. #define EMIF_REG_MCONNID2_MASK (0xff << 24)
  321. #define EMIF_REG_REGION_SEL2_SHIFT 16
  322. #define EMIF_REG_REGION_SEL2_MASK (0x3 << 16)
  323. #define EMIF_REG_MCONNID1_SHIFT 8
  324. #define EMIF_REG_MCONNID1_MASK (0xff << 8)
  325. #define EMIF_REG_REGION_SEL1_SHIFT 0
  326. #define EMIF_REG_REGION_SEL1_MASK (0x3 << 0)
  327. /* PERF_CNT_TIM */
  328. #define EMIF_REG_TOTAL_TIME_SHIFT 0
  329. #define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0)
  330. /* READ_IDLE_CTRL */
  331. #define EMIF_REG_READ_IDLE_LEN_SHIFT 16
  332. #define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16)
  333. #define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0
  334. #define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0)
  335. /* READ_IDLE_CTRL_SHDW */
  336. #define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16
  337. #define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16)
  338. #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0
  339. #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0)
  340. /* IRQ_EOI */
  341. #define EMIF_REG_EOI_SHIFT 0
  342. #define EMIF_REG_EOI_MASK (1 << 0)
  343. /* IRQSTATUS_RAW_SYS */
  344. #define EMIF_REG_DNV_SYS_SHIFT 2
  345. #define EMIF_REG_DNV_SYS_MASK (1 << 2)
  346. #define EMIF_REG_TA_SYS_SHIFT 1
  347. #define EMIF_REG_TA_SYS_MASK (1 << 1)
  348. #define EMIF_REG_ERR_SYS_SHIFT 0
  349. #define EMIF_REG_ERR_SYS_MASK (1 << 0)
  350. /* IRQSTATUS_RAW_LL */
  351. #define EMIF_REG_DNV_LL_SHIFT 2
  352. #define EMIF_REG_DNV_LL_MASK (1 << 2)
  353. #define EMIF_REG_TA_LL_SHIFT 1
  354. #define EMIF_REG_TA_LL_MASK (1 << 1)
  355. #define EMIF_REG_ERR_LL_SHIFT 0
  356. #define EMIF_REG_ERR_LL_MASK (1 << 0)
  357. /* IRQSTATUS_SYS */
  358. /* IRQSTATUS_LL */
  359. /* IRQENABLE_SET_SYS */
  360. #define EMIF_REG_EN_DNV_SYS_SHIFT 2
  361. #define EMIF_REG_EN_DNV_SYS_MASK (1 << 2)
  362. #define EMIF_REG_EN_TA_SYS_SHIFT 1
  363. #define EMIF_REG_EN_TA_SYS_MASK (1 << 1)
  364. #define EMIF_REG_EN_ERR_SYS_SHIFT 0
  365. #define EMIF_REG_EN_ERR_SYS_MASK (1 << 0)
  366. /* IRQENABLE_SET_LL */
  367. #define EMIF_REG_EN_DNV_LL_SHIFT 2
  368. #define EMIF_REG_EN_DNV_LL_MASK (1 << 2)
  369. #define EMIF_REG_EN_TA_LL_SHIFT 1
  370. #define EMIF_REG_EN_TA_LL_MASK (1 << 1)
  371. #define EMIF_REG_EN_ERR_LL_SHIFT 0
  372. #define EMIF_REG_EN_ERR_LL_MASK (1 << 0)
  373. /* IRQENABLE_CLR_SYS */
  374. /* IRQENABLE_CLR_LL */
  375. /* ZQ_CONFIG */
  376. #define EMIF_REG_ZQ_CS1EN_SHIFT 31
  377. #define EMIF_REG_ZQ_CS1EN_MASK (1 << 31)
  378. #define EMIF_REG_ZQ_CS0EN_SHIFT 30
  379. #define EMIF_REG_ZQ_CS0EN_MASK (1 << 30)
  380. #define EMIF_REG_ZQ_DUALCALEN_SHIFT 29
  381. #define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29)
  382. #define EMIF_REG_ZQ_SFEXITEN_SHIFT 28
  383. #define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28)
  384. #define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18
  385. #define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18)
  386. #define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16
  387. #define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16)
  388. #define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0
  389. #define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0)
  390. /* TEMP_ALERT_CONFIG */
  391. #define EMIF_REG_TA_CS1EN_SHIFT 31
  392. #define EMIF_REG_TA_CS1EN_MASK (1 << 31)
  393. #define EMIF_REG_TA_CS0EN_SHIFT 30
  394. #define EMIF_REG_TA_CS0EN_MASK (1 << 30)
  395. #define EMIF_REG_TA_SFEXITEN_SHIFT 28
  396. #define EMIF_REG_TA_SFEXITEN_MASK (1 << 28)
  397. #define EMIF_REG_TA_DEVWDT_SHIFT 26
  398. #define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26)
  399. #define EMIF_REG_TA_DEVCNT_SHIFT 24
  400. #define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24)
  401. #define EMIF_REG_TA_REFINTERVAL_SHIFT 0
  402. #define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0)
  403. /* OCP_ERR_LOG */
  404. #define EMIF_REG_MADDRSPACE_SHIFT 14
  405. #define EMIF_REG_MADDRSPACE_MASK (0x3 << 14)
  406. #define EMIF_REG_MBURSTSEQ_SHIFT 11
  407. #define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11)
  408. #define EMIF_REG_MCMD_SHIFT 8
  409. #define EMIF_REG_MCMD_MASK (0x7 << 8)
  410. #define EMIF_REG_MCONNID_SHIFT 0
  411. #define EMIF_REG_MCONNID_MASK (0xff << 0)
  412. /* DDR_PHY_CTRL_1 */
  413. #define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4
  414. #define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4)
  415. #define EMIF_REG_READ_LATENCY_SHIFT 0
  416. #define EMIF_REG_READ_LATENCY_MASK (0xf << 0)
  417. #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4
  418. #define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4)
  419. #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12
  420. #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12)
  421. /* DDR_PHY_CTRL_1_SHDW */
  422. #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4
  423. #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4)
  424. #define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0
  425. #define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0)
  426. #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4
  427. #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4)
  428. #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
  429. #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12)
  430. #define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT 25
  431. #define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK (1 << 25)
  432. #define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT 26
  433. #define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK (1 << 26)
  434. #define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT 27
  435. #define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK (1 << 27)
  436. /* DDR_PHY_CTRL_2 */
  437. #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0
  438. #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0)
  439. /*EMIF_READ_WRITE_LEVELING_CONTROL*/
  440. #define EMIF_REG_RDWRLVLFULL_START_SHIFT 31
  441. #define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31)
  442. #define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24
  443. #define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24)
  444. #define EMIF_REG_RDLVLINC_INT_SHIFT 16
  445. #define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16)
  446. #define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8
  447. #define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8)
  448. #define EMIF_REG_WRLVLINC_INT_SHIFT 0
  449. #define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0)
  450. /*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
  451. #define EMIF_REG_RDWRLVL_EN_SHIFT 31
  452. #define EMIF_REG_RDWRLVL_EN_MASK (1 << 31)
  453. #define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24
  454. #define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24)
  455. #define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16
  456. #define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16)
  457. #define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8
  458. #define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8)
  459. #define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0
  460. #define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0)
  461. /*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
  462. #define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
  463. #define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
  464. /* EMIF_PHY_CTRL_36 */
  465. #define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8)
  466. #define PHY_RDDQS_RATIO_REGS 5
  467. #define PHY_FIFO_WE_SLAVE_RATIO_REGS 5
  468. #define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10
  469. /*Leveling Fields */
  470. #define DDR3_WR_LVL_INT 0x73
  471. #define DDR3_RD_LVL_INT 0x33
  472. #define DDR3_RD_LVL_GATE_INT 0x59
  473. #define RD_RW_LVL_INC_PRE 0x0
  474. #define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT)
  475. #define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \
  476. | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
  477. | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \
  478. | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
  479. #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7
  480. #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7
  481. #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
  482. /* DMM */
  483. #define DMM_BASE 0x4E000040
  484. /* Memory Adapter */
  485. #define MA_BASE 0x482AF040
  486. #define MA_PRIORITY 0x482A2000
  487. #define MA_HIMEM_INTERLEAVE_UN_SHIFT 8
  488. #define MA_HIMEM_INTERLEAVE_UN_MASK (1 << 8)
  489. /* DMM_LISA_MAP */
  490. #define EMIF_SYS_ADDR_SHIFT 24
  491. #define EMIF_SYS_ADDR_MASK (0xff << 24)
  492. #define EMIF_SYS_SIZE_SHIFT 20
  493. #define EMIF_SYS_SIZE_MASK (0x7 << 20)
  494. #define EMIF_SDRC_INTL_SHIFT 18
  495. #define EMIF_SDRC_INTL_MASK (0x3 << 18)
  496. #define EMIF_SDRC_ADDRSPC_SHIFT 16
  497. #define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16)
  498. #define EMIF_SDRC_MAP_SHIFT 8
  499. #define EMIF_SDRC_MAP_MASK (0x3 << 8)
  500. #define EMIF_SDRC_ADDR_SHIFT 0
  501. #define EMIF_SDRC_ADDR_MASK (0xff << 0)
  502. /* DMM_LISA_MAP fields */
  503. #define DMM_SDRC_MAP_UNMAPPED 0
  504. #define DMM_SDRC_MAP_EMIF1_ONLY 1
  505. #define DMM_SDRC_MAP_EMIF2_ONLY 2
  506. #define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3
  507. #define DMM_SDRC_INTL_NONE 0
  508. #define DMM_SDRC_INTL_128B 1
  509. #define DMM_SDRC_INTL_256B 2
  510. #define DMM_SDRC_INTL_512 3
  511. #define DMM_SDRC_ADDR_SPC_SDRAM 0
  512. #define DMM_SDRC_ADDR_SPC_NVM 1
  513. #define DMM_SDRC_ADDR_SPC_INVALID 2
  514. #define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\
  515. (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
  516. (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
  517. (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
  518. (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
  519. #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
  520. (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
  521. (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
  522. (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
  523. #define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\
  524. (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\
  525. (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
  526. (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
  527. /* Trap for invalid TILER PAT entries */
  528. #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\
  529. (0 << EMIF_SDRC_ADDR_SHIFT) |\
  530. (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
  531. (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\
  532. (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\
  533. (0xFF << EMIF_SYS_ADDR_SHIFT))
  534. #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
  535. /* EMIF ECC CTRL reg */
  536. #define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT 31
  537. #define EMIF_ECC_CTRL_REG_ECC_EN_MASK (1 << 31)
  538. #define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT 30
  539. #define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK (1 << 30)
  540. #define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT 29
  541. #define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK (1 << 29)
  542. #define EMIF_ECC_REG_RMW_EN_SHIFT 28
  543. #define EMIF_ECC_REG_RMW_EN_MASK (1 << 28)
  544. #define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT 1
  545. #define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK (1 << 1)
  546. #define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT 0
  547. #define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK (1 << 0)
  548. /* EMIF ECC ADDRESS RANGE */
  549. #define EMIF_ECC_REG_ECC_END_ADDR_SHIFT 16
  550. #define EMIF_ECC_REG_ECC_END_ADDR_MASK (0xffff << 16)
  551. #define EMIF_ECC_REG_ECC_START_ADDR_SHIFT 0
  552. #define EMIF_ECC_REG_ECC_START_ADDR_MASK (0xffff << 0)
  553. /* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */
  554. #define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT 5
  555. #define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK (1 << 5)
  556. #define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT 4
  557. #define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK (1 << 4)
  558. #define EMIF_INT_WR_ECC_ERR_SYS_SHIFT 3
  559. #define EMIF_INT_WR_ECC_ERR_SYS_MASK (1 << 3)
  560. /* Reg mapping structure */
  561. struct emif_reg_struct {
  562. u32 emif_mod_id_rev;
  563. u32 emif_status;
  564. u32 emif_sdram_config;
  565. u32 emif_lpddr2_nvm_config;
  566. u32 emif_sdram_ref_ctrl;
  567. u32 emif_sdram_ref_ctrl_shdw;
  568. u32 emif_sdram_tim_1;
  569. u32 emif_sdram_tim_1_shdw;
  570. u32 emif_sdram_tim_2;
  571. u32 emif_sdram_tim_2_shdw;
  572. u32 emif_sdram_tim_3;
  573. u32 emif_sdram_tim_3_shdw;
  574. u32 emif_lpddr2_nvm_tim;
  575. u32 emif_lpddr2_nvm_tim_shdw;
  576. u32 emif_pwr_mgmt_ctrl;
  577. u32 emif_pwr_mgmt_ctrl_shdw;
  578. u32 emif_lpddr2_mode_reg_data;
  579. u32 padding1[1];
  580. u32 emif_lpddr2_mode_reg_data_es2;
  581. u32 padding11[1];
  582. u32 emif_lpddr2_mode_reg_cfg;
  583. u32 emif_l3_config;
  584. u32 emif_l3_cfg_val_1;
  585. u32 emif_l3_cfg_val_2;
  586. u32 emif_iodft_tlgc;
  587. u32 padding2[7];
  588. u32 emif_perf_cnt_1;
  589. u32 emif_perf_cnt_2;
  590. u32 emif_perf_cnt_cfg;
  591. u32 emif_perf_cnt_sel;
  592. u32 emif_perf_cnt_tim;
  593. u32 padding3;
  594. u32 emif_read_idlectrl;
  595. u32 emif_read_idlectrl_shdw;
  596. u32 padding4;
  597. u32 emif_irqstatus_raw_sys;
  598. u32 emif_irqstatus_raw_ll;
  599. u32 emif_irqstatus_sys;
  600. u32 emif_irqstatus_ll;
  601. u32 emif_irqenable_set_sys;
  602. u32 emif_irqenable_set_ll;
  603. u32 emif_irqenable_clr_sys;
  604. u32 emif_irqenable_clr_ll;
  605. u32 padding5;
  606. u32 emif_zq_config;
  607. u32 emif_temp_alert_config;
  608. u32 emif_l3_err_log;
  609. u32 emif_rd_wr_lvl_rmp_win;
  610. u32 emif_rd_wr_lvl_rmp_ctl;
  611. u32 emif_rd_wr_lvl_ctl;
  612. u32 padding6[1];
  613. u32 emif_ddr_phy_ctrl_1;
  614. u32 emif_ddr_phy_ctrl_1_shdw;
  615. u32 emif_ddr_phy_ctrl_2;
  616. u32 padding7[4];
  617. u32 emif_prio_class_serv_map;
  618. u32 emif_connect_id_serv_1_map;
  619. u32 emif_connect_id_serv_2_map;
  620. u32 padding8;
  621. u32 emif_ecc_ctrl_reg;
  622. u32 emif_ecc_address_range_1;
  623. u32 emif_ecc_address_range_2;
  624. u32 padding8_1;
  625. u32 emif_rd_wr_exec_thresh;
  626. u32 emif_cos_config;
  627. #if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE)
  628. u32 padding9[2];
  629. u32 emif_1b_ecc_err_cnt;
  630. u32 emif_1b_ecc_err_thrush;
  631. u32 emif_1b_ecc_err_dist_1;
  632. u32 emif_1b_ecc_err_addr_log;
  633. u32 emif_2b_ecc_err_addr_log;
  634. u32 emif_ddr_phy_status[28];
  635. u32 padding10[19];
  636. #else
  637. u32 padding9[6];
  638. u32 emif_ddr_phy_status[28];
  639. u32 padding10[20];
  640. #endif
  641. u32 emif_ddr_ext_phy_ctrl_1;
  642. u32 emif_ddr_ext_phy_ctrl_1_shdw;
  643. u32 emif_ddr_ext_phy_ctrl_2;
  644. u32 emif_ddr_ext_phy_ctrl_2_shdw;
  645. u32 emif_ddr_ext_phy_ctrl_3;
  646. u32 emif_ddr_ext_phy_ctrl_3_shdw;
  647. u32 emif_ddr_ext_phy_ctrl_4;
  648. u32 emif_ddr_ext_phy_ctrl_4_shdw;
  649. u32 emif_ddr_ext_phy_ctrl_5;
  650. u32 emif_ddr_ext_phy_ctrl_5_shdw;
  651. u32 emif_ddr_ext_phy_ctrl_6;
  652. u32 emif_ddr_ext_phy_ctrl_6_shdw;
  653. u32 emif_ddr_ext_phy_ctrl_7;
  654. u32 emif_ddr_ext_phy_ctrl_7_shdw;
  655. u32 emif_ddr_ext_phy_ctrl_8;
  656. u32 emif_ddr_ext_phy_ctrl_8_shdw;
  657. u32 emif_ddr_ext_phy_ctrl_9;
  658. u32 emif_ddr_ext_phy_ctrl_9_shdw;
  659. u32 emif_ddr_ext_phy_ctrl_10;
  660. u32 emif_ddr_ext_phy_ctrl_10_shdw;
  661. u32 emif_ddr_ext_phy_ctrl_11;
  662. u32 emif_ddr_ext_phy_ctrl_11_shdw;
  663. u32 emif_ddr_ext_phy_ctrl_12;
  664. u32 emif_ddr_ext_phy_ctrl_12_shdw;
  665. u32 emif_ddr_ext_phy_ctrl_13;
  666. u32 emif_ddr_ext_phy_ctrl_13_shdw;
  667. u32 emif_ddr_ext_phy_ctrl_14;
  668. u32 emif_ddr_ext_phy_ctrl_14_shdw;
  669. u32 emif_ddr_ext_phy_ctrl_15;
  670. u32 emif_ddr_ext_phy_ctrl_15_shdw;
  671. u32 emif_ddr_ext_phy_ctrl_16;
  672. u32 emif_ddr_ext_phy_ctrl_16_shdw;
  673. u32 emif_ddr_ext_phy_ctrl_17;
  674. u32 emif_ddr_ext_phy_ctrl_17_shdw;
  675. u32 emif_ddr_ext_phy_ctrl_18;
  676. u32 emif_ddr_ext_phy_ctrl_18_shdw;
  677. u32 emif_ddr_ext_phy_ctrl_19;
  678. u32 emif_ddr_ext_phy_ctrl_19_shdw;
  679. u32 emif_ddr_ext_phy_ctrl_20;
  680. u32 emif_ddr_ext_phy_ctrl_20_shdw;
  681. u32 emif_ddr_ext_phy_ctrl_21;
  682. u32 emif_ddr_ext_phy_ctrl_21_shdw;
  683. u32 emif_ddr_ext_phy_ctrl_22;
  684. u32 emif_ddr_ext_phy_ctrl_22_shdw;
  685. u32 emif_ddr_ext_phy_ctrl_23;
  686. u32 emif_ddr_ext_phy_ctrl_23_shdw;
  687. u32 emif_ddr_ext_phy_ctrl_24;
  688. u32 emif_ddr_ext_phy_ctrl_24_shdw;
  689. u32 emif_ddr_ext_phy_ctrl_25;
  690. u32 emif_ddr_ext_phy_ctrl_25_shdw;
  691. u32 emif_ddr_ext_phy_ctrl_26;
  692. u32 emif_ddr_ext_phy_ctrl_26_shdw;
  693. u32 emif_ddr_ext_phy_ctrl_27;
  694. u32 emif_ddr_ext_phy_ctrl_27_shdw;
  695. u32 emif_ddr_ext_phy_ctrl_28;
  696. u32 emif_ddr_ext_phy_ctrl_28_shdw;
  697. u32 emif_ddr_ext_phy_ctrl_29;
  698. u32 emif_ddr_ext_phy_ctrl_29_shdw;
  699. u32 emif_ddr_ext_phy_ctrl_30;
  700. u32 emif_ddr_ext_phy_ctrl_30_shdw;
  701. u32 emif_ddr_ext_phy_ctrl_31;
  702. u32 emif_ddr_ext_phy_ctrl_31_shdw;
  703. u32 emif_ddr_ext_phy_ctrl_32;
  704. u32 emif_ddr_ext_phy_ctrl_32_shdw;
  705. u32 emif_ddr_ext_phy_ctrl_33;
  706. u32 emif_ddr_ext_phy_ctrl_33_shdw;
  707. u32 emif_ddr_ext_phy_ctrl_34;
  708. u32 emif_ddr_ext_phy_ctrl_34_shdw;
  709. u32 emif_ddr_ext_phy_ctrl_35;
  710. u32 emif_ddr_ext_phy_ctrl_35_shdw;
  711. union {
  712. u32 emif_ddr_ext_phy_ctrl_36;
  713. u32 emif_ddr_fifo_misaligned_clear_1;
  714. };
  715. union {
  716. u32 emif_ddr_ext_phy_ctrl_36_shdw;
  717. u32 emif_ddr_fifo_misaligned_clear_2;
  718. };
  719. };
  720. struct dmm_lisa_map_regs {
  721. u32 dmm_lisa_map_0;
  722. u32 dmm_lisa_map_1;
  723. u32 dmm_lisa_map_2;
  724. u32 dmm_lisa_map_3;
  725. u8 is_ma_present;
  726. };
  727. #define CS0 0
  728. #define CS1 1
  729. /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
  730. #define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */
  731. /*
  732. * The period of DDR clk is represented as numerator and denominator for
  733. * better accuracy in integer based calculations. However, if the numerator
  734. * and denominator are very huge there may be chances of overflow in
  735. * calculations. So, as a trade-off keep denominator(and consequently
  736. * numerator) within a limit sacrificing some accuracy - but not much
  737. * If denominator and numerator are already small (such as at 400 MHz)
  738. * no adjustment is needed
  739. */
  740. #define EMIF_PERIOD_DEN_LIMIT 1000
  741. /*
  742. * Maximum number of different frequencies supported by EMIF driver
  743. * Determines the number of entries in the pointer array for register
  744. * cache
  745. */
  746. #define EMIF_MAX_NUM_FREQUENCIES 6
  747. /*
  748. * Indices into the Addressing Table array.
  749. * One entry each for all the different types of devices with different
  750. * addressing schemes
  751. */
  752. #define ADDR_TABLE_INDEX64M 0
  753. #define ADDR_TABLE_INDEX128M 1
  754. #define ADDR_TABLE_INDEX256M 2
  755. #define ADDR_TABLE_INDEX512M 3
  756. #define ADDR_TABLE_INDEX1GS4 4
  757. #define ADDR_TABLE_INDEX2GS4 5
  758. #define ADDR_TABLE_INDEX4G 6
  759. #define ADDR_TABLE_INDEX8G 7
  760. #define ADDR_TABLE_INDEX1GS2 8
  761. #define ADDR_TABLE_INDEX2GS2 9
  762. #define ADDR_TABLE_INDEXMAX 10
  763. /* Number of Row bits */
  764. #define ROW_9 0
  765. #define ROW_10 1
  766. #define ROW_11 2
  767. #define ROW_12 3
  768. #define ROW_13 4
  769. #define ROW_14 5
  770. #define ROW_15 6
  771. #define ROW_16 7
  772. /* Number of Column bits */
  773. #define COL_8 0
  774. #define COL_9 1
  775. #define COL_10 2
  776. #define COL_11 3
  777. #define COL_7 4 /*Not supported by OMAP included for completeness */
  778. /* Number of Banks*/
  779. #define BANKS1 0
  780. #define BANKS2 1
  781. #define BANKS4 2
  782. #define BANKS8 3
  783. /* Refresh rate in micro seconds x 10 */
  784. #define T_REFI_15_6 156
  785. #define T_REFI_7_8 78
  786. #define T_REFI_3_9 39
  787. #define EBANK_CS1_DIS 0
  788. #define EBANK_CS1_EN 1
  789. /* Read Latency used by the device at reset */
  790. #define RL_BOOT 3
  791. /* Read Latency for the highest frequency you want to use */
  792. #ifdef CONFIG_OMAP54XX
  793. #define RL_FINAL 8
  794. #else
  795. #define RL_FINAL 6
  796. #endif
  797. /* Interleaving policies at EMIF level- between banks and Chip Selects */
  798. #define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0
  799. #define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3
  800. /*
  801. * Interleaving policy to be used
  802. * Currently set to MAX interleaving for better performance
  803. */
  804. #define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
  805. /* State of the core voltage:
  806. * This is important for some parameters such as read idle control and
  807. * ZQ calibration timings. Timings are much stricter when voltage ramp
  808. * is happening compared to when the voltage is stable.
  809. * We need to calculate two sets of values for these parameters and use
  810. * them accordingly
  811. */
  812. #define LPDDR2_VOLTAGE_STABLE 0
  813. #define LPDDR2_VOLTAGE_RAMPING 1
  814. /* Length of the forced read idle period in terms of cycles */
  815. #define EMIF_REG_READ_IDLE_LEN_VAL 5
  816. /* Interval between forced 'read idles' */
  817. /* To be used when voltage is changed for DPS/DVFS - 1us */
  818. #define READ_IDLE_INTERVAL_DVFS (1*1000)
  819. /*
  820. * To be used when voltage is not scaled except by Smart Reflex
  821. * 50us - or maximum value will do
  822. */
  823. #define READ_IDLE_INTERVAL_NORMAL (50*1000)
  824. /*
  825. * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
  826. * be enough. This shoule be enough also in the case when voltage is changing
  827. * due to smart-reflex.
  828. */
  829. #define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000)
  830. /*
  831. * If voltage is changing due to DVFS ZQCS should be performed more
  832. * often(every 50us)
  833. */
  834. #define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50
  835. /* The interval between ZQCL commands as a multiple of ZQCS interval */
  836. #define REG_ZQ_ZQCL_MULT 4
  837. /* The interval between ZQINIT commands as a multiple of ZQCL interval */
  838. #define REG_ZQ_ZQINIT_MULT 3
  839. /* Enable ZQ Calibration on exiting Self-refresh */
  840. #define REG_ZQ_SFEXITEN_ENABLE 1
  841. /*
  842. * ZQ Calibration simultaneously on both chip-selects:
  843. * Needs one calibration resistor per CS
  844. * None of the boards that we know of have this capability
  845. * So disabled by default
  846. */
  847. #define REG_ZQ_DUALCALEN_DISABLE 0
  848. /*
  849. * Enable ZQ Calibration by default on CS0. If we are asked to program
  850. * the EMIF there will be something connected to CS0 for sure
  851. */
  852. #define REG_ZQ_CS0EN_ENABLE 1
  853. /* EMIF_PWR_MGMT_CTRL register */
  854. /* Low power modes */
  855. #define LP_MODE_DISABLE 0
  856. #define LP_MODE_CLOCK_STOP 1
  857. #define LP_MODE_SELF_REFRESH 2
  858. #define LP_MODE_PWR_DN 3
  859. /* REG_DPD_EN */
  860. #define DPD_DISABLE 0
  861. #define DPD_ENABLE 1
  862. /* Maximum delay before Low Power Modes */
  863. #define REG_CS_TIM 0x0
  864. #define REG_SR_TIM 0xF
  865. #define REG_PD_TIM 0xF
  866. /* EMIF_PWR_MGMT_CTRL register */
  867. #define EMIF_PWR_MGMT_CTRL (\
  868. ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
  869. ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
  870. ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
  871. ((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\
  872. & EMIF_REG_LP_MODE_MASK) |\
  873. ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
  874. & EMIF_REG_DPD_EN_MASK))\
  875. #define EMIF_PWR_MGMT_CTRL_SHDW (\
  876. ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\
  877. & EMIF_REG_CS_TIM_SHDW_MASK) |\
  878. ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
  879. & EMIF_REG_SR_TIM_SHDW_MASK) |\
  880. ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
  881. & EMIF_REG_PD_TIM_SHDW_MASK))
  882. /* EMIF_L3_CONFIG register value */
  883. #define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF
  884. #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000
  885. #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000
  886. /*
  887. * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
  888. * All these fields have magic values dependent on frequency and
  889. * determined by PHY and DLL integration with EMIF. Setting the magic
  890. * values suggested by hw team.
  891. */
  892. #define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF
  893. #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41
  894. #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80
  895. #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF
  896. /*
  897. * MR1 value:
  898. * Burst length : 8
  899. * Burst type : sequential
  900. * Wrap : enabled
  901. * nWR : 3(default). EMIF does not do pre-charge.
  902. * : So nWR is don't care
  903. */
  904. #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23
  905. #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3
  906. /* MR2 */
  907. #define MR2_RL3_WL1 1
  908. #define MR2_RL4_WL2 2
  909. #define MR2_RL5_WL2 3
  910. #define MR2_RL6_WL3 4
  911. /* MR10: ZQ calibration codes */
  912. #define MR10_ZQ_ZQCS 0x56
  913. #define MR10_ZQ_ZQCL 0xAB
  914. #define MR10_ZQ_ZQINIT 0xFF
  915. #define MR10_ZQ_ZQRESET 0xC3
  916. /* TEMP_ALERT_CONFIG */
  917. #define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */
  918. #define TEMP_ALERT_CONFIG_DEVCT_1 0
  919. #define TEMP_ALERT_CONFIG_DEVWDT_32 2
  920. /* MR16 value: refresh full array(no partial array self refresh) */
  921. #define MR16_REF_FULL_ARRAY 0
  922. /*
  923. * Maximum number of entries we keep in our array of timing tables
  924. * We need not keep all the speed bins supported by the device
  925. * We need to keep timing tables for only the speed bins that we
  926. * are interested in
  927. */
  928. #define MAX_NUM_SPEEDBINS 4
  929. /* LPDDR2 Densities */
  930. #define LPDDR2_DENSITY_64Mb 0
  931. #define LPDDR2_DENSITY_128Mb 1
  932. #define LPDDR2_DENSITY_256Mb 2
  933. #define LPDDR2_DENSITY_512Mb 3
  934. #define LPDDR2_DENSITY_1Gb 4
  935. #define LPDDR2_DENSITY_2Gb 5
  936. #define LPDDR2_DENSITY_4Gb 6
  937. #define LPDDR2_DENSITY_8Gb 7
  938. #define LPDDR2_DENSITY_16Gb 8
  939. #define LPDDR2_DENSITY_32Gb 9
  940. /* LPDDR2 type */
  941. #define LPDDR2_TYPE_S4 0
  942. #define LPDDR2_TYPE_S2 1
  943. #define LPDDR2_TYPE_NVM 2
  944. /* LPDDR2 IO width */
  945. #define LPDDR2_IO_WIDTH_32 0
  946. #define LPDDR2_IO_WIDTH_16 1
  947. #define LPDDR2_IO_WIDTH_8 2
  948. /* Mode register numbers */
  949. #define LPDDR2_MR0 0
  950. #define LPDDR2_MR1 1
  951. #define LPDDR2_MR2 2
  952. #define LPDDR2_MR3 3
  953. #define LPDDR2_MR4 4
  954. #define LPDDR2_MR5 5
  955. #define LPDDR2_MR6 6
  956. #define LPDDR2_MR7 7
  957. #define LPDDR2_MR8 8
  958. #define LPDDR2_MR9 9
  959. #define LPDDR2_MR10 10
  960. #define LPDDR2_MR11 11
  961. #define LPDDR2_MR16 16
  962. #define LPDDR2_MR17 17
  963. #define LPDDR2_MR18 18
  964. /* MR0 */
  965. #define LPDDR2_MR0_DAI_SHIFT 0
  966. #define LPDDR2_MR0_DAI_MASK 1
  967. #define LPDDR2_MR0_DI_SHIFT 1
  968. #define LPDDR2_MR0_DI_MASK (1 << 1)
  969. #define LPDDR2_MR0_DNVI_SHIFT 2
  970. #define LPDDR2_MR0_DNVI_MASK (1 << 2)
  971. /* MR4 */
  972. #define MR4_SDRAM_REF_RATE_SHIFT 0
  973. #define MR4_SDRAM_REF_RATE_MASK 7
  974. #define MR4_TUF_SHIFT 7
  975. #define MR4_TUF_MASK (1 << 7)
  976. /* MR4 SDRAM Refresh Rate field values */
  977. #define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0
  978. #define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1
  979. #define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2
  980. #define SDRAM_TEMP_NOMINAL 0x3
  981. #define SDRAM_TEMP_RESERVED_4 0x4
  982. #define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
  983. #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
  984. #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
  985. #define LPDDR2_MANUFACTURER_SAMSUNG 1
  986. #define LPDDR2_MANUFACTURER_QIMONDA 2
  987. #define LPDDR2_MANUFACTURER_ELPIDA 3
  988. #define LPDDR2_MANUFACTURER_ETRON 4
  989. #define LPDDR2_MANUFACTURER_NANYA 5
  990. #define LPDDR2_MANUFACTURER_HYNIX 6
  991. #define LPDDR2_MANUFACTURER_MOSEL 7
  992. #define LPDDR2_MANUFACTURER_WINBOND 8
  993. #define LPDDR2_MANUFACTURER_ESMT 9
  994. #define LPDDR2_MANUFACTURER_SPANSION 11
  995. #define LPDDR2_MANUFACTURER_SST 12
  996. #define LPDDR2_MANUFACTURER_ZMOS 13
  997. #define LPDDR2_MANUFACTURER_INTEL 14
  998. #define LPDDR2_MANUFACTURER_NUMONYX 254
  999. #define LPDDR2_MANUFACTURER_MICRON 255
  1000. /* MR8 register fields */
  1001. #define MR8_TYPE_SHIFT 0x0
  1002. #define MR8_TYPE_MASK 0x3
  1003. #define MR8_DENSITY_SHIFT 0x2
  1004. #define MR8_DENSITY_MASK (0xF << 0x2)
  1005. #define MR8_IO_WIDTH_SHIFT 0x6
  1006. #define MR8_IO_WIDTH_MASK (0x3 << 0x6)
  1007. /* SDRAM TYPE */
  1008. #define EMIF_SDRAM_TYPE_DDR2 0x2
  1009. #define EMIF_SDRAM_TYPE_DDR3 0x3
  1010. #define EMIF_SDRAM_TYPE_LPDDR2 0x4
  1011. struct lpddr2_addressing {
  1012. u8 num_banks;
  1013. u8 t_REFI_us_x10;
  1014. u8 row_sz[2]; /* One entry each for x32 and x16 */
  1015. u8 col_sz[2]; /* One entry each for x32 and x16 */
  1016. };
  1017. /* Structure for timings from the DDR datasheet */
  1018. struct lpddr2_ac_timings {
  1019. u32 max_freq;
  1020. u8 RL;
  1021. u8 tRPab;
  1022. u8 tRCD;
  1023. u8 tWR;
  1024. u8 tRASmin;
  1025. u8 tRRD;
  1026. u8 tWTRx2;
  1027. u8 tXSR;
  1028. u8 tXPx2;
  1029. u8 tRFCab;
  1030. u8 tRTPx2;
  1031. u8 tCKE;
  1032. u8 tCKESR;
  1033. u8 tZQCS;
  1034. u32 tZQCL;
  1035. u32 tZQINIT;
  1036. u8 tDQSCKMAXx2;
  1037. u8 tRASmax;
  1038. u8 tFAW;
  1039. };
  1040. /*
  1041. * Min tCK values for some of the parameters:
  1042. * If the calculated clock cycles for the respective parameter is
  1043. * less than the corresponding min tCK value, we need to set the min
  1044. * tCK value. This may happen at lower frequencies.
  1045. */
  1046. struct lpddr2_min_tck {
  1047. u32 tRL;
  1048. u32 tRP_AB;
  1049. u32 tRCD;
  1050. u32 tWR;
  1051. u32 tRAS_MIN;
  1052. u32 tRRD;
  1053. u32 tWTR;
  1054. u32 tXP;
  1055. u32 tRTP;
  1056. u8 tCKE;
  1057. u32 tCKESR;
  1058. u32 tFAW;
  1059. };
  1060. struct lpddr2_device_details {
  1061. u8 type;
  1062. u8 density;
  1063. u8 io_width;
  1064. u8 manufacturer;
  1065. };
  1066. struct lpddr2_device_timings {
  1067. const struct lpddr2_ac_timings **ac_timings;
  1068. const struct lpddr2_min_tck *min_tck;
  1069. };
  1070. /* Details of the devices connected to each chip-select of an EMIF instance */
  1071. struct emif_device_details {
  1072. const struct lpddr2_device_details *cs0_device_details;
  1073. const struct lpddr2_device_details *cs1_device_details;
  1074. const struct lpddr2_device_timings *cs0_device_timings;
  1075. const struct lpddr2_device_timings *cs1_device_timings;
  1076. };
  1077. /*
  1078. * Structure containing shadow of important registers in EMIF
  1079. * The calculation function fills in this structure to be later used for
  1080. * initialization and DVFS
  1081. */
  1082. struct emif_regs {
  1083. u32 freq;
  1084. u32 sdram_config_init;
  1085. u32 sdram_config;
  1086. u32 sdram_config2;
  1087. u32 ref_ctrl;
  1088. u32 ref_ctrl_final;
  1089. u32 sdram_tim1;
  1090. u32 sdram_tim2;
  1091. u32 sdram_tim3;
  1092. u32 ocp_config;
  1093. u32 read_idle_ctrl;
  1094. u32 zq_config;
  1095. u32 temp_alert_config;
  1096. u32 emif_ddr_phy_ctlr_1_init;
  1097. u32 emif_ddr_phy_ctlr_1;
  1098. u32 emif_ddr_ext_phy_ctrl_1;
  1099. u32 emif_ddr_ext_phy_ctrl_2;
  1100. u32 emif_ddr_ext_phy_ctrl_3;
  1101. u32 emif_ddr_ext_phy_ctrl_4;
  1102. u32 emif_ddr_ext_phy_ctrl_5;
  1103. u32 emif_rd_wr_lvl_rmp_win;
  1104. u32 emif_rd_wr_lvl_rmp_ctl;
  1105. u32 emif_rd_wr_lvl_ctl;
  1106. u32 emif_rd_wr_exec_thresh;
  1107. u32 emif_prio_class_serv_map;
  1108. u32 emif_connect_id_serv_1_map;
  1109. u32 emif_connect_id_serv_2_map;
  1110. u32 emif_cos_config;
  1111. u32 emif_ecc_ctrl_reg;
  1112. u32 emif_ecc_address_range_1;
  1113. u32 emif_ecc_address_range_2;
  1114. };
  1115. struct lpddr2_mr_regs {
  1116. s8 mr1;
  1117. s8 mr2;
  1118. s8 mr3;
  1119. s8 mr10;
  1120. s8 mr16;
  1121. };
  1122. struct read_write_regs {
  1123. u32 read_reg;
  1124. u32 write_reg;
  1125. };
  1126. static inline u32 get_emif_rev(u32 base)
  1127. {
  1128. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  1129. return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
  1130. >> EMIF_REG_MAJOR_REVISION_SHIFT;
  1131. }
  1132. /*
  1133. * Get SDRAM type connected to EMIF.
  1134. * Assuming similar SDRAM parts are connected to both EMIF's
  1135. * which is typically the case. So it is sufficient to get
  1136. * SDRAM type from EMIF1.
  1137. */
  1138. static inline u32 emif_sdram_type(u32 sdram_config)
  1139. {
  1140. return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK)
  1141. >> EMIF_REG_SDRAM_TYPE_SHIFT;
  1142. }
  1143. /* assert macros */
  1144. #if defined(DEBUG)
  1145. #define emif_assert(c) ({ if (!(c)) for (;;); })
  1146. #else
  1147. #define emif_assert(c) ({ if (0) hang(); })
  1148. #endif
  1149. #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  1150. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
  1151. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
  1152. #else
  1153. struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
  1154. struct lpddr2_device_details *lpddr2_dev_details);
  1155. void emif_get_device_timings(u32 emif_nr,
  1156. const struct lpddr2_device_timings **cs0_device_timings,
  1157. const struct lpddr2_device_timings **cs1_device_timings);
  1158. #endif
  1159. void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
  1160. void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
  1161. #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  1162. extern u32 *const T_num;
  1163. extern u32 *const T_den;
  1164. #endif
  1165. void config_data_eye_leveling_samples(u32 emif_base);
  1166. const struct read_write_regs *get_bug_regs(u32 *iterations);
  1167. #endif