armv7.h 4.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010
  4. * Texas Instruments, <www.ti.com>
  5. * Aneesh V <aneesh@ti.com>
  6. */
  7. #ifndef ARMV7_H
  8. #define ARMV7_H
  9. /* Cortex-A9 revisions */
  10. #define MIDR_CORTEX_A9_R0P1 0x410FC091
  11. #define MIDR_CORTEX_A9_R1P2 0x411FC092
  12. #define MIDR_CORTEX_A9_R1P3 0x411FC093
  13. #define MIDR_CORTEX_A9_R2P10 0x412FC09A
  14. /* Cortex-A15 revisions */
  15. #define MIDR_CORTEX_A15_R0P0 0x410FC0F0
  16. #define MIDR_CORTEX_A15_R2P2 0x412FC0F2
  17. /* Cortex-A7 revisions */
  18. #define MIDR_CORTEX_A7_R0P0 0x410FC070
  19. #define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
  20. /* ID_PFR1 feature fields */
  21. #define CPUID_ARM_SEC_SHIFT 4
  22. #define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT)
  23. #define CPUID_ARM_VIRT_SHIFT 12
  24. #define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT)
  25. #define CPUID_ARM_GENTIMER_SHIFT 16
  26. #define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT)
  27. /* valid bits in CBAR register / PERIPHBASE value */
  28. #define CBAR_MASK 0xFFFF8000
  29. /* CCSIDR */
  30. #define CCSIDR_LINE_SIZE_OFFSET 0
  31. #define CCSIDR_LINE_SIZE_MASK 0x7
  32. #define CCSIDR_ASSOCIATIVITY_OFFSET 3
  33. #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3)
  34. #define CCSIDR_NUM_SETS_OFFSET 13
  35. #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13)
  36. /*
  37. * Values for InD field in CSSELR
  38. * Selects the type of cache
  39. */
  40. #define ARMV7_CSSELR_IND_DATA_UNIFIED 0
  41. #define ARMV7_CSSELR_IND_INSTRUCTION 1
  42. /* Values for Ctype fields in CLIDR */
  43. #define ARMV7_CLIDR_CTYPE_NO_CACHE 0
  44. #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1
  45. #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2
  46. #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
  47. #define ARMV7_CLIDR_CTYPE_UNIFIED 4
  48. #ifndef __ASSEMBLY__
  49. #include <linux/types.h>
  50. #include <asm/io.h>
  51. #include <asm/barriers.h>
  52. /* read L2 control register (L2CTLR) */
  53. static inline uint32_t read_l2ctlr(void)
  54. {
  55. uint32_t val = 0;
  56. asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
  57. return val;
  58. }
  59. /* write L2 control register (L2CTLR) */
  60. static inline void write_l2ctlr(uint32_t val)
  61. {
  62. /*
  63. * Note: L2CTLR can only be written when the L2 memory system
  64. * is idle, ie before the MMU is enabled.
  65. */
  66. asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
  67. isb();
  68. }
  69. /*
  70. * Workaround for ARM errata # 798870
  71. * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
  72. * stalled for 1024 cycles to verify that its hazard condition still exists.
  73. */
  74. static inline void v7_enable_l2_hazard_detect(void)
  75. {
  76. uint32_t val;
  77. /* L2ACTLR[7]: Enable hazard detect timeout */
  78. asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
  79. val |= (1 << 7);
  80. asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
  81. }
  82. /*
  83. * Workaround for ARM errata # 799270
  84. * Ensure that the L2 logic has been used within the previous 256 cycles
  85. * before modifying the ACTLR.SMP bit. This is required during boot before
  86. * MMU has been enabled, or during a specified reset or power down sequence.
  87. */
  88. static inline void v7_enable_smp(uint32_t address)
  89. {
  90. uint32_t temp, val;
  91. /* Read auxiliary control register */
  92. asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
  93. /* Enable SMP */
  94. val |= (1 << 6);
  95. /* Dummy read to assure L2 access */
  96. temp = readl(address);
  97. temp &= 0;
  98. val |= temp;
  99. /* Write auxiliary control register */
  100. asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
  101. CP15DSB;
  102. CP15ISB;
  103. }
  104. void v7_en_l2_hazard_detect(void);
  105. void v7_outer_cache_enable(void);
  106. void v7_outer_cache_disable(void);
  107. void v7_outer_cache_flush_all(void);
  108. void v7_outer_cache_inval_all(void);
  109. void v7_outer_cache_flush_range(u32 start, u32 end);
  110. void v7_outer_cache_inval_range(u32 start, u32 end);
  111. #ifdef CONFIG_ARMV7_NONSEC
  112. int armv7_init_nonsec(void);
  113. int armv7_apply_memory_carveout(u64 *start, u64 *size);
  114. bool armv7_boot_nonsec(void);
  115. /* defined in assembly file */
  116. unsigned int _nonsec_init(void);
  117. void _do_nonsec_entry(void *target_pc, unsigned long r0,
  118. unsigned long r1, unsigned long r2);
  119. void _smp_pen(void);
  120. extern char __secure_start[];
  121. extern char __secure_end[];
  122. extern char __secure_stack_start[];
  123. extern char __secure_stack_end[];
  124. #endif /* CONFIG_ARMV7_NONSEC */
  125. void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
  126. u32 cpu_rev_comb, u32 cpu_variant,
  127. u32 cpu_rev);
  128. void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
  129. u32 cpu_variant, u32 cpu_rev);
  130. #endif /* ! __ASSEMBLY__ */
  131. #endif