clk_rst.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010-2014
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #ifndef _TEGRA_CLK_RST_H_
  7. #define _TEGRA_CLK_RST_H_
  8. /* PLL registers - there are several PLLs in the clock controller */
  9. struct clk_pll {
  10. uint pll_base; /* the control register */
  11. /* pll_out[0] is output A control, pll_out[1] is output B control */
  12. uint pll_out[2];
  13. uint pll_misc; /* other misc things */
  14. };
  15. /* PLL registers - there are several PLLs in the clock controller */
  16. struct clk_pll_simple {
  17. uint pll_base; /* the control register */
  18. uint pll_misc; /* other misc things */
  19. };
  20. struct clk_pllm {
  21. uint pllm_base; /* the control register */
  22. uint pllm_out; /* output control */
  23. uint pllm_misc1; /* misc1 */
  24. uint pllm_misc2; /* misc2 */
  25. };
  26. /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
  27. struct clk_set_clr {
  28. uint set;
  29. uint clr;
  30. };
  31. /*
  32. * Most PLLs use the clk_pll structure, but some have a simpler two-member
  33. * structure for which we use clk_pll_simple. The reason for this non-
  34. * othogonal setup is not stated.
  35. */
  36. enum {
  37. TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
  38. TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
  39. TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */
  40. TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
  41. TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
  42. TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
  43. TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
  44. TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
  45. };
  46. /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
  47. struct clk_rst_ctlr {
  48. uint crc_rst_src; /* _RST_SOURCE_0,0x00 */
  49. uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
  50. uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
  51. uint crc_reserved0; /* reserved_0, 0x1C */
  52. uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
  53. uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
  54. uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
  55. uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
  56. uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
  57. uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
  58. uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */
  59. uint crc_reserved1; /* reserved_1, 0x3C */
  60. uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */
  61. uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
  62. uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
  63. uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */
  64. uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */
  65. uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */
  66. uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
  67. uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */
  68. uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */
  69. struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */
  70. /* PLLs from 0xe0 to 0xf4 */
  71. struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
  72. uint crc_reserved10; /* _reserved_10, 0xF8 */
  73. uint crc_reserved11; /* _reserved_11, 0xFC */
  74. uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
  75. uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */
  76. uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
  77. uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
  78. uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
  79. uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
  80. uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
  81. uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
  82. uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
  83. uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
  84. uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
  85. uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
  86. uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
  87. uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
  88. uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
  89. uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
  90. uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */
  91. /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
  92. struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
  93. uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */
  94. /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
  95. struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
  96. uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */
  97. uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
  98. uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
  99. /* Additional (T30) registers */
  100. uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
  101. uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
  102. uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */
  103. uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
  104. uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
  105. uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
  106. uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */
  107. uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
  108. uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
  109. uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
  110. uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
  111. uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
  112. uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
  113. uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
  114. uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */
  115. uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */
  116. /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
  117. struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
  118. /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
  119. struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
  120. /* Additional (T114+) registers */
  121. uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
  122. uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
  123. uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
  124. uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */
  125. uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
  126. uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
  127. uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
  128. uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
  129. uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
  130. uint crc_reserved40[1]; /* _reserved_40, 0x474 */
  131. uint crc_intstatus; /* __INTSTATUS_0, 0x478 */
  132. uint crc_intmask; /* __INTMASK_0, 0x47C */
  133. uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
  134. uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
  135. uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
  136. uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */
  137. uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
  138. uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
  139. uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
  140. uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */
  141. uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
  142. uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
  143. uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
  144. uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
  145. uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
  146. uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
  147. uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */
  148. uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */
  149. uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */
  150. uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */
  151. uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */
  152. uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */
  153. uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */
  154. uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */
  155. uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */
  156. uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */
  157. uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */
  158. uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */
  159. uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
  160. uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
  161. uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
  162. uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */
  163. uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
  164. uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
  165. uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
  166. uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */
  167. uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
  168. uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */
  169. uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
  170. uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
  171. uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
  172. uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
  173. uint crc_reserved51[1]; /* _reserved_51, 0x538 */
  174. uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */
  175. uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
  176. uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
  177. uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
  178. uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */
  179. uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
  180. uint crc_reserved52[1]; /* _reserved_52, 0x554 */
  181. uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
  182. uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */
  183. u32 _rsv32[4]; /* 0x560-0x56c */
  184. u32 crc_plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */
  185. u32 _rsv32_1[7]; /* 0x574-58c */
  186. struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
  187. u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
  188. /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
  189. uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
  190. uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
  191. /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
  192. uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
  193. /*
  194. * NOTE: PLLA1 regs are in the middle of this Y region. Break this in
  195. * two later if PLLA1 is needed, but for now this is cleaner.
  196. */
  197. uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
  198. };
  199. /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
  200. #define CPU3_CLK_STP_SHIFT 11
  201. #define CPU2_CLK_STP_SHIFT 10
  202. #define CPU1_CLK_STP_SHIFT 9
  203. #define CPU0_CLK_STP_SHIFT 8
  204. #define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
  205. /* CLK_RST_CONTROLLER_PLLx_BASE_0 */
  206. #define PLL_BYPASS_SHIFT 31
  207. #define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT)
  208. #define PLL_ENABLE_SHIFT 30
  209. #define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT)
  210. #define PLL_BASE_OVRRIDE_MASK (1U << 28)
  211. #define PLL_LOCK_SHIFT 27
  212. #define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT)
  213. /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
  214. #define PLL_OUT_RSTN (1 << 0)
  215. #define PLL_OUT_CLKEN (1 << 1)
  216. #define PLL_OUT_OVRRIDE (1 << 2)
  217. #define PLL_OUT_RATIO_SHIFT 8
  218. #define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
  219. /* CLK_RST_CONTROLLER_PLLx_MISC_0 */
  220. #define PLL_DCCON_SHIFT 20
  221. #define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT)
  222. #define PLLP_OUT1_OVR (1 << 2)
  223. #define PLLP_OUT2_OVR (1 << 18)
  224. #define PLLP_OUT3_OVR (1 << 2)
  225. #define PLLP_OUT4_OVR (1 << 18)
  226. #define PLLP_OUT1_RATIO 8
  227. #define PLLP_OUT2_RATIO 24
  228. #define PLLP_OUT3_RATIO 8
  229. #define PLLP_OUT4_RATIO 24
  230. enum {
  231. IN_408_OUT_204_DIVISOR = 2,
  232. IN_408_OUT_102_DIVISOR = 6,
  233. IN_408_OUT_48_DIVISOR = 15,
  234. IN_408_OUT_9_6_DIVISOR = 83,
  235. };
  236. #define PLLP_OUT1_RSTN_DIS (1 << 0)
  237. #define PLLP_OUT1_RSTN_EN (0 << 0)
  238. #define PLLP_OUT1_CLKEN (1 << 1)
  239. #define PLLP_OUT2_RSTN_DIS (1 << 16)
  240. #define PLLP_OUT2_RSTN_EN (0 << 16)
  241. #define PLLP_OUT2_CLKEN (1 << 17)
  242. #define PLLP_OUT3_RSTN_DIS (1 << 0)
  243. #define PLLP_OUT3_RSTN_EN (0 << 0)
  244. #define PLLP_OUT3_CLKEN (1 << 1)
  245. #define PLLP_OUT4_RSTN_DIS (1 << 16)
  246. #define PLLP_OUT4_RSTN_EN (0 << 16)
  247. #define PLLP_OUT4_CLKEN (1 << 17)
  248. /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
  249. #define PLLU_POWERDOWN (1 << 16)
  250. #define PLL_ENABLE_POWERDOWN (1 << 14)
  251. #define PLL_ACTIVE_POWERDOWN (1 << 12)
  252. /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
  253. #define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
  254. #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
  255. #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
  256. /* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
  257. #define OSC_XOE_SHIFT 0
  258. #define OSC_XOE_MASK (1 << OSC_XOE_SHIFT)
  259. #define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT)
  260. #define OSC_XOBP_SHIFT 1
  261. #define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
  262. #define OSC_XOFS_SHIFT 4
  263. #define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT)
  264. #define OSC_DRIVE_STRENGTH 7
  265. /*
  266. * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
  267. * but can be 16. We could use knowledge we have to restrict the mask in
  268. * the 8-bit cases (the divider_bits value returned by
  269. * get_periph_clock_source()) but it does not seem worth it since the code
  270. * already checks the ranges of values it is writing, in clk_get_divider().
  271. */
  272. #define OUT_CLK_DIVISOR_SHIFT 0
  273. #define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
  274. #define OUT_CLK_SOURCE_31_30_SHIFT 30
  275. #define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
  276. #define OUT_CLK_SOURCE_31_29_SHIFT 29
  277. #define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT)
  278. /* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
  279. #define OUT_CLK_SOURCE_31_28_SHIFT 28
  280. #define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
  281. /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
  282. #define SCLK_SYS_STATE_SHIFT 28U
  283. #define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT)
  284. enum {
  285. SCLK_SYS_STATE_STDBY,
  286. SCLK_SYS_STATE_IDLE,
  287. SCLK_SYS_STATE_RUN,
  288. SCLK_SYS_STATE_IRQ = 4U,
  289. SCLK_SYS_STATE_FIQ = 8U,
  290. };
  291. #define SCLK_COP_FIQ_MASK (1 << 27)
  292. #define SCLK_CPU_FIQ_MASK (1 << 26)
  293. #define SCLK_COP_IRQ_MASK (1 << 25)
  294. #define SCLK_CPU_IRQ_MASK (1 << 24)
  295. #define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12
  296. #define SCLK_SWAKEUP_FIQ_SOURCE_MASK \
  297. (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
  298. #define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8
  299. #define SCLK_SWAKEUP_IRQ_SOURCE_MASK \
  300. (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
  301. #define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4
  302. #define SCLK_SWAKEUP_RUN_SOURCE_MASK \
  303. (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
  304. #define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
  305. #define SCLK_SWAKEUP_IDLE_SOURCE_MASK \
  306. (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
  307. enum {
  308. SCLK_SOURCE_CLKM,
  309. SCLK_SOURCE_PLLC_OUT1,
  310. SCLK_SOURCE_PLLP_OUT4,
  311. SCLK_SOURCE_PLLP_OUT3,
  312. SCLK_SOURCE_PLLP_OUT2,
  313. SCLK_SOURCE_CLKD,
  314. SCLK_SOURCE_CLKS,
  315. SCLK_SOURCE_PLLM_OUT1,
  316. };
  317. #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
  318. #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
  319. #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
  320. #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
  321. /* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
  322. #define SUPER_SCLK_ENB_SHIFT 31U
  323. #define SUPER_SCLK_ENB_MASK (1U << 31)
  324. #define SUPER_SCLK_DIVIDEND_SHIFT 8
  325. #define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
  326. #define SUPER_SCLK_DIVISOR_SHIFT 0
  327. #define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
  328. /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
  329. #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
  330. #define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
  331. #define CLK_SYS_RATE_AHB_RATE_SHIFT 4
  332. #define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
  333. #define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
  334. #define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
  335. #define CLK_SYS_RATE_APB_RATE_SHIFT 0
  336. #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
  337. /* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
  338. #define CLR_CPURESET0 (1 << 0)
  339. #define CLR_CPURESET1 (1 << 1)
  340. #define CLR_CPURESET2 (1 << 2)
  341. #define CLR_CPURESET3 (1 << 3)
  342. #define CLR_DBGRESET0 (1 << 12)
  343. #define CLR_DBGRESET1 (1 << 13)
  344. #define CLR_DBGRESET2 (1 << 14)
  345. #define CLR_DBGRESET3 (1 << 15)
  346. #define CLR_CORERESET0 (1 << 16)
  347. #define CLR_CORERESET1 (1 << 17)
  348. #define CLR_CORERESET2 (1 << 18)
  349. #define CLR_CORERESET3 (1 << 19)
  350. #define CLR_CXRESET0 (1 << 20)
  351. #define CLR_CXRESET1 (1 << 21)
  352. #define CLR_CXRESET2 (1 << 22)
  353. #define CLR_CXRESET3 (1 << 23)
  354. #define CLR_L2RESET (1 << 24)
  355. #define CLR_NONCPURESET (1 << 29)
  356. #define CLR_PRESETDBG (1 << 30)
  357. /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
  358. #define CLR_CPU0_CLK_STP (1 << 8)
  359. #define CLR_CPU1_CLK_STP (1 << 9)
  360. #define CLR_CPU2_CLK_STP (1 << 10)
  361. #define CLR_CPU3_CLK_STP (1 << 11)
  362. /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
  363. #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)
  364. /* CRC_CLK_ENB_V_SET_0 0x440 */
  365. #define SET_CLK_ENB_CPUG_ENABLE (1 << 0)
  366. #define SET_CLK_ENB_CPULP_ENABLE (1 << 1)
  367. #define SET_CLK_ENB_MSELECT_ENABLE (1 << 3)
  368. /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
  369. #define PLL_ACTIVE_POWERDOWN (1 << 12)
  370. #define PLL_ENABLE_POWERDOWN (1 << 14)
  371. #define PLLU_POWERDOWN (1 << 16)
  372. /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
  373. #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
  374. #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
  375. #define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
  376. /* CLK_RST_CONTROLLER_PLLX_MISC_3 */
  377. #define PLLX_IDDQ_SHIFT 3
  378. #define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT)
  379. /* CLK_RST_PLLDP_SS_CFG */
  380. #define PLLDP_SS_CFG_CLAMP (1 << 22)
  381. #define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24)
  382. #define PLLDP_SS_CFG_DITHER (1 << 28)
  383. /* CLK_RST_PLLD_MISC */
  384. #define PLLD_CLKENABLE 30
  385. #endif /* _TEGRA_CLK_RST_H_ */