iomux.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Based on Linux i.MX iomux-v3.h file:
  4. * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
  5. * <armlinux@phytec.de>
  6. *
  7. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  8. */
  9. #ifndef __MACH_IOMUX_H__
  10. #define __MACH_IOMUX_H__
  11. /*
  12. * build IOMUX_PAD structure
  13. *
  14. * This iomux scheme is based around pads, which are the physical balls
  15. * on the processor.
  16. *
  17. * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
  18. * things like driving strength and pullup/pulldown.
  19. * - Each pad can have but not necessarily does have an output routing register
  20. * (IOMUXC_SW_MUX_CTL_PAD_x).
  21. * - Each pad can have but not necessarily does have an input routing register
  22. * (IOMUXC_x_SELECT_INPUT)
  23. *
  24. * The three register sets do not have a fixed offset to each other,
  25. * hence we order this table by pad control registers (which all pads
  26. * have) and put the optional i/o routing registers into additional
  27. * fields.
  28. *
  29. * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
  30. * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
  31. *
  32. * IOMUX/PAD Bit field definitions
  33. *
  34. * MUX_CTRL_OFS: 0..15 (16)
  35. * SEL_INPUT_OFS: 16..31 (16)
  36. * MUX_MODE: 32..37 (6)
  37. * SEL_INP: 38..41 (4)
  38. * PAD_CTRL + NO_PAD_CTRL: 42..60 (19)
  39. * reserved: 61-63 (3)
  40. */
  41. typedef u64 iomux_cfg_t;
  42. #define MUX_CTRL_OFS_SHIFT 0
  43. #define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT)
  44. #define MUX_SEL_INPUT_OFS_SHIFT 16
  45. #define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \
  46. MUX_SEL_INPUT_OFS_SHIFT)
  47. #define MUX_MODE_SHIFT 32
  48. #define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT)
  49. #define MUX_SEL_INPUT_SHIFT 38
  50. #define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
  51. #define MUX_PAD_CTRL_SHIFT 42
  52. #define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT)
  53. #define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
  54. #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
  55. sel_input, pad_ctrl) \
  56. (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
  57. ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
  58. ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
  59. ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
  60. ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
  61. #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
  62. MUX_PAD_CTRL(pad))
  63. #define IOMUX_CONFIG_MPORTS 0x20
  64. #define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
  65. MUX_MODE_SHIFT)
  66. /* Bit definition below needs to be fixed acccording to ulp rm */
  67. #define NO_PAD_CTRL (1 << 18)
  68. #define PAD_CTL_OBE_ENABLE (1 << 17)
  69. #define PAD_CTL_IBE_ENABLE (1 << 16)
  70. #define PAD_CTL_DSE (1 << 6)
  71. #define PAD_CTL_ODE (1 << 5)
  72. #define PAD_CTL_SRE_FAST (0 << 2)
  73. #define PAD_CTL_SRE_SLOW (1 << 2)
  74. #define PAD_CTL_PUE (1 << 1)
  75. #define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE)
  76. #define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE)
  77. void mx7ulp_iomux_setup_pad(iomux_cfg_t pad);
  78. void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
  79. unsigned count);
  80. #endif /* __MACH_IOMUX_H__*/