mx6sx-ddr.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __ASM_ARCH_MX6SX_DDR_H__
  6. #define __ASM_ARCH_MX6SX_DDR_H__
  7. #ifndef CONFIG_MX6SX
  8. #error "wrong CPU"
  9. #endif
  10. #define MX6_IOM_DRAM_DQM0 0x020e02ec
  11. #define MX6_IOM_DRAM_DQM1 0x020e02f0
  12. #define MX6_IOM_DRAM_DQM2 0x020e02f4
  13. #define MX6_IOM_DRAM_DQM3 0x020e02f8
  14. #define MX6_IOM_DRAM_RAS 0x020e02fc
  15. #define MX6_IOM_DRAM_CAS 0x020e0300
  16. #define MX6_IOM_DRAM_SDODT0 0x020e0310
  17. #define MX6_IOM_DRAM_SDODT1 0x020e0314
  18. #define MX6_IOM_DRAM_SDBA2 0x020e0320
  19. #define MX6_IOM_DRAM_SDCKE0 0x020e0324
  20. #define MX6_IOM_DRAM_SDCKE1 0x020e0328
  21. #define MX6_IOM_DRAM_SDCLK_0 0x020e032c
  22. #define MX6_IOM_DRAM_RESET 0x020e0340
  23. #define MX6_IOM_DRAM_SDQS0 0x020e0330
  24. #define MX6_IOM_DRAM_SDQS1 0x020e0334
  25. #define MX6_IOM_DRAM_SDQS2 0x020e0338
  26. #define MX6_IOM_DRAM_SDQS3 0x020e033c
  27. #define MX6_IOM_GRP_ADDDS 0x020e05f4
  28. #define MX6_IOM_DDRMODE_CTL 0x020e05f8
  29. #define MX6_IOM_GRP_DDRPKE 0x020e05fc
  30. #define MX6_IOM_GRP_DDRMODE 0x020e0608
  31. #define MX6_IOM_GRP_B0DS 0x020e060c
  32. #define MX6_IOM_GRP_B1DS 0x020e0610
  33. #define MX6_IOM_GRP_CTLDS 0x020e0614
  34. #define MX6_IOM_GRP_DDR_TYPE 0x020e0618
  35. #define MX6_IOM_GRP_B2DS 0x020e061c
  36. #define MX6_IOM_GRP_B3DS 0x020e0620
  37. #endif /*__ASM_ARCH_MX6SX_DDR_H__ */