clock.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009
  4. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  5. */
  6. #ifndef __ASM_ARCH_CLOCK_H
  7. #define __ASM_ARCH_CLOCK_H
  8. #include <linux/types.h>
  9. #ifdef CONFIG_SYS_MX6_HCLK
  10. #define MXC_HCLK CONFIG_SYS_MX6_HCLK
  11. #else
  12. #define MXC_HCLK 24000000
  13. #endif
  14. #ifdef CONFIG_SYS_MX6_CLK32
  15. #define MXC_CLK32 CONFIG_SYS_MX6_CLK32
  16. #else
  17. #define MXC_CLK32 32768
  18. #endif
  19. struct cmd_tbl;
  20. enum mxc_clock {
  21. MXC_ARM_CLK = 0,
  22. MXC_PER_CLK,
  23. MXC_AHB_CLK,
  24. MXC_IPG_CLK,
  25. MXC_IPG_PERCLK,
  26. MXC_UART_CLK,
  27. MXC_CSPI_CLK,
  28. MXC_AXI_CLK,
  29. MXC_EMI_SLOW_CLK,
  30. MXC_DDR_CLK,
  31. MXC_ESDHC_CLK,
  32. MXC_ESDHC2_CLK,
  33. MXC_ESDHC3_CLK,
  34. MXC_ESDHC4_CLK,
  35. MXC_SATA_CLK,
  36. MXC_NFC_CLK,
  37. MXC_I2C_CLK,
  38. };
  39. enum ldb_di_clock {
  40. MXC_PLL5_CLK = 0,
  41. MXC_PLL2_PFD0_CLK,
  42. MXC_PLL2_PFD2_CLK,
  43. MXC_MMDC_CH1_CLK,
  44. MXC_PLL3_SW_CLK,
  45. };
  46. enum enet_freq {
  47. ENET_25MHZ,
  48. ENET_50MHZ,
  49. ENET_100MHZ,
  50. ENET_125MHZ,
  51. };
  52. u32 imx_get_uartclk(void);
  53. u32 imx_get_fecclk(void);
  54. unsigned int mxc_get_clock(enum mxc_clock clk);
  55. void setup_gpmi_io_clk(u32 cfg);
  56. void hab_caam_clock_enable(unsigned char enable);
  57. void enable_ocotp_clk(unsigned char enable);
  58. void enable_usboh3_clk(unsigned char enable);
  59. void enable_uart_clk(unsigned char enable);
  60. int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
  61. int enable_sata_clock(void);
  62. void disable_sata_clock(void);
  63. int enable_pcie_clock(void);
  64. int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
  65. int enable_spi_clk(unsigned char enable, unsigned spi_num);
  66. void enable_ipu_clock(void);
  67. void disable_ipu_clock(void);
  68. int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
  69. void enable_enet_clk(unsigned char enable);
  70. int enable_lcdif_clock(u32 base_addr, bool enable);
  71. void enable_qspi_clk(int qspi_num);
  72. void enable_thermal_clk(void);
  73. void mxs_set_lcdclk(u32 base_addr, u32 freq);
  74. void select_ldb_di_clock_source(enum ldb_di_clock clk);
  75. void enable_eim_clk(unsigned char enable);
  76. int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  77. char *const argv[]);
  78. #endif /* __ASM_ARCH_CLOCK_H */