fsl_icid.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #ifndef _FSL_ICID_H_
  6. #define _FSL_ICID_H_
  7. #include <asm/types.h>
  8. #include <fsl_qbman.h>
  9. #include <fsl_sec.h>
  10. #include <asm/armv8/sec_firmware.h>
  11. struct icid_id_table {
  12. const char *compat;
  13. u32 id;
  14. u32 reg;
  15. phys_addr_t compat_addr;
  16. phys_addr_t reg_addr;
  17. bool le;
  18. };
  19. struct fman_icid_id_table {
  20. u32 port_id;
  21. u32 icid;
  22. };
  23. u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
  24. int fdt_get_smmu_phandle(void *blob);
  25. int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
  26. void set_icids(void);
  27. void fdt_fixup_icid(void *blob);
  28. #define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
  29. { .compat = name, \
  30. .id = idA, \
  31. .reg = regA, \
  32. .compat_addr = compataddr, \
  33. .reg_addr = addr, \
  34. .le = _le \
  35. }
  36. #ifdef CONFIG_SYS_FSL_SEC_LE
  37. #define SEC_IS_LE true
  38. #elif defined(CONFIG_SYS_FSL_SEC_BE)
  39. #define SEC_IS_LE false
  40. #endif
  41. #ifdef CONFIG_FSL_LSCH2
  42. #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
  43. #define SCFG_IS_LE true
  44. #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
  45. #define SCFG_IS_LE false
  46. #endif
  47. #define QDMA_IS_LE false
  48. #define SET_SCFG_ICID(compat, streamid, name, compataddr) \
  49. SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
  50. offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
  51. compataddr, SCFG_IS_LE)
  52. #define SET_USB_ICID(usb_num, compat, streamid) \
  53. SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
  54. CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
  55. #define SET_SATA_ICID(compat, streamid) \
  56. SET_SCFG_ICID(compat, streamid, sata_icid,\
  57. AHCI_BASE_ADDR)
  58. #define SET_SDHC_ICID(streamid) \
  59. SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
  60. CONFIG_SYS_FSL_ESDHC_ADDR)
  61. #define SET_EDMA_ICID(streamid) \
  62. SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
  63. EDMA_BASE_ADDR)
  64. #define SET_ETR_ICID(streamid) \
  65. SET_SCFG_ICID(NULL, streamid, etr_icid, 0)
  66. #define SET_DEBUG_ICID(streamid) \
  67. SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
  68. #define SET_QE_ICID(streamid) \
  69. SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
  70. QE_BASE_ADDR)
  71. #define SET_QMAN_ICID(streamid) \
  72. SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
  73. offsetof(struct ccsr_qman, liodnr) + \
  74. CONFIG_SYS_FSL_QMAN_ADDR, \
  75. CONFIG_SYS_FSL_QMAN_ADDR, false)
  76. #define SET_BMAN_ICID(streamid) \
  77. SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
  78. offsetof(struct ccsr_bman, liodnr) + \
  79. CONFIG_SYS_FSL_BMAN_ADDR, \
  80. CONFIG_SYS_FSL_BMAN_ADDR, false)
  81. #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
  82. { .port_id = (_port_id), .icid = (streamid) }
  83. #define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
  84. #define SET_SEC_QI_ICID(streamid) \
  85. SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
  86. 0, offsetof(ccsr_sec_t, qilcr_ls) + \
  87. CONFIG_SYS_FSL_SEC_ADDR, \
  88. CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
  89. extern struct fman_icid_id_table fman_icid_tbl[];
  90. extern int fman_icid_tbl_sz;
  91. #else /* CONFIG_FSL_LSCH2 */
  92. #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
  93. #define GUR_IS_LE true
  94. #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
  95. #define GUR_IS_LE false
  96. #endif
  97. #define QDMA_IS_LE true
  98. #define SET_GUR_ICID(compat, streamid, name, compataddr) \
  99. SET_ICID_ENTRY(compat, streamid, streamid, \
  100. offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
  101. compataddr, GUR_IS_LE)
  102. #define SET_USB_ICID(usb_num, compat, streamid) \
  103. SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
  104. CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
  105. #define SET_SATA_ICID(sata_num, compat, streamid) \
  106. SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
  107. AHCI_BASE_ADDR##sata_num)
  108. #define SET_SDHC_ICID(sdhc_num, streamid) \
  109. SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
  110. FSL_ESDHC##sdhc_num##_BASE_ADDR)
  111. #define SET_EDMA_ICID(streamid) \
  112. SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
  113. EDMA_BASE_ADDR)
  114. #define SET_GPU_ICID(compat, streamid) \
  115. SET_GUR_ICID(compat, streamid, misc1_amqr,\
  116. GPU_BASE_ADDR)
  117. #define SET_DISPLAY_ICID(streamid) \
  118. SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
  119. DISPLAY_BASE_ADDR)
  120. #define SEC_ICID_REG_VAL(streamid) (streamid)
  121. #endif /* CONFIG_FSL_LSCH2 */
  122. #define SET_QDMA_ICID(compat, streamid) \
  123. SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
  124. QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
  125. QDMA_BASE_ADDR, QDMA_IS_LE), \
  126. SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
  127. QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
  128. QDMA_BASE_ADDR, QDMA_IS_LE)
  129. #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
  130. SET_ICID_ENTRY( \
  131. (CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
  132. (FSL_SEC_JR##jr_num##_OFFSET == \
  133. SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
  134. ? NULL \
  135. : "fsl,sec-v4.0-job-ring"), \
  136. streamid, \
  137. SEC_ICID_REG_VAL(streamid), \
  138. offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
  139. CONFIG_SYS_FSL_SEC_ADDR, \
  140. FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
  141. #define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
  142. SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
  143. offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
  144. CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
  145. #define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
  146. SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
  147. offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
  148. CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
  149. extern struct icid_id_table icid_tbl[];
  150. extern int icid_tbl_sz;
  151. #endif