mp.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <image.h>
  8. #include <asm/cache.h>
  9. #include <asm/io.h>
  10. #include <asm/system.h>
  11. #include <asm/arch/mp.h>
  12. #include <asm/arch/soc.h>
  13. #include "cpu.h"
  14. #include <asm/arch-fsl-layerscape/soc.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. void *get_spin_tbl_addr(void)
  17. {
  18. return &__spin_table;
  19. }
  20. phys_addr_t determine_mp_bootpg(void)
  21. {
  22. return (phys_addr_t)&secondary_boot_code;
  23. }
  24. void update_os_arch_secondary_cores(uint8_t os_arch)
  25. {
  26. u64 *table = get_spin_tbl_addr();
  27. int i;
  28. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  29. if (os_arch == IH_ARCH_DEFAULT)
  30. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  31. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
  32. else
  33. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  34. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
  35. }
  36. }
  37. #ifdef CONFIG_FSL_LSCH3
  38. void wake_secondary_core_n(int cluster, int core, int cluster_cores)
  39. {
  40. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  41. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  42. u32 mpidr = 0;
  43. mpidr = ((cluster << 8) | core);
  44. /*
  45. * mpidr_el1 register value of core which needs to be released
  46. * is written to scratchrw[6] register
  47. */
  48. gur_out32(&gur->scratchrw[6], mpidr);
  49. asm volatile("dsb st" : : : "memory");
  50. rst->brrl |= 1 << ((cluster * cluster_cores) + core);
  51. asm volatile("dsb st" : : : "memory");
  52. /*
  53. * scratchrw[6] register value is polled
  54. * when the value becomes zero, this means that this core is up
  55. * and running, next core can be released now
  56. */
  57. while (gur_in32(&gur->scratchrw[6]) != 0)
  58. ;
  59. }
  60. #endif
  61. int fsl_layerscape_wake_seconday_cores(void)
  62. {
  63. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  64. #ifdef CONFIG_FSL_LSCH3
  65. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  66. u32 svr, ver, cluster, type;
  67. int j = 0, cluster_cores = 0;
  68. #elif defined(CONFIG_FSL_LSCH2)
  69. struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
  70. #endif
  71. u32 cores, cpu_up_mask = 1;
  72. int i, timeout = 10;
  73. u64 *table = get_spin_tbl_addr();
  74. #ifdef COUNTER_FREQUENCY_REAL
  75. /* update for secondary cores */
  76. __real_cntfrq = COUNTER_FREQUENCY_REAL;
  77. flush_dcache_range((unsigned long)&__real_cntfrq,
  78. (unsigned long)&__real_cntfrq + 8);
  79. #endif
  80. cores = cpu_mask();
  81. /* Clear spin table so that secondary processors
  82. * observe the correct value after waking up from wfe.
  83. */
  84. memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
  85. flush_dcache_range((unsigned long)table,
  86. (unsigned long)table +
  87. (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
  88. printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
  89. #ifdef CONFIG_FSL_LSCH3
  90. gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
  91. gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
  92. svr = gur_in32(&gur->svr);
  93. ver = SVR_SOC_VER(svr);
  94. if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
  95. gur_out32(&gur->scratchrw[6], 1);
  96. asm volatile("dsb st" : : : "memory");
  97. rst->brrl = cores;
  98. asm volatile("dsb st" : : : "memory");
  99. } else {
  100. /*
  101. * Release the cores out of reset one-at-a-time to avoid
  102. * power spikes
  103. */
  104. i = 0;
  105. cluster = in_le32(&gur->tp_cluster[i].lower);
  106. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  107. type = initiator_type(cluster, j);
  108. if (type &&
  109. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  110. cluster_cores++;
  111. }
  112. do {
  113. cluster = in_le32(&gur->tp_cluster[i].lower);
  114. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  115. type = initiator_type(cluster, j);
  116. if (type &&
  117. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  118. wake_secondary_core_n(i, j,
  119. cluster_cores);
  120. }
  121. i++;
  122. } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
  123. }
  124. #elif defined(CONFIG_FSL_LSCH2)
  125. scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
  126. scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
  127. asm volatile("dsb st" : : : "memory");
  128. gur_out32(&gur->brrl, cores);
  129. asm volatile("dsb st" : : : "memory");
  130. /* Bootup online cores */
  131. scfg_out32(&scfg->corebcr, cores);
  132. #endif
  133. /* This is needed as a precautionary measure.
  134. * If some code before this has accidentally released the secondary
  135. * cores then the pre-bootloader code will trap them in a "wfe" unless
  136. * the scratchrw[6] is set. In this case we need a sev here to get these
  137. * cores moving again.
  138. */
  139. asm volatile("sev");
  140. while (timeout--) {
  141. flush_dcache_range((unsigned long)table, (unsigned long)table +
  142. CONFIG_MAX_CPUS * 64);
  143. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  144. if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  145. SPIN_TABLE_ELEM_STATUS_IDX])
  146. cpu_up_mask |= 1 << i;
  147. }
  148. if (hweight32(cpu_up_mask) == hweight32(cores))
  149. break;
  150. udelay(10);
  151. }
  152. if (timeout <= 0) {
  153. printf("Not all cores (0x%x) are up (0x%x)\n",
  154. cores, cpu_up_mask);
  155. return 1;
  156. }
  157. printf("All (%d) cores are up.\n", hweight32(cores));
  158. return 0;
  159. }
  160. int is_core_valid(unsigned int core)
  161. {
  162. return !!((1 << core) & cpu_mask());
  163. }
  164. static int is_pos_valid(unsigned int pos)
  165. {
  166. return !!((1 << pos) & cpu_pos_mask());
  167. }
  168. int is_core_online(u64 cpu_id)
  169. {
  170. u64 *table;
  171. int pos = id_to_core(cpu_id);
  172. table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
  173. return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
  174. }
  175. int cpu_reset(u32 nr)
  176. {
  177. puts("Feature is not implemented.\n");
  178. return 0;
  179. }
  180. int cpu_disable(u32 nr)
  181. {
  182. puts("Feature is not implemented.\n");
  183. return 0;
  184. }
  185. static int core_to_pos(int nr)
  186. {
  187. u32 cores = cpu_pos_mask();
  188. int i, count = 0;
  189. if (nr == 0) {
  190. return 0;
  191. } else if (nr >= hweight32(cores)) {
  192. puts("Not a valid core number.\n");
  193. return -1;
  194. }
  195. for (i = 1; i < 32; i++) {
  196. if (is_pos_valid(i)) {
  197. count++;
  198. if (count == nr)
  199. break;
  200. }
  201. }
  202. if (count != nr)
  203. return -1;
  204. return i;
  205. }
  206. int cpu_status(u32 nr)
  207. {
  208. u64 *table;
  209. int pos;
  210. if (nr == 0) {
  211. table = (u64 *)get_spin_tbl_addr();
  212. printf("table base @ 0x%p\n", table);
  213. } else {
  214. pos = core_to_pos(nr);
  215. if (pos < 0)
  216. return -1;
  217. table = (u64 *)get_spin_tbl_addr() + pos *
  218. WORDS_PER_SPIN_TABLE_ENTRY;
  219. printf("table @ 0x%p\n", table);
  220. printf(" addr - 0x%016llx\n",
  221. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
  222. printf(" status - 0x%016llx\n",
  223. table[SPIN_TABLE_ELEM_STATUS_IDX]);
  224. printf(" lpid - 0x%016llx\n",
  225. table[SPIN_TABLE_ELEM_LPID_IDX]);
  226. }
  227. return 0;
  228. }
  229. int cpu_release(u32 nr, int argc, char *const argv[])
  230. {
  231. u64 boot_addr;
  232. u64 *table = (u64 *)get_spin_tbl_addr();
  233. int pos;
  234. pos = core_to_pos(nr);
  235. if (pos <= 0)
  236. return -1;
  237. table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
  238. boot_addr = simple_strtoull(argv[0], NULL, 16);
  239. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
  240. flush_dcache_range((unsigned long)table,
  241. (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
  242. asm volatile("dsb st");
  243. smp_kick_all_cpus(); /* only those with entry addr set will run */
  244. /*
  245. * When the first release command runs, all cores are set to go. Those
  246. * without a valid entry address will be trapped by "wfe". "sev" kicks
  247. * them off to check the address again. When set, they continue to run.
  248. */
  249. asm volatile("sev");
  250. return 0;
  251. }