fsl_lsch3_serdes.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016-2018 NXP
  4. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <asm/io.h>
  9. #include <linux/errno.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <asm/arch/soc.h>
  12. #include <fsl-mc/ldpaa_wriop.h>
  13. #ifdef CONFIG_SYS_FSL_SRDS_1
  14. static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  15. #endif
  16. #ifdef CONFIG_SYS_FSL_SRDS_2
  17. static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  18. #endif
  19. #ifdef CONFIG_SYS_NXP_SRDS_3
  20. static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  21. #endif
  22. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  23. #ifdef CONFIG_ARCH_LX2160A
  24. int xfi_dpmac[XFI14 + 1];
  25. int sgmii_dpmac[SGMII18 + 1];
  26. int a25gaui_dpmac[_25GE10 + 1];
  27. int xlaui_dpmac[_40GE2 + 1];
  28. int caui2_dpmac[_50GE2 + 1];
  29. int caui4_dpmac[_100GE2 + 1];
  30. #else
  31. int xfi_dpmac[XFI8 + 1];
  32. int sgmii_dpmac[SGMII16 + 1];
  33. #endif
  34. #endif
  35. __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  36. {
  37. return;
  38. }
  39. /*
  40. *The return value of this func is the serdes protocol used.
  41. *Typically this function is called number of times depending
  42. *upon the number of serdes blocks in the Silicon.
  43. *Zero is used to denote that no serdes was enabled,
  44. *this is the case when golden RCW was used where DPAA2 bring was
  45. *intentionally removed to achieve boot to prompt
  46. */
  47. __weak int serdes_get_number(int serdes, int cfg)
  48. {
  49. return cfg;
  50. }
  51. int is_serdes_configured(enum srds_prtcl device)
  52. {
  53. int ret = 0;
  54. #ifdef CONFIG_SYS_FSL_SRDS_1
  55. if (!serdes1_prtcl_map[NONE])
  56. fsl_serdes_init();
  57. ret |= serdes1_prtcl_map[device];
  58. #endif
  59. #ifdef CONFIG_SYS_FSL_SRDS_2
  60. if (!serdes2_prtcl_map[NONE])
  61. fsl_serdes_init();
  62. ret |= serdes2_prtcl_map[device];
  63. #endif
  64. #ifdef CONFIG_SYS_NXP_SRDS_3
  65. if (!serdes3_prtcl_map[NONE])
  66. fsl_serdes_init();
  67. ret |= serdes3_prtcl_map[device];
  68. #endif
  69. return !!ret;
  70. }
  71. int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  72. {
  73. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  74. u32 cfg = 0;
  75. int i;
  76. switch (sd) {
  77. #ifdef CONFIG_SYS_FSL_SRDS_1
  78. case FSL_SRDS_1:
  79. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  80. cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  81. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  82. break;
  83. #endif
  84. #ifdef CONFIG_SYS_FSL_SRDS_2
  85. case FSL_SRDS_2:
  86. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
  87. cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
  88. cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
  89. break;
  90. #endif
  91. #ifdef CONFIG_SYS_NXP_SRDS_3
  92. case NXP_SRDS_3:
  93. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
  94. cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
  95. cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
  96. break;
  97. #endif
  98. default:
  99. printf("invalid SerDes%d\n", sd);
  100. break;
  101. }
  102. cfg = serdes_get_number(sd, cfg);
  103. /* Is serdes enabled at all? */
  104. if (cfg == 0)
  105. return -ENODEV;
  106. for (i = 0; i < SRDS_MAX_LANES; i++) {
  107. if (serdes_get_prtcl(sd, cfg, i) == device)
  108. return i;
  109. }
  110. return -ENODEV;
  111. }
  112. void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
  113. u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
  114. {
  115. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  116. u32 cfg;
  117. int lane;
  118. if (serdes_prtcl_map[NONE])
  119. return;
  120. memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
  121. cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
  122. cfg >>= sd_prctl_shift;
  123. cfg = serdes_get_number(sd, cfg);
  124. printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
  125. if (!is_serdes_prtcl_valid(sd, cfg))
  126. printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
  127. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  128. enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
  129. if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
  130. debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
  131. else {
  132. serdes_prtcl_map[lane_prtcl] = 1;
  133. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  134. #ifdef CONFIG_ARCH_LX2160A
  135. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
  136. wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
  137. (int)lane_prtcl);
  138. if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
  139. wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
  140. (int)lane_prtcl);
  141. if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
  142. wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
  143. (int)lane_prtcl);
  144. if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
  145. wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
  146. (int)lane_prtcl);
  147. if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
  148. wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
  149. (int)lane_prtcl);
  150. if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
  151. wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
  152. (int)lane_prtcl);
  153. #else
  154. switch (lane_prtcl) {
  155. case QSGMII_A:
  156. case QSGMII_B:
  157. case QSGMII_C:
  158. case QSGMII_D:
  159. wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
  160. break;
  161. default:
  162. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
  163. wriop_init_dpmac(sd,
  164. xfi_dpmac[lane_prtcl],
  165. (int)lane_prtcl);
  166. if (lane_prtcl >= SGMII1 &&
  167. lane_prtcl <= SGMII16)
  168. wriop_init_dpmac(sd, sgmii_dpmac[
  169. lane_prtcl],
  170. (int)lane_prtcl);
  171. break;
  172. }
  173. #endif
  174. #endif
  175. }
  176. }
  177. /* Set the first element to indicate serdes has been initialized */
  178. serdes_prtcl_map[NONE] = 1;
  179. }
  180. __weak int get_serdes_volt(void)
  181. {
  182. return -1;
  183. }
  184. __weak int set_serdes_volt(int svdd)
  185. {
  186. return -1;
  187. }
  188. #define LNAGCR0_RT_RSTB 0x00600000
  189. #define RSTCTL_RESET_MASK 0x000000E0
  190. #define RSTCTL_RSTREQ 0x80000000
  191. #define RSTCTL_RST_DONE 0x40000000
  192. #define RSTCTL_RSTERR 0x20000000
  193. #define RSTCTL_SDEN 0x00000020
  194. #define RSTCTL_SDRST_B 0x00000040
  195. #define RSTCTL_PLLRST_B 0x00000080
  196. #define TCALCR_CALRST_B 0x08000000
  197. struct serdes_prctl_info {
  198. u32 id;
  199. u32 mask;
  200. u32 shift;
  201. };
  202. struct serdes_prctl_info srds_prctl_info[] = {
  203. #ifdef CONFIG_SYS_FSL_SRDS_1
  204. {.id = 1,
  205. .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  206. .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
  207. },
  208. #endif
  209. #ifdef CONFIG_SYS_FSL_SRDS_2
  210. {.id = 2,
  211. .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  212. .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
  213. },
  214. #endif
  215. #ifdef CONFIG_SYS_NXP_SRDS_3
  216. {.id = 3,
  217. .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  218. .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
  219. },
  220. #endif
  221. {} /* NULL ENTRY */
  222. };
  223. static int get_serdes_prctl_info_idx(u32 serdes_id)
  224. {
  225. int pos = 0;
  226. struct serdes_prctl_info *srds_info;
  227. /* loop until NULL ENTRY defined by .id=0 */
  228. for (srds_info = srds_prctl_info; srds_info->id != 0;
  229. srds_info++, pos++) {
  230. if (srds_info->id == serdes_id)
  231. return pos;
  232. }
  233. return -1;
  234. }
  235. static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
  236. struct ccsr_serdes __iomem *serdes_base,
  237. bool cmplt)
  238. {
  239. int i, pos;
  240. u32 cfg_tmp;
  241. pos = get_serdes_prctl_info_idx(serdes_id);
  242. if (pos == -1) {
  243. printf("invalid serdes_id %d\n", serdes_id);
  244. return;
  245. }
  246. cfg_tmp = cfg & srds_prctl_info[pos].mask;
  247. cfg_tmp >>= srds_prctl_info[pos].shift;
  248. for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
  249. if (cmplt)
  250. setbits_le32(&serdes_base->lane[i].gcr0,
  251. LNAGCR0_RT_RSTB);
  252. else
  253. clrbits_le32(&serdes_base->lane[i].gcr0,
  254. LNAGCR0_RT_RSTB);
  255. }
  256. }
  257. static void do_pll_reset(u32 cfg,
  258. struct ccsr_serdes __iomem *serdes_base)
  259. {
  260. int i;
  261. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  262. clrbits_le32(&serdes_base->bank[i].rstctl,
  263. RSTCTL_RESET_MASK);
  264. udelay(1);
  265. setbits_le32(&serdes_base->bank[i].rstctl,
  266. RSTCTL_RSTREQ);
  267. }
  268. udelay(1);
  269. }
  270. static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
  271. {
  272. clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  273. clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  274. }
  275. static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
  276. struct ccsr_serdes __iomem *serdes_base)
  277. {
  278. if (!(cfg == 0x3 && i == 1)) {
  279. udelay(1);
  280. setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  281. setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  282. }
  283. udelay(1);
  284. }
  285. static void do_pll_reset_done(u32 cfg,
  286. struct ccsr_serdes __iomem *serdes_base)
  287. {
  288. int i;
  289. u32 reg = 0;
  290. for (i = 0; i < 2; i++) {
  291. reg = in_le32(&serdes_base->bank[i].pllcr0);
  292. if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
  293. setbits_le32(&serdes_base->bank[i].rstctl,
  294. RSTCTL_RST_DONE);
  295. }
  296. }
  297. }
  298. static void do_serdes_enable(u32 cfg,
  299. struct ccsr_serdes __iomem *serdes_base)
  300. {
  301. int i;
  302. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  303. setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
  304. udelay(1);
  305. setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
  306. udelay(1);
  307. /* Take the Rx/Tx calibration out of reset */
  308. do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
  309. }
  310. }
  311. static void do_pll_lock(u32 cfg,
  312. struct ccsr_serdes __iomem *serdes_base)
  313. {
  314. int i;
  315. u32 reg = 0;
  316. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  317. /* if the PLL is not locked, set RST_ERR */
  318. reg = in_le32(&serdes_base->bank[i].pllcr0);
  319. if (!((reg >> 23) & 0x1)) {
  320. setbits_le32(&serdes_base->bank[i].rstctl,
  321. RSTCTL_RSTERR);
  322. } else {
  323. udelay(1);
  324. setbits_le32(&serdes_base->bank[i].rstctl,
  325. RSTCTL_SDRST_B);
  326. udelay(1);
  327. }
  328. }
  329. }
  330. int setup_serdes_volt(u32 svdd)
  331. {
  332. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  333. struct ccsr_serdes __iomem *serdes1_base =
  334. (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
  335. u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  336. #ifdef CONFIG_SYS_FSL_SRDS_2
  337. struct ccsr_serdes __iomem *serdes2_base =
  338. (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
  339. u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
  340. #endif
  341. #ifdef CONFIG_SYS_NXP_SRDS_3
  342. struct ccsr_serdes __iomem *serdes3_base =
  343. (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
  344. u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
  345. #endif
  346. u32 cfg_tmp;
  347. int svdd_cur, svdd_tar;
  348. int ret = 1;
  349. /* Only support switch SVDD to 900mV */
  350. if (svdd != 900)
  351. return -EINVAL;
  352. /* Scale up to the LTC resolution is 1/4096V */
  353. svdd = (svdd * 4096) / 1000;
  354. svdd_tar = svdd;
  355. svdd_cur = get_serdes_volt();
  356. if (svdd_cur < 0)
  357. return -EINVAL;
  358. debug("%s: current SVDD: %x; target SVDD: %x\n",
  359. __func__, svdd_cur, svdd_tar);
  360. if (svdd_cur == svdd_tar)
  361. return 0;
  362. /* Put the all enabled lanes in reset */
  363. #ifdef CONFIG_SYS_FSL_SRDS_1
  364. do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
  365. #endif
  366. #ifdef CONFIG_SYS_FSL_SRDS_2
  367. do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
  368. #endif
  369. #ifdef CONFIG_SYS_NXP_SRDS_3
  370. do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
  371. #endif
  372. /* Put the all enabled PLL in reset */
  373. #ifdef CONFIG_SYS_FSL_SRDS_1
  374. cfg_tmp = cfg_rcwsrds1 & 0x3;
  375. do_pll_reset(cfg_tmp, serdes1_base);
  376. #endif
  377. #ifdef CONFIG_SYS_FSL_SRDS_2
  378. cfg_tmp = cfg_rcwsrds1 & 0xC;
  379. cfg_tmp >>= 2;
  380. do_pll_reset(cfg_tmp, serdes2_base);
  381. #endif
  382. #ifdef CONFIG_SYS_NXP_SRDS_3
  383. cfg_tmp = cfg_rcwsrds3 & 0x30;
  384. cfg_tmp >>= 4;
  385. do_pll_reset(cfg_tmp, serdes3_base);
  386. #endif
  387. /* Put the Rx/Tx calibration into reset */
  388. #ifdef CONFIG_SYS_FSL_SRDS_1
  389. do_rx_tx_cal_reset(serdes1_base);
  390. #endif
  391. #ifdef CONFIG_SYS_FSL_SRDS_2
  392. do_rx_tx_cal_reset(serdes2_base);
  393. #endif
  394. #ifdef CONFIG_SYS_NXP_SRDS_3
  395. do_rx_tx_cal_reset(serdes3_base);
  396. #endif
  397. ret = set_serdes_volt(svdd);
  398. if (ret < 0) {
  399. printf("could not change SVDD\n");
  400. ret = -1;
  401. }
  402. /* For each PLL that’s not disabled via RCW enable the SERDES */
  403. #ifdef CONFIG_SYS_FSL_SRDS_1
  404. cfg_tmp = cfg_rcwsrds1 & 0x3;
  405. do_serdes_enable(cfg_tmp, serdes1_base);
  406. #endif
  407. #ifdef CONFIG_SYS_FSL_SRDS_2
  408. cfg_tmp = cfg_rcwsrds1 & 0xC;
  409. cfg_tmp >>= 2;
  410. do_serdes_enable(cfg_tmp, serdes2_base);
  411. #endif
  412. #ifdef CONFIG_SYS_NXP_SRDS_3
  413. cfg_tmp = cfg_rcwsrds3 & 0x30;
  414. cfg_tmp >>= 4;
  415. do_serdes_enable(cfg_tmp, serdes3_base);
  416. #endif
  417. /* Wait for at at least 625us, ensure the PLLs being reset are locked */
  418. udelay(800);
  419. #ifdef CONFIG_SYS_FSL_SRDS_1
  420. cfg_tmp = cfg_rcwsrds1 & 0x3;
  421. do_pll_lock(cfg_tmp, serdes1_base);
  422. #endif
  423. #ifdef CONFIG_SYS_FSL_SRDS_2
  424. cfg_tmp = cfg_rcwsrds1 & 0xC;
  425. cfg_tmp >>= 2;
  426. do_pll_lock(cfg_tmp, serdes2_base);
  427. #endif
  428. #ifdef CONFIG_SYS_NXP_SRDS_3
  429. cfg_tmp = cfg_rcwsrds3 & 0x30;
  430. cfg_tmp >>= 4;
  431. do_pll_lock(cfg_tmp, serdes3_base);
  432. #endif
  433. /* Take the all enabled lanes out of reset */
  434. #ifdef CONFIG_SYS_FSL_SRDS_1
  435. do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
  436. #endif
  437. #ifdef CONFIG_SYS_FSL_SRDS_2
  438. do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
  439. #endif
  440. #ifdef CONFIG_SYS_NXP_SRDS_3
  441. do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
  442. #endif
  443. /* For each PLL being reset, and achieved PLL lock set RST_DONE */
  444. #ifdef CONFIG_SYS_FSL_SRDS_1
  445. cfg_tmp = cfg_rcwsrds1 & 0x3;
  446. do_pll_reset_done(cfg_tmp, serdes1_base);
  447. #endif
  448. #ifdef CONFIG_SYS_FSL_SRDS_2
  449. cfg_tmp = cfg_rcwsrds1 & 0xC;
  450. cfg_tmp >>= 2;
  451. do_pll_reset_done(cfg_tmp, serdes2_base);
  452. #endif
  453. #ifdef CONFIG_SYS_NXP_SRDS_3
  454. cfg_tmp = cfg_rcwsrds3 & 0x30;
  455. cfg_tmp >>= 4;
  456. do_pll_reset_done(cfg_tmp, serdes3_base);
  457. #endif
  458. return ret;
  459. }
  460. void fsl_serdes_init(void)
  461. {
  462. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  463. int i , j;
  464. #ifdef CONFIG_ARCH_LX2160A
  465. for (i = XFI1, j = 1; i <= XFI14; i++, j++)
  466. xfi_dpmac[i] = j;
  467. for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
  468. sgmii_dpmac[i] = j;
  469. for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
  470. a25gaui_dpmac[i] = j;
  471. for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
  472. xlaui_dpmac[i] = j;
  473. for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
  474. caui2_dpmac[i] = j;
  475. for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
  476. caui4_dpmac[i] = j;
  477. #else
  478. for (i = XFI1, j = 1; i <= XFI8; i++, j++)
  479. xfi_dpmac[i] = j;
  480. for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
  481. sgmii_dpmac[i] = j;
  482. #endif
  483. #endif
  484. #ifdef CONFIG_SYS_FSL_SRDS_1
  485. serdes_init(FSL_SRDS_1,
  486. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
  487. FSL_CHASSIS3_SRDS1_REGSR,
  488. FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  489. FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
  490. serdes1_prtcl_map);
  491. #endif
  492. #ifdef CONFIG_SYS_FSL_SRDS_2
  493. serdes_init(FSL_SRDS_2,
  494. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
  495. FSL_CHASSIS3_SRDS2_REGSR,
  496. FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  497. FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
  498. serdes2_prtcl_map);
  499. #endif
  500. #ifdef CONFIG_SYS_NXP_SRDS_3
  501. serdes_init(NXP_SRDS_3,
  502. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
  503. FSL_CHASSIS3_SRDS3_REGSR,
  504. FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  505. FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
  506. serdes3_prtcl_map);
  507. #endif
  508. }
  509. int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
  510. {
  511. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  512. char scfg[16], snum[16];
  513. int cfgr = 0;
  514. u32 cfg;
  515. cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
  516. cfg >>= sd_prctl_shift;
  517. cfg = serdes_get_number(sd, cfg);
  518. #if defined(SRDS_BITS_PER_LANE)
  519. /*
  520. * reverse lanes, lane 0 should be printed first so it must be moved to
  521. * high order bits.
  522. * For example bb58 should read 85bb, lane 0 being protocol 8.
  523. * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
  524. * independent per-lane protocol configuration, at this time LS1028A and
  525. * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
  526. * lanes as a single value.
  527. */
  528. for (int i = 0; i < SRDS_MAX_LANES; i++) {
  529. int tmp;
  530. tmp = cfg >> (i * SRDS_BITS_PER_LANE);
  531. tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
  532. tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
  533. cfgr |= tmp;
  534. }
  535. #endif /* SRDS_BITS_PER_LANE */
  536. snprintf(snum, 16, "serdes%d", sd);
  537. snprintf(scfg, 16, "%x", cfgr);
  538. env_set(snum, scfg);
  539. return 0;
  540. }
  541. int serdes_misc_init(void)
  542. {
  543. #ifdef CONFIG_SYS_FSL_SRDS_1
  544. serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
  545. FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  546. FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
  547. #endif
  548. #ifdef CONFIG_SYS_FSL_SRDS_2
  549. serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
  550. FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  551. FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
  552. #endif
  553. #ifdef CONFIG_SYS_NXP_SRDS_3
  554. serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
  555. FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  556. FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
  557. #endif
  558. return 0;
  559. }