mpu_v7r.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Cortex-R Memory Protection Unit specific code
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <cpu_func.h>
  11. #include <asm/armv7.h>
  12. #include <asm/system.h>
  13. #include <asm/barriers.h>
  14. #include <linux/compiler.h>
  15. #include <asm/armv7_mpu.h>
  16. /* MPU Type register definitions */
  17. #define MPUIR_S_SHIFT 0
  18. #define MPUIR_S_MASK BIT(MPUIR_S_SHIFT)
  19. #define MPUIR_DREGION_SHIFT 8
  20. #define MPUIR_DREGION_MASK (0xff << 8)
  21. /**
  22. * Note:
  23. * The Memory Protection Unit(MPU) allows to partition memory into regions
  24. * and set individual protection attributes for each region. In absence
  25. * of MPU a default map[1] will take effect. make sure to run this code
  26. * from a region which has execution permissions by default.
  27. * [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html
  28. */
  29. void disable_mpu(void)
  30. {
  31. u32 reg;
  32. reg = get_cr();
  33. reg &= ~CR_M;
  34. dsb();
  35. set_cr(reg);
  36. isb();
  37. }
  38. void enable_mpu(void)
  39. {
  40. u32 reg;
  41. reg = get_cr();
  42. reg |= CR_M;
  43. dsb();
  44. set_cr(reg);
  45. isb();
  46. }
  47. int mpu_enabled(void)
  48. {
  49. return get_cr() & CR_M;
  50. }
  51. void mpu_config(struct mpu_region_config *rgn)
  52. {
  53. u32 attr, val;
  54. attr = get_attr_encoding(rgn->mr_attr);
  55. /* MPU Region Number Register */
  56. asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (rgn->region_no));
  57. /* MPU Region Base Address Register */
  58. asm volatile ("mcr p15, 0, %0, c6, c1, 0" : : "r" (rgn->start_addr));
  59. /* MPU Region Size and Enable Register */
  60. if (rgn->reg_size)
  61. val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION;
  62. else
  63. val = DISABLE_REGION;
  64. asm volatile ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val));
  65. /* MPU Region Access Control Register */
  66. val = rgn->xn << XN_SHIFT | rgn->ap << AP_SHIFT | attr;
  67. asm volatile ("mcr p15, 0, %0, c6, c1, 4" : : "r" (val));
  68. }
  69. void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns)
  70. {
  71. u32 num, i;
  72. asm volatile ("mrc p15, 0, %0, c0, c0, 4" : "=r" (num));
  73. num = (num & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT;
  74. /* Regions to be configured cannot be greater than available regions */
  75. if (num < num_rgns)
  76. num_rgns = num;
  77. /**
  78. * Assuming dcache might not be enabled at this point, disabling
  79. * and invalidating only icache.
  80. */
  81. icache_disable();
  82. invalidate_icache_all();
  83. disable_mpu();
  84. for (i = 0; i < num_rgns; i++)
  85. mpu_config(&rgns[i]);
  86. enable_mpu();
  87. icache_enable();
  88. }
  89. void enable_caches(void)
  90. {
  91. /*
  92. * setup_mpu_regions() might have enabled Icache. So add a check
  93. * before enabling Icache
  94. */
  95. if (!icache_status())
  96. icache_enable();
  97. dcache_enable();
  98. }