mxs.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX23/i.MX28 common code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  10. */
  11. #include <common.h>
  12. #include <command.h>
  13. #include <cpu_func.h>
  14. #include <hang.h>
  15. #include <init.h>
  16. #include <net.h>
  17. #include <linux/errno.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/mach-imx/dma.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/iomux.h>
  23. #include <asm/arch/imx-regs.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <linux/compiler.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
  28. __weak void lowlevel_init(void) {}
  29. void reset_cpu(ulong ignored) __attribute__((noreturn));
  30. void reset_cpu(ulong ignored)
  31. {
  32. struct mxs_rtc_regs *rtc_regs =
  33. (struct mxs_rtc_regs *)MXS_RTC_BASE;
  34. struct mxs_lcdif_regs *lcdif_regs =
  35. (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  36. /*
  37. * Shut down the LCD controller as it interferes with BootROM boot mode
  38. * pads sampling.
  39. */
  40. writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
  41. /* Wait 1 uS before doing the actual watchdog reset */
  42. writel(1, &rtc_regs->hw_rtc_watchdog);
  43. writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
  44. /* Endless loop, reset will exit from here */
  45. for (;;)
  46. ;
  47. }
  48. /*
  49. * This function will craft a jumptable at 0x0 which will redirect interrupt
  50. * vectoring to proper location of U-Boot in RAM.
  51. *
  52. * The structure of the jumptable will be as follows:
  53. * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
  54. * <destination address> ... for each previous ldr, thus also repeated 8 times
  55. *
  56. * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
  57. * offset 0x18 from current value of PC register. Note that PC is already
  58. * incremented by 4 when computing the offset, so the effective offset is
  59. * actually 0x20, this the associated <destination address>. Loading the PC
  60. * register with an address performs a jump to that address.
  61. */
  62. void mx28_fixup_vt(uint32_t start_addr)
  63. {
  64. /* ldr pc, [pc, #0x18] */
  65. const uint32_t ldr_pc = 0xe59ff018;
  66. /* Jumptable location is 0x0 */
  67. uint32_t *vt = (uint32_t *)0x0;
  68. int i;
  69. for (i = 0; i < 8; i++) {
  70. /* cppcheck-suppress nullPointer */
  71. vt[i] = ldr_pc;
  72. /* cppcheck-suppress nullPointer */
  73. vt[i + 8] = start_addr + (4 * i);
  74. }
  75. }
  76. #ifdef CONFIG_ARCH_MISC_INIT
  77. int arch_misc_init(void)
  78. {
  79. mx28_fixup_vt(gd->relocaddr);
  80. return 0;
  81. }
  82. #endif
  83. int arch_cpu_init(void)
  84. {
  85. struct mxs_clkctrl_regs *clkctrl_regs =
  86. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  87. extern uint32_t _start;
  88. mx28_fixup_vt((uint32_t)&_start);
  89. /*
  90. * Enable NAND clock
  91. */
  92. /* Set bypass bit */
  93. writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
  94. &clkctrl_regs->hw_clkctrl_clkseq_set);
  95. /* Set GPMI clock to ref_xtal / 1 */
  96. clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
  97. while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
  98. ;
  99. clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
  100. CLKCTRL_GPMI_DIV_MASK, 1);
  101. udelay(1000);
  102. /*
  103. * Configure GPIO unit
  104. */
  105. mxs_gpio_init();
  106. #ifdef CONFIG_APBH_DMA
  107. /* Start APBH DMA */
  108. mxs_dma_init();
  109. #endif
  110. return 0;
  111. }
  112. u32 get_cpu_rev(void)
  113. {
  114. struct mxs_digctl_regs *digctl_regs =
  115. (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
  116. uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
  117. switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
  118. case HW_DIGCTL_CHIPID_MX23:
  119. switch (rev) {
  120. case 0x0:
  121. case 0x1:
  122. case 0x2:
  123. case 0x3:
  124. case 0x4:
  125. return (MXC_CPU_MX23 << 12) | (rev + 0x10);
  126. default:
  127. return 0;
  128. }
  129. case HW_DIGCTL_CHIPID_MX28:
  130. switch (rev) {
  131. case 0x1:
  132. return (MXC_CPU_MX28 << 12) | 0x12;
  133. default:
  134. return 0;
  135. }
  136. default:
  137. return 0;
  138. }
  139. }
  140. #if defined(CONFIG_DISPLAY_CPUINFO)
  141. const char *get_imx_type(u32 imxtype)
  142. {
  143. switch (imxtype) {
  144. case MXC_CPU_MX23:
  145. return "23";
  146. case MXC_CPU_MX28:
  147. return "28";
  148. default:
  149. return "??";
  150. }
  151. }
  152. int print_cpuinfo(void)
  153. {
  154. u32 cpurev;
  155. struct mxs_spl_data *data = MXS_SPL_DATA;
  156. cpurev = get_cpu_rev();
  157. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  158. get_imx_type((cpurev & 0xFF000) >> 12),
  159. (cpurev & 0x000F0) >> 4,
  160. (cpurev & 0x0000F) >> 0,
  161. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  162. printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
  163. return 0;
  164. }
  165. #endif
  166. int do_mx28_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  167. char *const argv[])
  168. {
  169. printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  170. printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
  171. printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
  172. printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
  173. return 0;
  174. }
  175. /*
  176. * Initializes on-chip ethernet controllers.
  177. */
  178. #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
  179. int cpu_eth_init(bd_t *bis)
  180. {
  181. struct mxs_clkctrl_regs *clkctrl_regs =
  182. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  183. /* Turn on ENET clocks */
  184. clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
  185. CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
  186. /* Set up ENET PLL for 50 MHz */
  187. /* Power on ENET PLL */
  188. writel(CLKCTRL_PLL2CTRL0_POWER,
  189. &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
  190. udelay(10);
  191. /* Gate on ENET PLL */
  192. writel(CLKCTRL_PLL2CTRL0_CLKGATE,
  193. &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
  194. /* Enable pad output */
  195. setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
  196. return 0;
  197. }
  198. #endif
  199. __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
  200. {
  201. mac[0] = 0x00;
  202. mac[1] = 0x04; /* Use FSL vendor MAC address by default */
  203. if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
  204. mac[5] += 1;
  205. }
  206. #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
  207. #define MXS_OCOTP_MAX_TIMEOUT 1000000
  208. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  209. {
  210. struct mxs_ocotp_regs *ocotp_regs =
  211. (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
  212. uint32_t data;
  213. memset(mac, 0, 6);
  214. writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
  215. if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
  216. MXS_OCOTP_MAX_TIMEOUT)) {
  217. printf("MXS FEC: Can't get MAC from OCOTP\n");
  218. return;
  219. }
  220. data = readl(&ocotp_regs->hw_ocotp_cust0);
  221. mac[2] = (data >> 24) & 0xff;
  222. mac[3] = (data >> 16) & 0xff;
  223. mac[4] = (data >> 8) & 0xff;
  224. mac[5] = data & 0xff;
  225. mx28_adjust_mac(dev_id, mac);
  226. }
  227. #else
  228. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  229. {
  230. memset(mac, 0, 6);
  231. }
  232. #endif
  233. int mxs_dram_init(void)
  234. {
  235. struct mxs_spl_data *data = MXS_SPL_DATA;
  236. if (data->mem_dram_size == 0) {
  237. printf("MXS:\n"
  238. "Error, the RAM size passed up from SPL is 0!\n");
  239. hang();
  240. }
  241. gd->ram_size = data->mem_dram_size;
  242. return 0;
  243. }
  244. U_BOOT_CMD(
  245. clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
  246. "display clocks",
  247. ""
  248. );