mpc85xx_ddr_gen3.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008-2020 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <asm/processor.h>
  10. #include <linux/delay.h>
  11. #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  12. #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  13. #endif
  14. /*
  15. * regs has the to-be-set values for DDR controller registers
  16. * ctrl_num is the DDR controller number
  17. * step: 0 goes through the initialization in one pass
  18. * 1 sets registers and returns before enabling controller
  19. * 2 resumes from step 1 and continues to initialize
  20. * Dividing the initialization to two steps to deassert DDR reset signal
  21. * to comply with JEDEC specs for RDIMMs.
  22. */
  23. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  24. unsigned int ctrl_num, int step)
  25. {
  26. unsigned int i, bus_width;
  27. struct ccsr_ddr __iomem *ddr;
  28. u32 temp_sdram_cfg;
  29. u32 total_gb_size_per_controller;
  30. int timeout;
  31. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  32. int timeout_save;
  33. volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  34. unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  35. int csn = -1;
  36. #endif
  37. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
  38. u32 save1, save2;
  39. #endif
  40. #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) || \
  41. (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
  42. defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
  43. defined(CONFIG_SYS_FSL_ERRATUM_A008109)
  44. u32 val32;
  45. #endif
  46. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  47. unsigned int ddr_freq;
  48. #endif
  49. switch (ctrl_num) {
  50. case 0:
  51. ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  52. break;
  53. #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  54. case 1:
  55. ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  56. break;
  57. #endif
  58. #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  59. case 2:
  60. ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  61. break;
  62. #endif
  63. #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  64. case 3:
  65. ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  66. break;
  67. #endif
  68. default:
  69. printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  70. return;
  71. }
  72. if (step == 2)
  73. goto step2;
  74. if (regs->ddr_eor)
  75. out_be32(&ddr->eor, regs->ddr_eor);
  76. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  77. debug("Workaround for ERRATUM_DDR111_DDR134\n");
  78. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  79. cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  80. cs_ea = regs->cs[i].bnds & 0xfff;
  81. if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  82. csn = i;
  83. csn_bnds_backup = regs->cs[i].bnds;
  84. csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  85. if (cs_ea > 0xeff)
  86. *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  87. else
  88. *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  89. debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  90. "change it to 0x%x\n",
  91. csn, csn_bnds_backup, regs->cs[i].bnds);
  92. break;
  93. }
  94. }
  95. #endif
  96. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  97. if (i == 0) {
  98. out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  99. out_be32(&ddr->cs0_config, regs->cs[i].config);
  100. out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  101. } else if (i == 1) {
  102. out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  103. out_be32(&ddr->cs1_config, regs->cs[i].config);
  104. out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  105. } else if (i == 2) {
  106. out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  107. out_be32(&ddr->cs2_config, regs->cs[i].config);
  108. out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  109. } else if (i == 3) {
  110. out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  111. out_be32(&ddr->cs3_config, regs->cs[i].config);
  112. out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  113. }
  114. }
  115. out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  116. out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  117. out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  118. out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  119. out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  120. out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  121. out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
  122. out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
  123. out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
  124. out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
  125. out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
  126. out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
  127. out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  128. out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  129. out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
  130. out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  131. out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
  132. out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
  133. out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
  134. out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
  135. #ifndef CONFIG_SYS_FSL_DDR_EMU
  136. /*
  137. * Skip these two registers if running on emulator
  138. * because emulator doesn't have skew between bytes.
  139. */
  140. if (regs->ddr_wrlvl_cntl_2)
  141. out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
  142. if (regs->ddr_wrlvl_cntl_3)
  143. out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
  144. #endif
  145. out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
  146. out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
  147. out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
  148. out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
  149. #ifdef CONFIG_DEEP_SLEEP
  150. if (is_warm_boot()) {
  151. out_be32(&ddr->sdram_cfg_2,
  152. regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
  153. out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  154. out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
  155. /* DRAM VRef will not be trained */
  156. out_be32(&ddr->ddr_cdr2,
  157. regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
  158. } else
  159. #endif
  160. {
  161. out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  162. out_be32(&ddr->init_addr, regs->ddr_init_addr);
  163. out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  164. out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
  165. }
  166. out_be32(&ddr->err_disable, regs->err_disable);
  167. out_be32(&ddr->err_int_en, regs->err_int_en);
  168. for (i = 0; i < 32; i++) {
  169. if (regs->debug[i]) {
  170. debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
  171. out_be32(&ddr->debug[i], regs->debug[i]);
  172. }
  173. }
  174. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  175. out_be32(&ddr->debug[12], 0x00000015);
  176. out_be32(&ddr->debug[21], 0x24000000);
  177. #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
  178. /*
  179. * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
  180. * deasserted. Clocks start when any chip select is enabled and clock
  181. * control register is set. Because all DDR components are connected to
  182. * one reset signal, this needs to be done in two steps. Step 1 is to
  183. * get the clocks started. Step 2 resumes after reset signal is
  184. * deasserted.
  185. */
  186. if (step == 1) {
  187. udelay(200);
  188. return;
  189. }
  190. step2:
  191. /* Set, but do not enable the memory */
  192. temp_sdram_cfg = regs->ddr_sdram_cfg;
  193. temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
  194. out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
  195. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
  196. debug("Workaround for ERRATUM_DDR_A003\n");
  197. if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
  198. out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
  199. out_be32(&ddr->debug[2], 0x00000400);
  200. out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
  201. out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
  202. out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
  203. out_be32(&ddr->mtcr, 0);
  204. save1 = in_be32(&ddr->debug[12]);
  205. save2 = in_be32(&ddr->debug[21]);
  206. out_be32(&ddr->debug[12], 0x00000015);
  207. out_be32(&ddr->debug[21], 0x24000000);
  208. out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
  209. out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
  210. asm volatile("sync;isync");
  211. while (!(in_be32(&ddr->debug[1]) & 0x2))
  212. ;
  213. switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
  214. case 0x00000000:
  215. out_be32(&ddr->sdram_md_cntl,
  216. MD_CNTL_MD_EN |
  217. MD_CNTL_CS_SEL_CS0_CS1 |
  218. 0x04000000 |
  219. MD_CNTL_WRCW |
  220. MD_CNTL_MD_VALUE(0x02));
  221. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  222. if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
  223. break;
  224. while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
  225. ;
  226. out_be32(&ddr->sdram_md_cntl,
  227. MD_CNTL_MD_EN |
  228. MD_CNTL_CS_SEL_CS2_CS3 |
  229. 0x04000000 |
  230. MD_CNTL_WRCW |
  231. MD_CNTL_MD_VALUE(0x02));
  232. #endif
  233. break;
  234. case 0x00100000:
  235. out_be32(&ddr->sdram_md_cntl,
  236. MD_CNTL_MD_EN |
  237. MD_CNTL_CS_SEL_CS0_CS1 |
  238. 0x04000000 |
  239. MD_CNTL_WRCW |
  240. MD_CNTL_MD_VALUE(0x0a));
  241. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  242. if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
  243. break;
  244. while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
  245. ;
  246. out_be32(&ddr->sdram_md_cntl,
  247. MD_CNTL_MD_EN |
  248. MD_CNTL_CS_SEL_CS2_CS3 |
  249. 0x04000000 |
  250. MD_CNTL_WRCW |
  251. MD_CNTL_MD_VALUE(0x0a));
  252. #endif
  253. break;
  254. case 0x00200000:
  255. out_be32(&ddr->sdram_md_cntl,
  256. MD_CNTL_MD_EN |
  257. MD_CNTL_CS_SEL_CS0_CS1 |
  258. 0x04000000 |
  259. MD_CNTL_WRCW |
  260. MD_CNTL_MD_VALUE(0x12));
  261. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  262. if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
  263. break;
  264. while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
  265. ;
  266. out_be32(&ddr->sdram_md_cntl,
  267. MD_CNTL_MD_EN |
  268. MD_CNTL_CS_SEL_CS2_CS3 |
  269. 0x04000000 |
  270. MD_CNTL_WRCW |
  271. MD_CNTL_MD_VALUE(0x12));
  272. #endif
  273. break;
  274. case 0x00300000:
  275. out_be32(&ddr->sdram_md_cntl,
  276. MD_CNTL_MD_EN |
  277. MD_CNTL_CS_SEL_CS0_CS1 |
  278. 0x04000000 |
  279. MD_CNTL_WRCW |
  280. MD_CNTL_MD_VALUE(0x1a));
  281. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  282. if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
  283. break;
  284. while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
  285. ;
  286. out_be32(&ddr->sdram_md_cntl,
  287. MD_CNTL_MD_EN |
  288. MD_CNTL_CS_SEL_CS2_CS3 |
  289. 0x04000000 |
  290. MD_CNTL_WRCW |
  291. MD_CNTL_MD_VALUE(0x1a));
  292. #endif
  293. break;
  294. default:
  295. out_be32(&ddr->sdram_md_cntl,
  296. MD_CNTL_MD_EN |
  297. MD_CNTL_CS_SEL_CS0_CS1 |
  298. 0x04000000 |
  299. MD_CNTL_WRCW |
  300. MD_CNTL_MD_VALUE(0x02));
  301. #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  302. if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
  303. break;
  304. while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
  305. ;
  306. out_be32(&ddr->sdram_md_cntl,
  307. MD_CNTL_MD_EN |
  308. MD_CNTL_CS_SEL_CS2_CS3 |
  309. 0x04000000 |
  310. MD_CNTL_WRCW |
  311. MD_CNTL_MD_VALUE(0x02));
  312. #endif
  313. printf("Unsupported RC10\n");
  314. break;
  315. }
  316. while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
  317. ;
  318. udelay(6);
  319. out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
  320. out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  321. out_be32(&ddr->debug[2], 0x0);
  322. out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
  323. out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
  324. out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  325. out_be32(&ddr->debug[12], save1);
  326. out_be32(&ddr->debug[21], save2);
  327. out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  328. }
  329. #endif
  330. #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
  331. /* Erratum applies when accumulated ECC is used, or DBI is enabled */
  332. #define IS_ACC_ECC_EN(v) ((v) & 0x4)
  333. #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
  334. if (has_erratum_a008378()) {
  335. if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
  336. IS_DBI(regs->ddr_sdram_cfg_3)) {
  337. val32 = ddr_in32(&ddr->debug[28]);
  338. val32 |= (0x9 << 20);
  339. ddr_out32(&ddr->debug[28], val32);
  340. }
  341. debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
  342. }
  343. #endif
  344. #if defined(CONFIG_SYS_FSL_ERRATUM_A008109)
  345. val32 = in_be32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */
  346. out_be32(&ddr->sdram_cfg_2, val32);
  347. val32 = in_be32(&ddr->debug[18]) | 0x2;
  348. out_be32(&ddr->debug[18], val32);
  349. out_be32(&ddr->debug[28], 0x30000000);
  350. debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
  351. #endif
  352. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  353. ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
  354. val32 = in_be32(&ddr->debug[28]);
  355. val32 &= 0xff0fff00;
  356. if (ddr_freq <= 1333)
  357. val32 |= 0x0080006a;
  358. else if (ddr_freq <= 1600)
  359. val32 |= 0x0070006f;
  360. else if (ddr_freq <= 1867)
  361. val32 |= 0x00700076;
  362. else if (ddr_freq <= 2133)
  363. val32 |= 0x0060007b;
  364. out_be32(&ddr->debug[28], val32);
  365. debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
  366. #endif
  367. /*
  368. * For 8572 DDR1 erratum - DDR controller may enter illegal state
  369. * when operatiing in 32-bit bus mode with 4-beat bursts,
  370. * This erratum does not affect DDR3 mode, only for DDR2 mode.
  371. */
  372. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
  373. debug("Workaround for ERRATUM_DDR_115\n");
  374. if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
  375. && in_be32(&ddr->sdram_cfg) & 0x80000) {
  376. /* set DEBUG_1[31] */
  377. setbits_be32(&ddr->debug[0], 1);
  378. }
  379. #endif
  380. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  381. debug("Workaround for ERRATUM_DDR111_DDR134\n");
  382. /*
  383. * This is the combined workaround for DDR111 and DDR134
  384. * following the published errata for MPC8572
  385. */
  386. /* 1. Set EEBACR[3] */
  387. setbits_be32(&ecm->eebacr, 0x10000000);
  388. debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
  389. /* 2. Set DINIT in SDRAM_CFG_2*/
  390. setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
  391. debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
  392. in_be32(&ddr->sdram_cfg_2));
  393. /* 3. Set DEBUG_3[21] */
  394. setbits_be32(&ddr->debug[2], 0x400);
  395. debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
  396. #endif /* part 1 of the workaound */
  397. /*
  398. * 500 painful micro-seconds must elapse between
  399. * the DDR clock setup and the DDR config enable.
  400. * DDR2 need 200 us, and DDR3 need 500 us from spec,
  401. * we choose the max, that is 500 us for all of case.
  402. */
  403. udelay(500);
  404. asm volatile("sync;isync");
  405. #ifdef CONFIG_DEEP_SLEEP
  406. if (is_warm_boot()) {
  407. /* enter self-refresh */
  408. setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
  409. /* do board specific memory setup */
  410. board_mem_sleep_setup();
  411. temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
  412. } else
  413. #endif
  414. temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
  415. /* Let the controller go */
  416. out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
  417. asm volatile("sync;isync");
  418. total_gb_size_per_controller = 0;
  419. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  420. if (!(regs->cs[i].config & 0x80000000))
  421. continue;
  422. total_gb_size_per_controller += 1 << (
  423. ((regs->cs[i].config >> 14) & 0x3) + 2 +
  424. ((regs->cs[i].config >> 8) & 0x7) + 12 +
  425. ((regs->cs[i].config >> 0) & 0x7) + 8 +
  426. 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
  427. 26); /* minus 26 (count of 64M) */
  428. }
  429. if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
  430. total_gb_size_per_controller *= 3;
  431. else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
  432. total_gb_size_per_controller <<= 1;
  433. /*
  434. * total memory / bus width = transactions needed
  435. * transactions needed / data rate = seconds
  436. * to add plenty of buffer, double the time
  437. * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
  438. * Let's wait for 800ms
  439. */
  440. bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
  441. >> SDRAM_CFG_DBW_SHIFT);
  442. timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
  443. (get_ddr_freq(ctrl_num) >> 20)) << 1;
  444. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  445. timeout_save = timeout;
  446. #endif
  447. total_gb_size_per_controller >>= 4; /* shift down to gb size */
  448. debug("total %d GB\n", total_gb_size_per_controller);
  449. debug("Need to wait up to %d * 10ms\n", timeout);
  450. /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
  451. while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
  452. (timeout >= 0)) {
  453. udelay(10000); /* throttle polling rate */
  454. timeout--;
  455. }
  456. if (timeout <= 0)
  457. printf("Waiting for D_INIT timeout. Memory may not work.\n");
  458. #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  459. /* continue this workaround */
  460. /* 4. Clear DEBUG3[21] */
  461. clrbits_be32(&ddr->debug[2], 0x400);
  462. debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
  463. /* DDR134 workaround starts */
  464. /* A: Clear sdram_cfg_2[odt_cfg] */
  465. clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
  466. debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
  467. in_be32(&ddr->sdram_cfg_2));
  468. /* B: Set DEBUG1[15] */
  469. setbits_be32(&ddr->debug[0], 0x10000);
  470. debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
  471. /* C: Set timing_cfg_2[cpo] to 0b11111 */
  472. setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
  473. debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
  474. in_be32(&ddr->timing_cfg_2));
  475. /* D: Set D6 to 0x9f9f9f9f */
  476. out_be32(&ddr->debug[5], 0x9f9f9f9f);
  477. debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
  478. /* E: Set D7 to 0x9f9f9f9f */
  479. out_be32(&ddr->debug[6], 0x9f9f9f9f);
  480. debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
  481. /* F: Set D2[20] */
  482. setbits_be32(&ddr->debug[1], 0x800);
  483. debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
  484. /* G: Poll on D2[20] until cleared */
  485. while (in_be32(&ddr->debug[1]) & 0x800)
  486. udelay(10000); /* throttle polling rate */
  487. /* H: Clear D1[15] */
  488. clrbits_be32(&ddr->debug[0], 0x10000);
  489. debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
  490. /* I: Set sdram_cfg_2[odt_cfg] */
  491. setbits_be32(&ddr->sdram_cfg_2,
  492. regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
  493. debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
  494. /* Continuing with the DDR111 workaround */
  495. /* 5. Set D2[21] */
  496. setbits_be32(&ddr->debug[1], 0x400);
  497. debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
  498. /* 6. Poll D2[21] until its cleared */
  499. while (in_be32(&ddr->debug[1]) & 0x400)
  500. udelay(10000); /* throttle polling rate */
  501. /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
  502. debug("Wait for %d * 10ms\n", timeout_save);
  503. udelay(timeout_save * 10000);
  504. /* 8. Set sdram_cfg_2[dinit] if options requires */
  505. setbits_be32(&ddr->sdram_cfg_2,
  506. regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
  507. debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
  508. /* 9. Poll until dinit is cleared */
  509. timeout = timeout_save;
  510. debug("Need to wait up to %d * 10ms\n", timeout);
  511. while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
  512. (timeout >= 0)) {
  513. udelay(10000); /* throttle polling rate */
  514. timeout--;
  515. }
  516. if (timeout <= 0)
  517. printf("Waiting for D_INIT timeout. Memory may not work.\n");
  518. /* 10. Clear EEBACR[3] */
  519. clrbits_be32(&ecm->eebacr, 10000000);
  520. debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
  521. if (csn != -1) {
  522. csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
  523. *csn_bnds_t = csn_bnds_backup;
  524. debug("Change cs%d_bnds back to 0x%08x\n",
  525. csn, regs->cs[csn].bnds);
  526. setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */
  527. switch (csn) {
  528. case 0:
  529. out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
  530. break;
  531. case 1:
  532. out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
  533. break;
  534. #if CONFIG_CHIP_SELECTS_PER_CTRL > 2
  535. case 2:
  536. out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
  537. break;
  538. case 3:
  539. out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
  540. break;
  541. #endif
  542. }
  543. clrbits_be32(&ddr->sdram_cfg, 0x2);
  544. }
  545. #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
  546. #ifdef CONFIG_DEEP_SLEEP
  547. if (is_warm_boot())
  548. /* exit self-refresh */
  549. clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
  550. #endif
  551. }