ctrl_regs.c 75 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017-2020 NXP Semiconductor
  5. */
  6. /*
  7. * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
  8. * Based on code from spd_sdram.c
  9. * Author: James Yang [at freescale.com]
  10. */
  11. #include <common.h>
  12. #include <fsl_ddr_sdram.h>
  13. #include <fsl_errata.h>
  14. #include <fsl_ddr.h>
  15. #include <fsl_immap.h>
  16. #include <log.h>
  17. #include <asm/bitops.h>
  18. #include <asm/io.h>
  19. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  20. defined(CONFIG_ARM)
  21. #include <asm/arch/clock.h>
  22. #endif
  23. /*
  24. * Determine Rtt value.
  25. *
  26. * This should likely be either board or controller specific.
  27. *
  28. * Rtt(nominal) - DDR2:
  29. * 0 = Rtt disabled
  30. * 1 = 75 ohm
  31. * 2 = 150 ohm
  32. * 3 = 50 ohm
  33. * Rtt(nominal) - DDR3:
  34. * 0 = Rtt disabled
  35. * 1 = 60 ohm
  36. * 2 = 120 ohm
  37. * 3 = 40 ohm
  38. * 4 = 20 ohm
  39. * 5 = 30 ohm
  40. *
  41. * FIXME: Apparently 8641 needs a value of 2
  42. * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  43. *
  44. * FIXME: There was some effort down this line earlier:
  45. *
  46. * unsigned int i;
  47. * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  48. * if (popts->dimmslot[i].num_valid_cs
  49. * && (popts->cs_local_opts[2*i].odt_rd_cfg
  50. * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  51. * rtt = 2;
  52. * break;
  53. * }
  54. * }
  55. */
  56. static inline int fsl_ddr_get_rtt(void)
  57. {
  58. int rtt;
  59. #if defined(CONFIG_SYS_FSL_DDR1)
  60. rtt = 0;
  61. #elif defined(CONFIG_SYS_FSL_DDR2)
  62. rtt = 3;
  63. #else
  64. rtt = 0;
  65. #endif
  66. return rtt;
  67. }
  68. #ifdef CONFIG_SYS_FSL_DDR4
  69. /*
  70. * compute CAS write latency according to DDR4 spec
  71. * CWL = 9 for <= 1600MT/s
  72. * 10 for <= 1866MT/s
  73. * 11 for <= 2133MT/s
  74. * 12 for <= 2400MT/s
  75. * 14 for <= 2667MT/s
  76. * 16 for <= 2933MT/s
  77. * 18 for higher
  78. */
  79. static inline unsigned int compute_cas_write_latency(
  80. const unsigned int ctrl_num)
  81. {
  82. unsigned int cwl;
  83. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  84. if (mclk_ps >= 1250)
  85. cwl = 9;
  86. else if (mclk_ps >= 1070)
  87. cwl = 10;
  88. else if (mclk_ps >= 935)
  89. cwl = 11;
  90. else if (mclk_ps >= 833)
  91. cwl = 12;
  92. else if (mclk_ps >= 750)
  93. cwl = 14;
  94. else if (mclk_ps >= 681)
  95. cwl = 16;
  96. else
  97. cwl = 18;
  98. return cwl;
  99. }
  100. #else
  101. /*
  102. * compute the CAS write latency according to DDR3 spec
  103. * CWL = 5 if tCK >= 2.5ns
  104. * 6 if 2.5ns > tCK >= 1.875ns
  105. * 7 if 1.875ns > tCK >= 1.5ns
  106. * 8 if 1.5ns > tCK >= 1.25ns
  107. * 9 if 1.25ns > tCK >= 1.07ns
  108. * 10 if 1.07ns > tCK >= 0.935ns
  109. * 11 if 0.935ns > tCK >= 0.833ns
  110. * 12 if 0.833ns > tCK >= 0.75ns
  111. */
  112. static inline unsigned int compute_cas_write_latency(
  113. const unsigned int ctrl_num)
  114. {
  115. unsigned int cwl;
  116. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  117. if (mclk_ps >= 2500)
  118. cwl = 5;
  119. else if (mclk_ps >= 1875)
  120. cwl = 6;
  121. else if (mclk_ps >= 1500)
  122. cwl = 7;
  123. else if (mclk_ps >= 1250)
  124. cwl = 8;
  125. else if (mclk_ps >= 1070)
  126. cwl = 9;
  127. else if (mclk_ps >= 935)
  128. cwl = 10;
  129. else if (mclk_ps >= 833)
  130. cwl = 11;
  131. else if (mclk_ps >= 750)
  132. cwl = 12;
  133. else {
  134. cwl = 12;
  135. printf("Warning: CWL is out of range\n");
  136. }
  137. return cwl;
  138. }
  139. #endif
  140. /* Chip Select Configuration (CSn_CONFIG) */
  141. static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
  142. const memctl_options_t *popts,
  143. const dimm_params_t *dimm_params)
  144. {
  145. unsigned int cs_n_en = 0; /* Chip Select enable */
  146. unsigned int intlv_en = 0; /* Memory controller interleave enable */
  147. unsigned int intlv_ctl = 0; /* Interleaving control */
  148. unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
  149. unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
  150. unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
  151. unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
  152. unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
  153. unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
  154. int go_config = 0;
  155. #ifdef CONFIG_SYS_FSL_DDR4
  156. unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
  157. #else
  158. unsigned int n_banks_per_sdram_device;
  159. #endif
  160. /* Compute CS_CONFIG only for existing ranks of each DIMM. */
  161. switch (i) {
  162. case 0:
  163. if (dimm_params[dimm_number].n_ranks > 0) {
  164. go_config = 1;
  165. /* These fields only available in CS0_CONFIG */
  166. if (!popts->memctl_interleaving)
  167. break;
  168. switch (popts->memctl_interleaving_mode) {
  169. case FSL_DDR_256B_INTERLEAVING:
  170. case FSL_DDR_CACHE_LINE_INTERLEAVING:
  171. case FSL_DDR_PAGE_INTERLEAVING:
  172. case FSL_DDR_BANK_INTERLEAVING:
  173. case FSL_DDR_SUPERBANK_INTERLEAVING:
  174. intlv_en = popts->memctl_interleaving;
  175. intlv_ctl = popts->memctl_interleaving_mode;
  176. break;
  177. default:
  178. break;
  179. }
  180. }
  181. break;
  182. case 1:
  183. if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
  184. (dimm_number == 1 && dimm_params[1].n_ranks > 0))
  185. go_config = 1;
  186. break;
  187. case 2:
  188. if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
  189. (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
  190. go_config = 1;
  191. break;
  192. case 3:
  193. if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
  194. (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
  195. (dimm_number == 3 && dimm_params[3].n_ranks > 0))
  196. go_config = 1;
  197. break;
  198. default:
  199. break;
  200. }
  201. if (go_config) {
  202. cs_n_en = 1;
  203. ap_n_en = popts->cs_local_opts[i].auto_precharge;
  204. odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
  205. odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
  206. #ifdef CONFIG_SYS_FSL_DDR4
  207. ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
  208. bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
  209. #else
  210. n_banks_per_sdram_device
  211. = dimm_params[dimm_number].n_banks_per_sdram_device;
  212. ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
  213. #endif
  214. row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
  215. col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
  216. }
  217. ddr->cs[i].config = (0
  218. | ((cs_n_en & 0x1) << 31)
  219. | ((intlv_en & 0x3) << 29)
  220. | ((intlv_ctl & 0xf) << 24)
  221. | ((ap_n_en & 0x1) << 23)
  222. /* XXX: some implementation only have 1 bit starting at left */
  223. | ((odt_rd_cfg & 0x7) << 20)
  224. /* XXX: Some implementation only have 1 bit starting at left */
  225. | ((odt_wr_cfg & 0x7) << 16)
  226. | ((ba_bits_cs_n & 0x3) << 14)
  227. | ((row_bits_cs_n & 0x7) << 8)
  228. #ifdef CONFIG_SYS_FSL_DDR4
  229. | ((bg_bits_cs_n & 0x3) << 4)
  230. #endif
  231. | ((col_bits_cs_n & 0x7) << 0)
  232. );
  233. debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
  234. }
  235. /* Chip Select Configuration 2 (CSn_CONFIG_2) */
  236. /* FIXME: 8572 */
  237. static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
  238. {
  239. unsigned int pasr_cfg = 0; /* Partial array self refresh config */
  240. ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
  241. debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
  242. }
  243. /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
  244. #if !defined(CONFIG_SYS_FSL_DDR1)
  245. /*
  246. * Check DIMM configuration, return 2 if quad-rank or two dual-rank
  247. * Return 1 if other two slots configuration. Return 0 if single slot.
  248. */
  249. static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
  250. {
  251. #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
  252. if (dimm_params[0].n_ranks == 4)
  253. return 2;
  254. #endif
  255. #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
  256. if ((dimm_params[0].n_ranks == 2) &&
  257. (dimm_params[1].n_ranks == 2))
  258. return 2;
  259. #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  260. if (dimm_params[0].n_ranks == 4)
  261. return 2;
  262. #endif
  263. if ((dimm_params[0].n_ranks != 0) &&
  264. (dimm_params[2].n_ranks != 0))
  265. return 1;
  266. #endif
  267. return 0;
  268. }
  269. /*
  270. * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
  271. *
  272. * Avoid writing for DDR I. The new PQ38 DDR controller
  273. * dreams up non-zero default values to be backwards compatible.
  274. */
  275. static void set_timing_cfg_0(const unsigned int ctrl_num,
  276. fsl_ddr_cfg_regs_t *ddr,
  277. const memctl_options_t *popts,
  278. const dimm_params_t *dimm_params)
  279. {
  280. unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
  281. unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
  282. /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
  283. unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
  284. unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
  285. /* Active powerdown exit timing (tXARD and tXARDS). */
  286. unsigned char act_pd_exit_mclk;
  287. /* Precharge powerdown exit timing (tXP). */
  288. unsigned char pre_pd_exit_mclk;
  289. /* ODT powerdown exit timing (tAXPD). */
  290. unsigned char taxpd_mclk = 0;
  291. /* Mode register set cycle time (tMRD). */
  292. unsigned char tmrd_mclk;
  293. #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
  294. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  295. #endif
  296. #ifdef CONFIG_SYS_FSL_DDR4
  297. /* tXP=max(4nCK, 6ns) */
  298. int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
  299. unsigned int data_rate = get_ddr_freq(ctrl_num);
  300. /* for faster clock, need more time for data setup */
  301. trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
  302. /*
  303. * for single quad-rank DIMM and two-slot DIMMs
  304. * to avoid ODT overlap
  305. */
  306. switch (avoid_odt_overlap(dimm_params)) {
  307. case 2:
  308. twrt_mclk = 2;
  309. twwt_mclk = 2;
  310. trrt_mclk = 2;
  311. break;
  312. default:
  313. twrt_mclk = 1;
  314. twwt_mclk = 1;
  315. trrt_mclk = 0;
  316. break;
  317. }
  318. act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
  319. pre_pd_exit_mclk = act_pd_exit_mclk;
  320. /*
  321. * MRS_CYC = max(tMRD, tMOD)
  322. * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
  323. */
  324. tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
  325. #elif defined(CONFIG_SYS_FSL_DDR3)
  326. unsigned int data_rate = get_ddr_freq(ctrl_num);
  327. int txp;
  328. unsigned int ip_rev;
  329. int odt_overlap;
  330. /*
  331. * (tXARD and tXARDS). Empirical?
  332. * The DDR3 spec has not tXARD,
  333. * we use the tXP instead of it.
  334. * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
  335. * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
  336. * spec has not the tAXPD, we use
  337. * tAXPD=1, need design to confirm.
  338. */
  339. txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
  340. ip_rev = fsl_ddr_get_version(ctrl_num);
  341. if (ip_rev >= 0x40700) {
  342. /*
  343. * MRS_CYC = max(tMRD, tMOD)
  344. * tMRD = 4nCK (8nCK for RDIMM)
  345. * tMOD = max(12nCK, 15ns)
  346. */
  347. tmrd_mclk = max((unsigned int)12,
  348. picos_to_mclk(ctrl_num, 15000));
  349. } else {
  350. /*
  351. * MRS_CYC = tMRD
  352. * tMRD = 4nCK (8nCK for RDIMM)
  353. */
  354. if (popts->registered_dimm_en)
  355. tmrd_mclk = 8;
  356. else
  357. tmrd_mclk = 4;
  358. }
  359. /* set the turnaround time */
  360. /*
  361. * for single quad-rank DIMM and two-slot DIMMs
  362. * to avoid ODT overlap
  363. */
  364. odt_overlap = avoid_odt_overlap(dimm_params);
  365. switch (odt_overlap) {
  366. case 2:
  367. twwt_mclk = 2;
  368. trrt_mclk = 1;
  369. break;
  370. case 1:
  371. twwt_mclk = 1;
  372. trrt_mclk = 0;
  373. break;
  374. default:
  375. break;
  376. }
  377. /* for faster clock, need more time for data setup */
  378. trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
  379. if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
  380. twrt_mclk = 1;
  381. if (popts->dynamic_power == 0) { /* powerdown is not used */
  382. act_pd_exit_mclk = 1;
  383. pre_pd_exit_mclk = 1;
  384. taxpd_mclk = 1;
  385. } else {
  386. /* act_pd_exit_mclk = tXARD, see above */
  387. act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
  388. /* Mode register MR0[A12] is '1' - fast exit */
  389. pre_pd_exit_mclk = act_pd_exit_mclk;
  390. taxpd_mclk = 1;
  391. }
  392. #else /* CONFIG_SYS_FSL_DDR2 */
  393. /*
  394. * (tXARD and tXARDS). Empirical?
  395. * tXARD = 2 for DDR2
  396. * tXP=2
  397. * tAXPD=8
  398. */
  399. act_pd_exit_mclk = 2;
  400. pre_pd_exit_mclk = 2;
  401. taxpd_mclk = 8;
  402. tmrd_mclk = 2;
  403. #endif
  404. if (popts->trwt_override)
  405. trwt_mclk = popts->trwt;
  406. ddr->timing_cfg_0 = (0
  407. | ((trwt_mclk & 0x3) << 30) /* RWT */
  408. | ((twrt_mclk & 0x3) << 28) /* WRT */
  409. | ((trrt_mclk & 0x3) << 26) /* RRT */
  410. | ((twwt_mclk & 0x3) << 24) /* WWT */
  411. | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
  412. | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
  413. | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
  414. | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
  415. );
  416. debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
  417. }
  418. #endif /* !defined(CONFIG_SYS_FSL_DDR1) */
  419. /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
  420. static void set_timing_cfg_3(const unsigned int ctrl_num,
  421. fsl_ddr_cfg_regs_t *ddr,
  422. const memctl_options_t *popts,
  423. const common_timing_params_t *common_dimm,
  424. unsigned int cas_latency,
  425. unsigned int additive_latency)
  426. {
  427. /* Extended precharge to activate interval (tRP) */
  428. unsigned int ext_pretoact = 0;
  429. /* Extended Activate to precharge interval (tRAS) */
  430. unsigned int ext_acttopre = 0;
  431. /* Extended activate to read/write interval (tRCD) */
  432. unsigned int ext_acttorw = 0;
  433. /* Extended refresh recovery time (tRFC) */
  434. unsigned int ext_refrec;
  435. /* Extended MCAS latency from READ cmd */
  436. unsigned int ext_caslat = 0;
  437. /* Extended additive latency */
  438. unsigned int ext_add_lat = 0;
  439. /* Extended last data to precharge interval (tWR) */
  440. unsigned int ext_wrrec = 0;
  441. /* Control Adjust */
  442. unsigned int cntl_adj = 0;
  443. ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
  444. ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
  445. ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
  446. ext_caslat = (2 * cas_latency - 1) >> 4;
  447. ext_add_lat = additive_latency >> 4;
  448. #ifdef CONFIG_SYS_FSL_DDR4
  449. ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
  450. #else
  451. ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
  452. /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
  453. #endif
  454. ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
  455. (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
  456. ddr->timing_cfg_3 = (0
  457. | ((ext_pretoact & 0x1) << 28)
  458. | ((ext_acttopre & 0x3) << 24)
  459. | ((ext_acttorw & 0x1) << 22)
  460. | ((ext_refrec & 0x3F) << 16)
  461. | ((ext_caslat & 0x3) << 12)
  462. | ((ext_add_lat & 0x1) << 10)
  463. | ((ext_wrrec & 0x1) << 8)
  464. | ((cntl_adj & 0x7) << 0)
  465. );
  466. debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
  467. }
  468. /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
  469. static void set_timing_cfg_1(const unsigned int ctrl_num,
  470. fsl_ddr_cfg_regs_t *ddr,
  471. const memctl_options_t *popts,
  472. const common_timing_params_t *common_dimm,
  473. unsigned int cas_latency)
  474. {
  475. /* Precharge-to-activate interval (tRP) */
  476. unsigned char pretoact_mclk;
  477. /* Activate to precharge interval (tRAS) */
  478. unsigned char acttopre_mclk;
  479. /* Activate to read/write interval (tRCD) */
  480. unsigned char acttorw_mclk;
  481. /* CASLAT */
  482. unsigned char caslat_ctrl;
  483. /* Refresh recovery time (tRFC) ; trfc_low */
  484. unsigned char refrec_ctrl;
  485. /* Last data to precharge minimum interval (tWR) */
  486. unsigned char wrrec_mclk;
  487. /* Activate-to-activate interval (tRRD) */
  488. unsigned char acttoact_mclk;
  489. /* Last write data pair to read command issue interval (tWTR) */
  490. unsigned char wrtord_mclk;
  491. #ifdef CONFIG_SYS_FSL_DDR4
  492. /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
  493. static const u8 wrrec_table[] = {
  494. 10, 10, 10, 10, 10,
  495. 10, 10, 10, 10, 10,
  496. 12, 12, 14, 14, 16,
  497. 16, 18, 18, 20, 20,
  498. 24, 24, 24, 24};
  499. #else
  500. /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
  501. static const u8 wrrec_table[] = {
  502. 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
  503. #endif
  504. pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
  505. acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
  506. acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
  507. /*
  508. * Translate CAS Latency to a DDR controller field value:
  509. *
  510. * CAS Lat DDR I DDR II Ctrl
  511. * Clocks SPD Bit SPD Bit Value
  512. * ------- ------- ------- -----
  513. * 1.0 0 0001
  514. * 1.5 1 0010
  515. * 2.0 2 2 0011
  516. * 2.5 3 0100
  517. * 3.0 4 3 0101
  518. * 3.5 5 0110
  519. * 4.0 4 0111
  520. * 4.5 1000
  521. * 5.0 5 1001
  522. */
  523. #if defined(CONFIG_SYS_FSL_DDR1)
  524. caslat_ctrl = (cas_latency + 1) & 0x07;
  525. #elif defined(CONFIG_SYS_FSL_DDR2)
  526. caslat_ctrl = 2 * cas_latency - 1;
  527. #else
  528. /*
  529. * if the CAS latency more than 8 cycle,
  530. * we need set extend bit for it at
  531. * TIMING_CFG_3[EXT_CASLAT]
  532. */
  533. if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
  534. caslat_ctrl = 2 * cas_latency - 1;
  535. else
  536. caslat_ctrl = (cas_latency - 1) << 1;
  537. #endif
  538. #ifdef CONFIG_SYS_FSL_DDR4
  539. refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
  540. wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  541. acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
  542. wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
  543. if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
  544. printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
  545. else
  546. wrrec_mclk = wrrec_table[wrrec_mclk - 1];
  547. #else
  548. refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
  549. wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  550. acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
  551. wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
  552. if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
  553. printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
  554. else
  555. wrrec_mclk = wrrec_table[wrrec_mclk - 1];
  556. #endif
  557. if (popts->otf_burst_chop_en)
  558. wrrec_mclk += 2;
  559. /*
  560. * JEDEC has min requirement for tRRD
  561. */
  562. #if defined(CONFIG_SYS_FSL_DDR3)
  563. if (acttoact_mclk < 4)
  564. acttoact_mclk = 4;
  565. #endif
  566. /*
  567. * JEDEC has some min requirements for tWTR
  568. */
  569. #if defined(CONFIG_SYS_FSL_DDR2)
  570. if (wrtord_mclk < 2)
  571. wrtord_mclk = 2;
  572. #elif defined(CONFIG_SYS_FSL_DDR3)
  573. if (wrtord_mclk < 4)
  574. wrtord_mclk = 4;
  575. #endif
  576. if (popts->otf_burst_chop_en)
  577. wrtord_mclk += 2;
  578. ddr->timing_cfg_1 = (0
  579. | ((pretoact_mclk & 0x0F) << 28)
  580. | ((acttopre_mclk & 0x0F) << 24)
  581. | ((acttorw_mclk & 0xF) << 20)
  582. | ((caslat_ctrl & 0xF) << 16)
  583. | ((refrec_ctrl & 0xF) << 12)
  584. | ((wrrec_mclk & 0x0F) << 8)
  585. | ((acttoact_mclk & 0x0F) << 4)
  586. | ((wrtord_mclk & 0x0F) << 0)
  587. );
  588. debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
  589. }
  590. /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
  591. static void set_timing_cfg_2(const unsigned int ctrl_num,
  592. fsl_ddr_cfg_regs_t *ddr,
  593. const memctl_options_t *popts,
  594. const common_timing_params_t *common_dimm,
  595. unsigned int cas_latency,
  596. unsigned int additive_latency)
  597. {
  598. /* Additive latency */
  599. unsigned char add_lat_mclk;
  600. /* CAS-to-preamble override */
  601. unsigned short cpo;
  602. /* Write latency */
  603. unsigned char wr_lat;
  604. /* Read to precharge (tRTP) */
  605. unsigned char rd_to_pre;
  606. /* Write command to write data strobe timing adjustment */
  607. unsigned char wr_data_delay;
  608. /* Minimum CKE pulse width (tCKE) */
  609. unsigned char cke_pls;
  610. /* Window for four activates (tFAW) */
  611. unsigned short four_act;
  612. #ifdef CONFIG_SYS_FSL_DDR3
  613. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  614. #endif
  615. /* FIXME add check that this must be less than acttorw_mclk */
  616. add_lat_mclk = additive_latency;
  617. cpo = popts->cpo_override;
  618. #if defined(CONFIG_SYS_FSL_DDR1)
  619. /*
  620. * This is a lie. It should really be 1, but if it is
  621. * set to 1, bits overlap into the old controller's
  622. * otherwise unused ACSM field. If we leave it 0, then
  623. * the HW will magically treat it as 1 for DDR 1. Oh Yea.
  624. */
  625. wr_lat = 0;
  626. #elif defined(CONFIG_SYS_FSL_DDR2)
  627. wr_lat = cas_latency - 1;
  628. #else
  629. wr_lat = compute_cas_write_latency(ctrl_num);
  630. #endif
  631. #ifdef CONFIG_SYS_FSL_DDR4
  632. rd_to_pre = picos_to_mclk(ctrl_num, 7500);
  633. #else
  634. rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
  635. #endif
  636. /*
  637. * JEDEC has some min requirements for tRTP
  638. */
  639. #if defined(CONFIG_SYS_FSL_DDR2)
  640. if (rd_to_pre < 2)
  641. rd_to_pre = 2;
  642. #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  643. if (rd_to_pre < 4)
  644. rd_to_pre = 4;
  645. #endif
  646. if (popts->otf_burst_chop_en)
  647. rd_to_pre += 2; /* according to UM */
  648. wr_data_delay = popts->write_data_delay;
  649. #ifdef CONFIG_SYS_FSL_DDR4
  650. cpo = 0;
  651. cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
  652. #elif defined(CONFIG_SYS_FSL_DDR3)
  653. /*
  654. * cke pulse = max(3nCK, 7.5ns) for DDR3-800
  655. * max(3nCK, 5.625ns) for DDR3-1066, 1333
  656. * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
  657. */
  658. cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
  659. (mclk_ps > 1245 ? 5625 : 5000)));
  660. #else
  661. cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
  662. #endif
  663. four_act = picos_to_mclk(ctrl_num,
  664. popts->tfaw_window_four_activates_ps);
  665. ddr->timing_cfg_2 = (0
  666. | ((add_lat_mclk & 0xf) << 28)
  667. | ((cpo & 0x1f) << 23)
  668. | ((wr_lat & 0xf) << 19)
  669. | (((wr_lat & 0x10) >> 4) << 18)
  670. | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
  671. | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
  672. | ((cke_pls & 0x7) << 6)
  673. | ((four_act & 0x3f) << 0)
  674. );
  675. debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
  676. }
  677. /* DDR SDRAM Register Control Word */
  678. static void set_ddr_sdram_rcw(const unsigned int ctrl_num,
  679. fsl_ddr_cfg_regs_t *ddr,
  680. const memctl_options_t *popts,
  681. const common_timing_params_t *common_dimm)
  682. {
  683. unsigned int ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
  684. unsigned int rc0a, rc0f;
  685. if (common_dimm->all_dimms_registered &&
  686. !common_dimm->all_dimms_unbuffered) {
  687. if (popts->rcw_override) {
  688. ddr->ddr_sdram_rcw_1 = popts->rcw_1;
  689. ddr->ddr_sdram_rcw_2 = popts->rcw_2;
  690. ddr->ddr_sdram_rcw_3 = popts->rcw_3;
  691. } else {
  692. rc0a = ddr_freq > 3200 ? 0x7 :
  693. (ddr_freq > 2933 ? 0x6 :
  694. (ddr_freq > 2666 ? 0x5 :
  695. (ddr_freq > 2400 ? 0x4 :
  696. (ddr_freq > 2133 ? 0x3 :
  697. (ddr_freq > 1866 ? 0x2 :
  698. (ddr_freq > 1600 ? 1 : 0))))));
  699. rc0f = ddr_freq > 3200 ? 0x3 :
  700. (ddr_freq > 2400 ? 0x2 :
  701. (ddr_freq > 2133 ? 0x1 : 0));
  702. ddr->ddr_sdram_rcw_1 =
  703. common_dimm->rcw[0] << 28 | \
  704. common_dimm->rcw[1] << 24 | \
  705. common_dimm->rcw[2] << 20 | \
  706. common_dimm->rcw[3] << 16 | \
  707. common_dimm->rcw[4] << 12 | \
  708. common_dimm->rcw[5] << 8 | \
  709. common_dimm->rcw[6] << 4 | \
  710. common_dimm->rcw[7];
  711. ddr->ddr_sdram_rcw_2 =
  712. common_dimm->rcw[8] << 28 | \
  713. common_dimm->rcw[9] << 24 | \
  714. rc0a << 20 | \
  715. common_dimm->rcw[11] << 16 | \
  716. common_dimm->rcw[12] << 12 | \
  717. common_dimm->rcw[13] << 8 | \
  718. common_dimm->rcw[14] << 4 | \
  719. rc0f;
  720. ddr->ddr_sdram_rcw_3 =
  721. ((ddr_freq - 1260 + 19) / 20) << 8;
  722. }
  723. debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n",
  724. ddr->ddr_sdram_rcw_1);
  725. debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n",
  726. ddr->ddr_sdram_rcw_2);
  727. debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n",
  728. ddr->ddr_sdram_rcw_3);
  729. }
  730. }
  731. /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
  732. static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
  733. const memctl_options_t *popts,
  734. const common_timing_params_t *common_dimm)
  735. {
  736. unsigned int mem_en; /* DDR SDRAM interface logic enable */
  737. unsigned int sren; /* Self refresh enable (during sleep) */
  738. unsigned int ecc_en; /* ECC enable. */
  739. unsigned int rd_en; /* Registered DIMM enable */
  740. unsigned int sdram_type; /* Type of SDRAM */
  741. unsigned int dyn_pwr; /* Dynamic power management mode */
  742. unsigned int dbw; /* DRAM dta bus width */
  743. unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
  744. unsigned int ncap = 0; /* Non-concurrent auto-precharge */
  745. unsigned int threet_en; /* Enable 3T timing */
  746. unsigned int twot_en; /* Enable 2T timing */
  747. unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
  748. unsigned int x32_en = 0; /* x32 enable */
  749. unsigned int pchb8 = 0; /* precharge bit 8 enable */
  750. unsigned int hse; /* Global half strength override */
  751. unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
  752. unsigned int mem_halt = 0; /* memory controller halt */
  753. unsigned int bi = 0; /* Bypass initialization */
  754. mem_en = 1;
  755. sren = popts->self_refresh_in_sleep;
  756. if (common_dimm->all_dimms_ecc_capable) {
  757. /* Allow setting of ECC only if all DIMMs are ECC. */
  758. ecc_en = popts->ecc_mode;
  759. } else {
  760. ecc_en = 0;
  761. }
  762. if (common_dimm->all_dimms_registered &&
  763. !common_dimm->all_dimms_unbuffered) {
  764. rd_en = 1;
  765. twot_en = 0;
  766. } else {
  767. rd_en = 0;
  768. twot_en = popts->twot_en;
  769. }
  770. sdram_type = CONFIG_FSL_SDRAM_TYPE;
  771. dyn_pwr = popts->dynamic_power;
  772. dbw = popts->data_bus_width;
  773. /* 8-beat burst enable DDR-III case
  774. * we must clear it when use the on-the-fly mode,
  775. * must set it when use the 32-bits bus mode.
  776. */
  777. if ((sdram_type == SDRAM_TYPE_DDR3) ||
  778. (sdram_type == SDRAM_TYPE_DDR4)) {
  779. if (popts->burst_length == DDR_BL8)
  780. eight_be = 1;
  781. if (popts->burst_length == DDR_OTF)
  782. eight_be = 0;
  783. if (dbw == 0x1)
  784. eight_be = 1;
  785. }
  786. threet_en = popts->threet_en;
  787. ba_intlv_ctl = popts->ba_intlv_ctl;
  788. hse = popts->half_strength_driver_enable;
  789. /* set when ddr bus width < 64 */
  790. acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
  791. ddr->ddr_sdram_cfg = (0
  792. | ((mem_en & 0x1) << 31)
  793. | ((sren & 0x1) << 30)
  794. | ((ecc_en & 0x1) << 29)
  795. | ((rd_en & 0x1) << 28)
  796. | ((sdram_type & 0x7) << 24)
  797. | ((dyn_pwr & 0x1) << 21)
  798. | ((dbw & 0x3) << 19)
  799. | ((eight_be & 0x1) << 18)
  800. | ((ncap & 0x1) << 17)
  801. | ((threet_en & 0x1) << 16)
  802. | ((twot_en & 0x1) << 15)
  803. | ((ba_intlv_ctl & 0x7F) << 8)
  804. | ((x32_en & 0x1) << 5)
  805. | ((pchb8 & 0x1) << 4)
  806. | ((hse & 0x1) << 3)
  807. | ((acc_ecc_en & 0x1) << 2)
  808. | ((mem_halt & 0x1) << 1)
  809. | ((bi & 0x1) << 0)
  810. );
  811. debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
  812. }
  813. /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
  814. static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
  815. fsl_ddr_cfg_regs_t *ddr,
  816. const memctl_options_t *popts,
  817. const unsigned int unq_mrs_en)
  818. {
  819. unsigned int frc_sr = 0; /* Force self refresh */
  820. unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
  821. unsigned int odt_cfg = 0; /* ODT configuration */
  822. unsigned int num_pr; /* Number of posted refreshes */
  823. unsigned int slow = 0; /* DDR will be run less than 1250 */
  824. unsigned int x4_en = 0; /* x4 DRAM enable */
  825. unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
  826. unsigned int ap_en; /* Address Parity Enable */
  827. unsigned int d_init; /* DRAM data initialization */
  828. unsigned int rcw_en = 0; /* Register Control Word Enable */
  829. unsigned int md_en = 0; /* Mirrored DIMM Enable */
  830. unsigned int qd_en = 0; /* quad-rank DIMM Enable */
  831. int i;
  832. #ifndef CONFIG_SYS_FSL_DDR4
  833. unsigned int dll_rst_dis = 1; /* DLL reset disable */
  834. unsigned int dqs_cfg; /* DQS configuration */
  835. dqs_cfg = popts->dqs_config;
  836. #endif
  837. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  838. if (popts->cs_local_opts[i].odt_rd_cfg
  839. || popts->cs_local_opts[i].odt_wr_cfg) {
  840. odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
  841. break;
  842. }
  843. }
  844. sr_ie = popts->self_refresh_interrupt_en;
  845. num_pr = popts->package_3ds + 1;
  846. /*
  847. * 8572 manual says
  848. * {TIMING_CFG_1[PRETOACT]
  849. * + [DDR_SDRAM_CFG_2[NUM_PR]
  850. * * ({EXT_REFREC || REFREC} + 8 + 2)]}
  851. * << DDR_SDRAM_INTERVAL[REFINT]
  852. */
  853. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  854. obc_cfg = popts->otf_burst_chop_en;
  855. #else
  856. obc_cfg = 0;
  857. #endif
  858. #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
  859. slow = get_ddr_freq(ctrl_num) < 1249000000;
  860. #endif
  861. if (popts->registered_dimm_en)
  862. rcw_en = 1;
  863. /* DDR4 can have address parity for UDIMM and discrete */
  864. if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
  865. (!popts->registered_dimm_en)) {
  866. ap_en = 0;
  867. } else {
  868. ap_en = popts->ap_en;
  869. }
  870. x4_en = popts->x4_en ? 1 : 0;
  871. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  872. /* Use the DDR controller to auto initialize memory. */
  873. d_init = popts->ecc_init_using_memctl;
  874. ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
  875. debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
  876. #else
  877. /* Memory will be initialized via DMA, or not at all. */
  878. d_init = 0;
  879. #endif
  880. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  881. md_en = popts->mirrored_dimm;
  882. #endif
  883. qd_en = popts->quad_rank_present ? 1 : 0;
  884. ddr->ddr_sdram_cfg_2 = (0
  885. | ((frc_sr & 0x1) << 31)
  886. | ((sr_ie & 0x1) << 30)
  887. #ifndef CONFIG_SYS_FSL_DDR4
  888. | ((dll_rst_dis & 0x1) << 29)
  889. | ((dqs_cfg & 0x3) << 26)
  890. #endif
  891. | ((odt_cfg & 0x3) << 21)
  892. | ((num_pr & 0xf) << 12)
  893. | ((slow & 1) << 11)
  894. | (x4_en << 10)
  895. | (qd_en << 9)
  896. | (unq_mrs_en << 8)
  897. | ((obc_cfg & 0x1) << 6)
  898. | ((ap_en & 0x1) << 5)
  899. | ((d_init & 0x1) << 4)
  900. | ((rcw_en & 0x1) << 2)
  901. | ((md_en & 0x1) << 0)
  902. );
  903. debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
  904. }
  905. #ifdef CONFIG_SYS_FSL_DDR4
  906. /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
  907. static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
  908. fsl_ddr_cfg_regs_t *ddr,
  909. const memctl_options_t *popts,
  910. const common_timing_params_t *common_dimm,
  911. const unsigned int unq_mrs_en)
  912. {
  913. unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
  914. unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
  915. int i;
  916. unsigned int wr_crc = 0; /* Disable */
  917. unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
  918. unsigned int srt = 0; /* self-refresh temerature, normal range */
  919. unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
  920. unsigned int mpr = 0; /* serial */
  921. unsigned int wc_lat;
  922. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  923. if (popts->rtt_override)
  924. rtt_wr = popts->rtt_wr_override_value;
  925. else
  926. rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
  927. if (common_dimm->extended_op_srt)
  928. srt = common_dimm->extended_op_srt;
  929. esdmode2 = (0
  930. | ((wr_crc & 0x1) << 12)
  931. | ((rtt_wr & 0x3) << 9)
  932. | ((srt & 0x3) << 6)
  933. | ((cwl & 0x7) << 3));
  934. if (mclk_ps >= 1250)
  935. wc_lat = 0;
  936. else if (mclk_ps >= 833)
  937. wc_lat = 1;
  938. else
  939. wc_lat = 2;
  940. esdmode3 = (0
  941. | ((mpr & 0x3) << 11)
  942. | ((wc_lat & 0x3) << 9));
  943. ddr->ddr_sdram_mode_2 = (0
  944. | ((esdmode2 & 0xFFFF) << 16)
  945. | ((esdmode3 & 0xFFFF) << 0)
  946. );
  947. debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
  948. if (unq_mrs_en) { /* unique mode registers are supported */
  949. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  950. if (popts->rtt_override)
  951. rtt_wr = popts->rtt_wr_override_value;
  952. else
  953. rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
  954. esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
  955. esdmode2 |= (rtt_wr & 0x3) << 9;
  956. switch (i) {
  957. case 1:
  958. ddr->ddr_sdram_mode_4 = (0
  959. | ((esdmode2 & 0xFFFF) << 16)
  960. | ((esdmode3 & 0xFFFF) << 0)
  961. );
  962. break;
  963. case 2:
  964. ddr->ddr_sdram_mode_6 = (0
  965. | ((esdmode2 & 0xFFFF) << 16)
  966. | ((esdmode3 & 0xFFFF) << 0)
  967. );
  968. break;
  969. case 3:
  970. ddr->ddr_sdram_mode_8 = (0
  971. | ((esdmode2 & 0xFFFF) << 16)
  972. | ((esdmode3 & 0xFFFF) << 0)
  973. );
  974. break;
  975. }
  976. }
  977. debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
  978. ddr->ddr_sdram_mode_4);
  979. debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
  980. ddr->ddr_sdram_mode_6);
  981. debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
  982. ddr->ddr_sdram_mode_8);
  983. }
  984. }
  985. #elif defined(CONFIG_SYS_FSL_DDR3)
  986. /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
  987. static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
  988. fsl_ddr_cfg_regs_t *ddr,
  989. const memctl_options_t *popts,
  990. const common_timing_params_t *common_dimm,
  991. const unsigned int unq_mrs_en)
  992. {
  993. unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
  994. unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
  995. int i;
  996. unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
  997. unsigned int srt = 0; /* self-refresh temerature, normal range */
  998. unsigned int asr = 0; /* auto self-refresh disable */
  999. unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
  1000. unsigned int pasr = 0; /* partial array self refresh disable */
  1001. if (popts->rtt_override)
  1002. rtt_wr = popts->rtt_wr_override_value;
  1003. else
  1004. rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
  1005. if (common_dimm->extended_op_srt)
  1006. srt = common_dimm->extended_op_srt;
  1007. esdmode2 = (0
  1008. | ((rtt_wr & 0x3) << 9)
  1009. | ((srt & 0x1) << 7)
  1010. | ((asr & 0x1) << 6)
  1011. | ((cwl & 0x7) << 3)
  1012. | ((pasr & 0x7) << 0));
  1013. ddr->ddr_sdram_mode_2 = (0
  1014. | ((esdmode2 & 0xFFFF) << 16)
  1015. | ((esdmode3 & 0xFFFF) << 0)
  1016. );
  1017. debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
  1018. if (unq_mrs_en) { /* unique mode registers are supported */
  1019. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  1020. if (popts->rtt_override)
  1021. rtt_wr = popts->rtt_wr_override_value;
  1022. else
  1023. rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
  1024. esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
  1025. esdmode2 |= (rtt_wr & 0x3) << 9;
  1026. switch (i) {
  1027. case 1:
  1028. ddr->ddr_sdram_mode_4 = (0
  1029. | ((esdmode2 & 0xFFFF) << 16)
  1030. | ((esdmode3 & 0xFFFF) << 0)
  1031. );
  1032. break;
  1033. case 2:
  1034. ddr->ddr_sdram_mode_6 = (0
  1035. | ((esdmode2 & 0xFFFF) << 16)
  1036. | ((esdmode3 & 0xFFFF) << 0)
  1037. );
  1038. break;
  1039. case 3:
  1040. ddr->ddr_sdram_mode_8 = (0
  1041. | ((esdmode2 & 0xFFFF) << 16)
  1042. | ((esdmode3 & 0xFFFF) << 0)
  1043. );
  1044. break;
  1045. }
  1046. }
  1047. debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
  1048. ddr->ddr_sdram_mode_4);
  1049. debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
  1050. ddr->ddr_sdram_mode_6);
  1051. debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
  1052. ddr->ddr_sdram_mode_8);
  1053. }
  1054. }
  1055. #else /* for DDR2 and DDR1 */
  1056. /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
  1057. static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
  1058. fsl_ddr_cfg_regs_t *ddr,
  1059. const memctl_options_t *popts,
  1060. const common_timing_params_t *common_dimm,
  1061. const unsigned int unq_mrs_en)
  1062. {
  1063. unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
  1064. unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
  1065. ddr->ddr_sdram_mode_2 = (0
  1066. | ((esdmode2 & 0xFFFF) << 16)
  1067. | ((esdmode3 & 0xFFFF) << 0)
  1068. );
  1069. debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
  1070. }
  1071. #endif
  1072. #ifdef CONFIG_SYS_FSL_DDR4
  1073. /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
  1074. static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
  1075. const memctl_options_t *popts,
  1076. const common_timing_params_t *common_dimm,
  1077. const unsigned int unq_mrs_en)
  1078. {
  1079. int i;
  1080. unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
  1081. unsigned short esdmode5; /* Extended SDRAM mode 5 */
  1082. int rtt_park = 0;
  1083. bool four_cs = false;
  1084. const unsigned int mclk_ps = get_memory_clk_period_ps(0);
  1085. #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
  1086. if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
  1087. (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
  1088. (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
  1089. (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
  1090. four_cs = true;
  1091. #endif
  1092. if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
  1093. esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */
  1094. rtt_park = four_cs ? 0 : 1;
  1095. } else {
  1096. esdmode5 = 0x00000400; /* Data mask enabled */
  1097. }
  1098. /*
  1099. * For DDR3, set C/A latency if address parity is enabled.
  1100. * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is
  1101. * handled by register chip and RCW settings.
  1102. */
  1103. if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
  1104. ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
  1105. !popts->registered_dimm_en)) {
  1106. if (mclk_ps >= 935) {
  1107. /* for DDR4-1600/1866/2133 */
  1108. esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
  1109. } else if (mclk_ps >= 833) {
  1110. /* for DDR4-2400 */
  1111. esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
  1112. } else {
  1113. printf("parity: mclk_ps = %d not supported\n", mclk_ps);
  1114. }
  1115. }
  1116. ddr->ddr_sdram_mode_9 = (0
  1117. | ((esdmode4 & 0xffff) << 16)
  1118. | ((esdmode5 & 0xffff) << 0)
  1119. );
  1120. /* Normally only the first enabled CS use 0x500, others use 0x400
  1121. * But when four chip-selects are all enabled, all mode registers
  1122. * need 0x500 to park.
  1123. */
  1124. debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9);
  1125. if (unq_mrs_en) { /* unique mode registers are supported */
  1126. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  1127. if (!rtt_park &&
  1128. (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
  1129. esdmode5 |= 0x00000500; /* RTT_PARK */
  1130. rtt_park = four_cs ? 0 : 1;
  1131. } else {
  1132. esdmode5 = 0x00000400;
  1133. }
  1134. if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
  1135. ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
  1136. !popts->registered_dimm_en)) {
  1137. if (mclk_ps >= 935) {
  1138. /* for DDR4-1600/1866/2133 */
  1139. esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
  1140. } else if (mclk_ps >= 833) {
  1141. /* for DDR4-2400 */
  1142. esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
  1143. } else {
  1144. printf("parity: mclk_ps = %d not supported\n",
  1145. mclk_ps);
  1146. }
  1147. }
  1148. switch (i) {
  1149. case 1:
  1150. ddr->ddr_sdram_mode_11 = (0
  1151. | ((esdmode4 & 0xFFFF) << 16)
  1152. | ((esdmode5 & 0xFFFF) << 0)
  1153. );
  1154. break;
  1155. case 2:
  1156. ddr->ddr_sdram_mode_13 = (0
  1157. | ((esdmode4 & 0xFFFF) << 16)
  1158. | ((esdmode5 & 0xFFFF) << 0)
  1159. );
  1160. break;
  1161. case 3:
  1162. ddr->ddr_sdram_mode_15 = (0
  1163. | ((esdmode4 & 0xFFFF) << 16)
  1164. | ((esdmode5 & 0xFFFF) << 0)
  1165. );
  1166. break;
  1167. }
  1168. }
  1169. debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
  1170. ddr->ddr_sdram_mode_11);
  1171. debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
  1172. ddr->ddr_sdram_mode_13);
  1173. debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
  1174. ddr->ddr_sdram_mode_15);
  1175. }
  1176. }
  1177. /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
  1178. static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
  1179. fsl_ddr_cfg_regs_t *ddr,
  1180. const memctl_options_t *popts,
  1181. const common_timing_params_t *common_dimm,
  1182. const unsigned int unq_mrs_en)
  1183. {
  1184. int i;
  1185. unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
  1186. unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
  1187. unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
  1188. esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
  1189. if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
  1190. esdmode6 |= 1 << 6; /* Range 2 */
  1191. ddr->ddr_sdram_mode_10 = (0
  1192. | ((esdmode6 & 0xffff) << 16)
  1193. | ((esdmode7 & 0xffff) << 0)
  1194. );
  1195. debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10);
  1196. if (unq_mrs_en) { /* unique mode registers are supported */
  1197. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  1198. switch (i) {
  1199. case 1:
  1200. ddr->ddr_sdram_mode_12 = (0
  1201. | ((esdmode6 & 0xFFFF) << 16)
  1202. | ((esdmode7 & 0xFFFF) << 0)
  1203. );
  1204. break;
  1205. case 2:
  1206. ddr->ddr_sdram_mode_14 = (0
  1207. | ((esdmode6 & 0xFFFF) << 16)
  1208. | ((esdmode7 & 0xFFFF) << 0)
  1209. );
  1210. break;
  1211. case 3:
  1212. ddr->ddr_sdram_mode_16 = (0
  1213. | ((esdmode6 & 0xFFFF) << 16)
  1214. | ((esdmode7 & 0xFFFF) << 0)
  1215. );
  1216. break;
  1217. }
  1218. }
  1219. debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
  1220. ddr->ddr_sdram_mode_12);
  1221. debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
  1222. ddr->ddr_sdram_mode_14);
  1223. debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
  1224. ddr->ddr_sdram_mode_16);
  1225. }
  1226. }
  1227. #endif
  1228. /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
  1229. static void set_ddr_sdram_interval(const unsigned int ctrl_num,
  1230. fsl_ddr_cfg_regs_t *ddr,
  1231. const memctl_options_t *popts,
  1232. const common_timing_params_t *common_dimm)
  1233. {
  1234. unsigned int refint; /* Refresh interval */
  1235. unsigned int bstopre; /* Precharge interval */
  1236. refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
  1237. bstopre = popts->bstopre;
  1238. /* refint field used 0x3FFF in earlier controllers */
  1239. ddr->ddr_sdram_interval = (0
  1240. | ((refint & 0xFFFF) << 16)
  1241. | ((bstopre & 0x3FFF) << 0)
  1242. );
  1243. debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
  1244. }
  1245. #ifdef CONFIG_SYS_FSL_DDR4
  1246. /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
  1247. static void set_ddr_sdram_mode(const unsigned int ctrl_num,
  1248. fsl_ddr_cfg_regs_t *ddr,
  1249. const memctl_options_t *popts,
  1250. const common_timing_params_t *common_dimm,
  1251. unsigned int cas_latency,
  1252. unsigned int additive_latency,
  1253. const unsigned int unq_mrs_en)
  1254. {
  1255. int i;
  1256. unsigned short esdmode; /* Extended SDRAM mode */
  1257. unsigned short sdmode; /* SDRAM mode */
  1258. /* Mode Register - MR1 */
  1259. unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
  1260. unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
  1261. unsigned int rtt;
  1262. unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
  1263. unsigned int al = 0; /* Posted CAS# additive latency (AL) */
  1264. unsigned int dic = 0; /* Output driver impedance, 40ohm */
  1265. unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
  1266. 0=Disable (Test/Debug) */
  1267. /* Mode Register - MR0 */
  1268. unsigned int wr = 0; /* Write Recovery */
  1269. unsigned int dll_rst; /* DLL Reset */
  1270. unsigned int mode; /* Normal=0 or Test=1 */
  1271. unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
  1272. /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
  1273. unsigned int bt;
  1274. unsigned int bl; /* BL: Burst Length */
  1275. unsigned int wr_mclk;
  1276. /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
  1277. static const u8 wr_table[] = {
  1278. 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
  1279. /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
  1280. static const u8 cas_latency_table[] = {
  1281. 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
  1282. 9, 9, 10, 10, 11, 11};
  1283. if (popts->rtt_override)
  1284. rtt = popts->rtt_override_value;
  1285. else
  1286. rtt = popts->cs_local_opts[0].odt_rtt_norm;
  1287. if (additive_latency == (cas_latency - 1))
  1288. al = 1;
  1289. if (additive_latency == (cas_latency - 2))
  1290. al = 2;
  1291. if (popts->quad_rank_present)
  1292. dic = 1; /* output driver impedance 240/7 ohm */
  1293. /*
  1294. * The esdmode value will also be used for writing
  1295. * MR1 during write leveling for DDR3, although the
  1296. * bits specifically related to the write leveling
  1297. * scheme will be handled automatically by the DDR
  1298. * controller. so we set the wrlvl_en = 0 here.
  1299. */
  1300. esdmode = (0
  1301. | ((qoff & 0x1) << 12)
  1302. | ((tdqs_en & 0x1) << 11)
  1303. | ((rtt & 0x7) << 8)
  1304. | ((wrlvl_en & 0x1) << 7)
  1305. | ((al & 0x3) << 3)
  1306. | ((dic & 0x3) << 1) /* DIC field is split */
  1307. | ((dll_en & 0x1) << 0)
  1308. );
  1309. /*
  1310. * DLL control for precharge PD
  1311. * 0=slow exit DLL off (tXPDLL)
  1312. * 1=fast exit DLL on (tXP)
  1313. */
  1314. wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  1315. if (wr_mclk <= 24) {
  1316. wr = wr_table[wr_mclk - 10];
  1317. } else {
  1318. printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
  1319. wr_mclk);
  1320. }
  1321. dll_rst = 0; /* dll no reset */
  1322. mode = 0; /* normal mode */
  1323. /* look up table to get the cas latency bits */
  1324. if (cas_latency >= 9 && cas_latency <= 24)
  1325. caslat = cas_latency_table[cas_latency - 9];
  1326. else
  1327. printf("Error: unsupported cas latency for mode register\n");
  1328. bt = 0; /* Nibble sequential */
  1329. switch (popts->burst_length) {
  1330. case DDR_BL8:
  1331. bl = 0;
  1332. break;
  1333. case DDR_OTF:
  1334. bl = 1;
  1335. break;
  1336. case DDR_BC4:
  1337. bl = 2;
  1338. break;
  1339. default:
  1340. printf("Error: invalid burst length of %u specified. ",
  1341. popts->burst_length);
  1342. puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
  1343. bl = 1;
  1344. break;
  1345. }
  1346. sdmode = (0
  1347. | ((wr & 0x7) << 9)
  1348. | ((dll_rst & 0x1) << 8)
  1349. | ((mode & 0x1) << 7)
  1350. | (((caslat >> 1) & 0x7) << 4)
  1351. | ((bt & 0x1) << 3)
  1352. | ((caslat & 1) << 2)
  1353. | ((bl & 0x3) << 0)
  1354. );
  1355. ddr->ddr_sdram_mode = (0
  1356. | ((esdmode & 0xFFFF) << 16)
  1357. | ((sdmode & 0xFFFF) << 0)
  1358. );
  1359. debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
  1360. if (unq_mrs_en) { /* unique mode registers are supported */
  1361. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  1362. if (popts->rtt_override)
  1363. rtt = popts->rtt_override_value;
  1364. else
  1365. rtt = popts->cs_local_opts[i].odt_rtt_norm;
  1366. esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
  1367. esdmode |= (rtt & 0x7) << 8;
  1368. switch (i) {
  1369. case 1:
  1370. ddr->ddr_sdram_mode_3 = (0
  1371. | ((esdmode & 0xFFFF) << 16)
  1372. | ((sdmode & 0xFFFF) << 0)
  1373. );
  1374. break;
  1375. case 2:
  1376. ddr->ddr_sdram_mode_5 = (0
  1377. | ((esdmode & 0xFFFF) << 16)
  1378. | ((sdmode & 0xFFFF) << 0)
  1379. );
  1380. break;
  1381. case 3:
  1382. ddr->ddr_sdram_mode_7 = (0
  1383. | ((esdmode & 0xFFFF) << 16)
  1384. | ((sdmode & 0xFFFF) << 0)
  1385. );
  1386. break;
  1387. }
  1388. }
  1389. debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
  1390. ddr->ddr_sdram_mode_3);
  1391. debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
  1392. ddr->ddr_sdram_mode_5);
  1393. debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
  1394. ddr->ddr_sdram_mode_5);
  1395. }
  1396. }
  1397. #elif defined(CONFIG_SYS_FSL_DDR3)
  1398. /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
  1399. static void set_ddr_sdram_mode(const unsigned int ctrl_num,
  1400. fsl_ddr_cfg_regs_t *ddr,
  1401. const memctl_options_t *popts,
  1402. const common_timing_params_t *common_dimm,
  1403. unsigned int cas_latency,
  1404. unsigned int additive_latency,
  1405. const unsigned int unq_mrs_en)
  1406. {
  1407. int i;
  1408. unsigned short esdmode; /* Extended SDRAM mode */
  1409. unsigned short sdmode; /* SDRAM mode */
  1410. /* Mode Register - MR1 */
  1411. unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
  1412. unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
  1413. unsigned int rtt;
  1414. unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
  1415. unsigned int al = 0; /* Posted CAS# additive latency (AL) */
  1416. unsigned int dic = 0; /* Output driver impedance, 40ohm */
  1417. unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
  1418. 1=Disable (Test/Debug) */
  1419. /* Mode Register - MR0 */
  1420. unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
  1421. unsigned int wr = 0; /* Write Recovery */
  1422. unsigned int dll_rst; /* DLL Reset */
  1423. unsigned int mode; /* Normal=0 or Test=1 */
  1424. unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
  1425. /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
  1426. unsigned int bt;
  1427. unsigned int bl; /* BL: Burst Length */
  1428. unsigned int wr_mclk;
  1429. /*
  1430. * DDR_SDRAM_MODE doesn't support 9,11,13,15
  1431. * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
  1432. * for this table
  1433. */
  1434. static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
  1435. if (popts->rtt_override)
  1436. rtt = popts->rtt_override_value;
  1437. else
  1438. rtt = popts->cs_local_opts[0].odt_rtt_norm;
  1439. if (additive_latency == (cas_latency - 1))
  1440. al = 1;
  1441. if (additive_latency == (cas_latency - 2))
  1442. al = 2;
  1443. if (popts->quad_rank_present)
  1444. dic = 1; /* output driver impedance 240/7 ohm */
  1445. /*
  1446. * The esdmode value will also be used for writing
  1447. * MR1 during write leveling for DDR3, although the
  1448. * bits specifically related to the write leveling
  1449. * scheme will be handled automatically by the DDR
  1450. * controller. so we set the wrlvl_en = 0 here.
  1451. */
  1452. esdmode = (0
  1453. | ((qoff & 0x1) << 12)
  1454. | ((tdqs_en & 0x1) << 11)
  1455. | ((rtt & 0x4) << 7) /* rtt field is split */
  1456. | ((wrlvl_en & 0x1) << 7)
  1457. | ((rtt & 0x2) << 5) /* rtt field is split */
  1458. | ((dic & 0x2) << 4) /* DIC field is split */
  1459. | ((al & 0x3) << 3)
  1460. | ((rtt & 0x1) << 2) /* rtt field is split */
  1461. | ((dic & 0x1) << 1) /* DIC field is split */
  1462. | ((dll_en & 0x1) << 0)
  1463. );
  1464. /*
  1465. * DLL control for precharge PD
  1466. * 0=slow exit DLL off (tXPDLL)
  1467. * 1=fast exit DLL on (tXP)
  1468. */
  1469. dll_on = 1;
  1470. wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  1471. if (wr_mclk <= 16) {
  1472. wr = wr_table[wr_mclk - 5];
  1473. } else {
  1474. printf("Error: unsupported write recovery for mode register "
  1475. "wr_mclk = %d\n", wr_mclk);
  1476. }
  1477. dll_rst = 0; /* dll no reset */
  1478. mode = 0; /* normal mode */
  1479. /* look up table to get the cas latency bits */
  1480. if (cas_latency >= 5 && cas_latency <= 16) {
  1481. unsigned char cas_latency_table[] = {
  1482. 0x2, /* 5 clocks */
  1483. 0x4, /* 6 clocks */
  1484. 0x6, /* 7 clocks */
  1485. 0x8, /* 8 clocks */
  1486. 0xa, /* 9 clocks */
  1487. 0xc, /* 10 clocks */
  1488. 0xe, /* 11 clocks */
  1489. 0x1, /* 12 clocks */
  1490. 0x3, /* 13 clocks */
  1491. 0x5, /* 14 clocks */
  1492. 0x7, /* 15 clocks */
  1493. 0x9, /* 16 clocks */
  1494. };
  1495. caslat = cas_latency_table[cas_latency - 5];
  1496. } else {
  1497. printf("Error: unsupported cas latency for mode register\n");
  1498. }
  1499. bt = 0; /* Nibble sequential */
  1500. switch (popts->burst_length) {
  1501. case DDR_BL8:
  1502. bl = 0;
  1503. break;
  1504. case DDR_OTF:
  1505. bl = 1;
  1506. break;
  1507. case DDR_BC4:
  1508. bl = 2;
  1509. break;
  1510. default:
  1511. printf("Error: invalid burst length of %u specified. "
  1512. " Defaulting to on-the-fly BC4 or BL8 beats.\n",
  1513. popts->burst_length);
  1514. bl = 1;
  1515. break;
  1516. }
  1517. sdmode = (0
  1518. | ((dll_on & 0x1) << 12)
  1519. | ((wr & 0x7) << 9)
  1520. | ((dll_rst & 0x1) << 8)
  1521. | ((mode & 0x1) << 7)
  1522. | (((caslat >> 1) & 0x7) << 4)
  1523. | ((bt & 0x1) << 3)
  1524. | ((caslat & 1) << 2)
  1525. | ((bl & 0x3) << 0)
  1526. );
  1527. ddr->ddr_sdram_mode = (0
  1528. | ((esdmode & 0xFFFF) << 16)
  1529. | ((sdmode & 0xFFFF) << 0)
  1530. );
  1531. debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
  1532. if (unq_mrs_en) { /* unique mode registers are supported */
  1533. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  1534. if (popts->rtt_override)
  1535. rtt = popts->rtt_override_value;
  1536. else
  1537. rtt = popts->cs_local_opts[i].odt_rtt_norm;
  1538. esdmode &= 0xFDBB; /* clear bit 9,6,2 */
  1539. esdmode |= (0
  1540. | ((rtt & 0x4) << 7) /* rtt field is split */
  1541. | ((rtt & 0x2) << 5) /* rtt field is split */
  1542. | ((rtt & 0x1) << 2) /* rtt field is split */
  1543. );
  1544. switch (i) {
  1545. case 1:
  1546. ddr->ddr_sdram_mode_3 = (0
  1547. | ((esdmode & 0xFFFF) << 16)
  1548. | ((sdmode & 0xFFFF) << 0)
  1549. );
  1550. break;
  1551. case 2:
  1552. ddr->ddr_sdram_mode_5 = (0
  1553. | ((esdmode & 0xFFFF) << 16)
  1554. | ((sdmode & 0xFFFF) << 0)
  1555. );
  1556. break;
  1557. case 3:
  1558. ddr->ddr_sdram_mode_7 = (0
  1559. | ((esdmode & 0xFFFF) << 16)
  1560. | ((sdmode & 0xFFFF) << 0)
  1561. );
  1562. break;
  1563. }
  1564. }
  1565. debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
  1566. ddr->ddr_sdram_mode_3);
  1567. debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
  1568. ddr->ddr_sdram_mode_5);
  1569. debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
  1570. ddr->ddr_sdram_mode_5);
  1571. }
  1572. }
  1573. #else /* !CONFIG_SYS_FSL_DDR3 */
  1574. /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
  1575. static void set_ddr_sdram_mode(const unsigned int ctrl_num,
  1576. fsl_ddr_cfg_regs_t *ddr,
  1577. const memctl_options_t *popts,
  1578. const common_timing_params_t *common_dimm,
  1579. unsigned int cas_latency,
  1580. unsigned int additive_latency,
  1581. const unsigned int unq_mrs_en)
  1582. {
  1583. unsigned short esdmode; /* Extended SDRAM mode */
  1584. unsigned short sdmode; /* SDRAM mode */
  1585. /*
  1586. * FIXME: This ought to be pre-calculated in a
  1587. * technology-specific routine,
  1588. * e.g. compute_DDR2_mode_register(), and then the
  1589. * sdmode and esdmode passed in as part of common_dimm.
  1590. */
  1591. /* Extended Mode Register */
  1592. unsigned int mrs = 0; /* Mode Register Set */
  1593. unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
  1594. unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
  1595. unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
  1596. unsigned int ocd = 0; /* 0x0=OCD not supported,
  1597. 0x7=OCD default state */
  1598. unsigned int rtt;
  1599. unsigned int al; /* Posted CAS# additive latency (AL) */
  1600. unsigned int ods = 0; /* Output Drive Strength:
  1601. 0 = Full strength (18ohm)
  1602. 1 = Reduced strength (4ohm) */
  1603. unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
  1604. 1=Disable (Test/Debug) */
  1605. /* Mode Register (MR) */
  1606. unsigned int mr; /* Mode Register Definition */
  1607. unsigned int pd; /* Power-Down Mode */
  1608. unsigned int wr; /* Write Recovery */
  1609. unsigned int dll_res; /* DLL Reset */
  1610. unsigned int mode; /* Normal=0 or Test=1 */
  1611. unsigned int caslat = 0;/* CAS# latency */
  1612. /* BT: Burst Type (0=Sequential, 1=Interleaved) */
  1613. unsigned int bt;
  1614. unsigned int bl; /* BL: Burst Length */
  1615. dqs_en = !popts->dqs_config;
  1616. rtt = fsl_ddr_get_rtt();
  1617. al = additive_latency;
  1618. esdmode = (0
  1619. | ((mrs & 0x3) << 14)
  1620. | ((outputs & 0x1) << 12)
  1621. | ((rdqs_en & 0x1) << 11)
  1622. | ((dqs_en & 0x1) << 10)
  1623. | ((ocd & 0x7) << 7)
  1624. | ((rtt & 0x2) << 5) /* rtt field is split */
  1625. | ((al & 0x7) << 3)
  1626. | ((rtt & 0x1) << 2) /* rtt field is split */
  1627. | ((ods & 0x1) << 1)
  1628. | ((dll_en & 0x1) << 0)
  1629. );
  1630. mr = 0; /* FIXME: CHECKME */
  1631. /*
  1632. * 0 = Fast Exit (Normal)
  1633. * 1 = Slow Exit (Low Power)
  1634. */
  1635. pd = 0;
  1636. #if defined(CONFIG_SYS_FSL_DDR1)
  1637. wr = 0; /* Historical */
  1638. #elif defined(CONFIG_SYS_FSL_DDR2)
  1639. wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  1640. #endif
  1641. dll_res = 0;
  1642. mode = 0;
  1643. #if defined(CONFIG_SYS_FSL_DDR1)
  1644. if (1 <= cas_latency && cas_latency <= 4) {
  1645. unsigned char mode_caslat_table[4] = {
  1646. 0x5, /* 1.5 clocks */
  1647. 0x2, /* 2.0 clocks */
  1648. 0x6, /* 2.5 clocks */
  1649. 0x3 /* 3.0 clocks */
  1650. };
  1651. caslat = mode_caslat_table[cas_latency - 1];
  1652. } else {
  1653. printf("Warning: unknown cas_latency %d\n", cas_latency);
  1654. }
  1655. #elif defined(CONFIG_SYS_FSL_DDR2)
  1656. caslat = cas_latency;
  1657. #endif
  1658. bt = 0;
  1659. switch (popts->burst_length) {
  1660. case DDR_BL4:
  1661. bl = 2;
  1662. break;
  1663. case DDR_BL8:
  1664. bl = 3;
  1665. break;
  1666. default:
  1667. printf("Error: invalid burst length of %u specified. "
  1668. " Defaulting to 4 beats.\n",
  1669. popts->burst_length);
  1670. bl = 2;
  1671. break;
  1672. }
  1673. sdmode = (0
  1674. | ((mr & 0x3) << 14)
  1675. | ((pd & 0x1) << 12)
  1676. | ((wr & 0x7) << 9)
  1677. | ((dll_res & 0x1) << 8)
  1678. | ((mode & 0x1) << 7)
  1679. | ((caslat & 0x7) << 4)
  1680. | ((bt & 0x1) << 3)
  1681. | ((bl & 0x7) << 0)
  1682. );
  1683. ddr->ddr_sdram_mode = (0
  1684. | ((esdmode & 0xFFFF) << 16)
  1685. | ((sdmode & 0xFFFF) << 0)
  1686. );
  1687. debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
  1688. }
  1689. #endif
  1690. /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
  1691. static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
  1692. {
  1693. unsigned int init_value; /* Initialization value */
  1694. #ifdef CONFIG_MEM_INIT_VALUE
  1695. init_value = CONFIG_MEM_INIT_VALUE;
  1696. #else
  1697. init_value = 0xDEADBEEF;
  1698. #endif
  1699. ddr->ddr_data_init = init_value;
  1700. }
  1701. /*
  1702. * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
  1703. * The old controller on the 8540/60 doesn't have this register.
  1704. * Hope it's OK to set it (to 0) anyway.
  1705. */
  1706. static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
  1707. const memctl_options_t *popts)
  1708. {
  1709. unsigned int clk_adjust; /* Clock adjust */
  1710. unsigned int ss_en = 0; /* Source synchronous enable */
  1711. #if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
  1712. /* Per FSL Application Note: AN2805 */
  1713. ss_en = 1;
  1714. #endif
  1715. if (fsl_ddr_get_version(0) >= 0x40701) {
  1716. /* clk_adjust in 5-bits on T-series and LS-series */
  1717. clk_adjust = (popts->clk_adjust & 0x1F) << 22;
  1718. } else {
  1719. /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
  1720. clk_adjust = (popts->clk_adjust & 0xF) << 23;
  1721. }
  1722. ddr->ddr_sdram_clk_cntl = (0
  1723. | ((ss_en & 0x1) << 31)
  1724. | clk_adjust
  1725. );
  1726. debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
  1727. }
  1728. /* DDR Initialization Address (DDR_INIT_ADDR) */
  1729. static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
  1730. {
  1731. unsigned int init_addr = 0; /* Initialization address */
  1732. ddr->ddr_init_addr = init_addr;
  1733. }
  1734. /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
  1735. static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
  1736. {
  1737. unsigned int uia = 0; /* Use initialization address */
  1738. unsigned int init_ext_addr = 0; /* Initialization address */
  1739. ddr->ddr_init_ext_addr = (0
  1740. | ((uia & 0x1) << 31)
  1741. | (init_ext_addr & 0xF)
  1742. );
  1743. }
  1744. /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
  1745. static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
  1746. const memctl_options_t *popts)
  1747. {
  1748. unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
  1749. unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
  1750. unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
  1751. unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
  1752. unsigned int trwt_mclk = 0; /* ext_rwt */
  1753. unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
  1754. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  1755. if (popts->burst_length == DDR_BL8) {
  1756. /* We set BL/2 for fixed BL8 */
  1757. rrt = 0; /* BL/2 clocks */
  1758. wwt = 0; /* BL/2 clocks */
  1759. } else {
  1760. /* We need to set BL/2 + 2 to BC4 and OTF */
  1761. rrt = 2; /* BL/2 + 2 clocks */
  1762. wwt = 2; /* BL/2 + 2 clocks */
  1763. }
  1764. #endif
  1765. #ifdef CONFIG_SYS_FSL_DDR4
  1766. dll_lock = 2; /* tDLLK = 1024 clocks */
  1767. #elif defined(CONFIG_SYS_FSL_DDR3)
  1768. dll_lock = 1; /* tDLLK = 512 clocks from spec */
  1769. #endif
  1770. if (popts->trwt_override)
  1771. trwt_mclk = popts->trwt;
  1772. ddr->timing_cfg_4 = (0
  1773. | ((rwt & 0xf) << 28)
  1774. | ((wrt & 0xf) << 24)
  1775. | ((rrt & 0xf) << 20)
  1776. | ((wwt & 0xf) << 16)
  1777. | ((trwt_mclk & 0xc) << 12)
  1778. | (dll_lock & 0x3)
  1779. );
  1780. debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
  1781. }
  1782. /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
  1783. static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
  1784. {
  1785. unsigned int rodt_on = 0; /* Read to ODT on */
  1786. unsigned int rodt_off = 0; /* Read to ODT off */
  1787. unsigned int wodt_on = 0; /* Write to ODT on */
  1788. unsigned int wodt_off = 0; /* Write to ODT off */
  1789. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  1790. unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
  1791. ((ddr->timing_cfg_2 & 0x00040000) >> 14);
  1792. /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
  1793. if (cas_latency >= wr_lat)
  1794. rodt_on = cas_latency - wr_lat + 1;
  1795. rodt_off = 4; /* 4 clocks */
  1796. wodt_on = 1; /* 1 clocks */
  1797. wodt_off = 4; /* 4 clocks */
  1798. #endif
  1799. ddr->timing_cfg_5 = (0
  1800. | ((rodt_on & 0x1f) << 24)
  1801. | ((rodt_off & 0x7) << 20)
  1802. | ((wodt_on & 0x1f) << 12)
  1803. | ((wodt_off & 0x7) << 8)
  1804. );
  1805. debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
  1806. }
  1807. #ifdef CONFIG_SYS_FSL_DDR4
  1808. static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
  1809. {
  1810. unsigned int hs_caslat = 0;
  1811. unsigned int hs_wrlat = 0;
  1812. unsigned int hs_wrrec = 0;
  1813. unsigned int hs_clkadj = 0;
  1814. unsigned int hs_wrlvl_start = 0;
  1815. ddr->timing_cfg_6 = (0
  1816. | ((hs_caslat & 0x1f) << 24)
  1817. | ((hs_wrlat & 0x1f) << 19)
  1818. | ((hs_wrrec & 0x1f) << 12)
  1819. | ((hs_clkadj & 0x1f) << 6)
  1820. | ((hs_wrlvl_start & 0x1f) << 0)
  1821. );
  1822. debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
  1823. }
  1824. static void set_timing_cfg_7(const unsigned int ctrl_num,
  1825. fsl_ddr_cfg_regs_t *ddr,
  1826. const memctl_options_t *popts,
  1827. const common_timing_params_t *common_dimm)
  1828. {
  1829. unsigned int txpr, tcksre, tcksrx;
  1830. unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
  1831. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  1832. txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
  1833. tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
  1834. tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
  1835. if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
  1836. CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
  1837. /* for DDR4 only */
  1838. par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1;
  1839. debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);
  1840. }
  1841. cs_to_cmd = 0;
  1842. if (txpr <= 200)
  1843. cke_rst = 0;
  1844. else if (txpr <= 256)
  1845. cke_rst = 1;
  1846. else if (txpr <= 512)
  1847. cke_rst = 2;
  1848. else
  1849. cke_rst = 3;
  1850. if (tcksre <= 19)
  1851. cksre = tcksre - 5;
  1852. else
  1853. cksre = 15;
  1854. if (tcksrx <= 19)
  1855. cksrx = tcksrx - 5;
  1856. else
  1857. cksrx = 15;
  1858. ddr->timing_cfg_7 = (0
  1859. | ((cke_rst & 0x3) << 28)
  1860. | ((cksre & 0xf) << 24)
  1861. | ((cksrx & 0xf) << 20)
  1862. | ((par_lat & 0xf) << 16)
  1863. | ((cs_to_cmd & 0xf) << 4)
  1864. );
  1865. debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
  1866. }
  1867. static void set_timing_cfg_8(const unsigned int ctrl_num,
  1868. fsl_ddr_cfg_regs_t *ddr,
  1869. const memctl_options_t *popts,
  1870. const common_timing_params_t *common_dimm,
  1871. unsigned int cas_latency)
  1872. {
  1873. int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
  1874. unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
  1875. int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
  1876. int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
  1877. ((ddr->timing_cfg_2 & 0x00040000) >> 14);
  1878. rwt_bg = cas_latency + 2 + 4 - wr_lat;
  1879. if (rwt_bg < tccdl)
  1880. rwt_bg = tccdl - rwt_bg;
  1881. else
  1882. rwt_bg = 0;
  1883. wrt_bg = wr_lat + 4 + 1 - cas_latency;
  1884. if (wrt_bg < tccdl)
  1885. wrt_bg = tccdl - wrt_bg;
  1886. else
  1887. wrt_bg = 0;
  1888. if (popts->burst_length == DDR_BL8) {
  1889. rrt_bg = tccdl - 4;
  1890. wwt_bg = tccdl - 4;
  1891. } else {
  1892. rrt_bg = tccdl - 2;
  1893. wwt_bg = tccdl - 2;
  1894. }
  1895. acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
  1896. wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
  1897. if (popts->otf_burst_chop_en)
  1898. wrtord_bg += 2;
  1899. pre_all_rec = 0;
  1900. ddr->timing_cfg_8 = (0
  1901. | ((rwt_bg & 0xf) << 28)
  1902. | ((wrt_bg & 0xf) << 24)
  1903. | ((rrt_bg & 0xf) << 20)
  1904. | ((wwt_bg & 0xf) << 16)
  1905. | ((acttoact_bg & 0xf) << 12)
  1906. | ((wrtord_bg & 0xf) << 8)
  1907. | ((pre_all_rec & 0x1f) << 0)
  1908. );
  1909. debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
  1910. }
  1911. static void set_timing_cfg_9(const unsigned int ctrl_num,
  1912. fsl_ddr_cfg_regs_t *ddr,
  1913. const memctl_options_t *popts,
  1914. const common_timing_params_t *common_dimm)
  1915. {
  1916. unsigned int refrec_cid_mclk = 0;
  1917. unsigned int acttoact_cid_mclk = 0;
  1918. if (popts->package_3ds) {
  1919. refrec_cid_mclk =
  1920. picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps);
  1921. acttoact_cid_mclk = 4U; /* tRRDS_slr */
  1922. }
  1923. ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 |
  1924. (acttoact_cid_mclk & 0xf) << 8;
  1925. debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
  1926. }
  1927. /* This function needs to be called after set_ddr_sdram_cfg() is called */
  1928. static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
  1929. const dimm_params_t *dimm_params)
  1930. {
  1931. unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
  1932. int i;
  1933. for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  1934. if (dimm_params[i].n_ranks)
  1935. break;
  1936. }
  1937. if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
  1938. puts("DDR error: no DIMM found!\n");
  1939. return;
  1940. }
  1941. ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
  1942. ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
  1943. ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
  1944. ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
  1945. ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
  1946. ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
  1947. ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
  1948. ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
  1949. ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
  1950. ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
  1951. ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
  1952. ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
  1953. ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
  1954. ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
  1955. ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
  1956. /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
  1957. ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
  1958. ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
  1959. (acc_ecc_en ? 0 :
  1960. (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
  1961. dimm_params[i].dq_mapping_ors;
  1962. debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
  1963. debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
  1964. debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
  1965. debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
  1966. }
  1967. static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
  1968. const memctl_options_t *popts)
  1969. {
  1970. int rd_pre;
  1971. rd_pre = popts->quad_rank_present ? 1 : 0;
  1972. ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
  1973. /* Disable MRS on parity error for RDIMMs */
  1974. ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0;
  1975. if (popts->package_3ds) { /* only 2,4,8 are supported */
  1976. if ((popts->package_3ds + 1) & 0x1) {
  1977. printf("Error: Unsupported 3DS DIMM with %d die\n",
  1978. popts->package_3ds + 1);
  1979. } else {
  1980. ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1)
  1981. << 4;
  1982. }
  1983. }
  1984. debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
  1985. }
  1986. #endif /* CONFIG_SYS_FSL_DDR4 */
  1987. /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
  1988. static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
  1989. {
  1990. unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
  1991. /* Normal Operation Full Calibration Time (tZQoper) */
  1992. unsigned int zqoper = 0;
  1993. /* Normal Operation Short Calibration Time (tZQCS) */
  1994. unsigned int zqcs = 0;
  1995. #ifdef CONFIG_SYS_FSL_DDR4
  1996. unsigned int zqcs_init;
  1997. #endif
  1998. if (zq_en) {
  1999. #ifdef CONFIG_SYS_FSL_DDR4
  2000. zqinit = 10; /* 1024 clocks */
  2001. zqoper = 9; /* 512 clocks */
  2002. zqcs = 7; /* 128 clocks */
  2003. zqcs_init = 5; /* 1024 refresh sequences */
  2004. #else
  2005. zqinit = 9; /* 512 clocks */
  2006. zqoper = 8; /* 256 clocks */
  2007. zqcs = 6; /* 64 clocks */
  2008. #endif
  2009. }
  2010. ddr->ddr_zq_cntl = (0
  2011. | ((zq_en & 0x1) << 31)
  2012. | ((zqinit & 0xF) << 24)
  2013. | ((zqoper & 0xF) << 16)
  2014. | ((zqcs & 0xF) << 8)
  2015. #ifdef CONFIG_SYS_FSL_DDR4
  2016. | ((zqcs_init & 0xF) << 0)
  2017. #endif
  2018. );
  2019. debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
  2020. }
  2021. /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
  2022. static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
  2023. const memctl_options_t *popts)
  2024. {
  2025. /*
  2026. * First DQS pulse rising edge after margining mode
  2027. * is programmed (tWL_MRD)
  2028. */
  2029. unsigned int wrlvl_mrd = 0;
  2030. /* ODT delay after margining mode is programmed (tWL_ODTEN) */
  2031. unsigned int wrlvl_odten = 0;
  2032. /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
  2033. unsigned int wrlvl_dqsen = 0;
  2034. /* WRLVL_SMPL: Write leveling sample time */
  2035. unsigned int wrlvl_smpl = 0;
  2036. /* WRLVL_WLR: Write leveling repeition time */
  2037. unsigned int wrlvl_wlr = 0;
  2038. /* WRLVL_START: Write leveling start time */
  2039. unsigned int wrlvl_start = 0;
  2040. /* suggest enable write leveling for DDR3 due to fly-by topology */
  2041. if (wrlvl_en) {
  2042. /* tWL_MRD min = 40 nCK, we set it 64 */
  2043. wrlvl_mrd = 0x6;
  2044. /* tWL_ODTEN 128 */
  2045. wrlvl_odten = 0x7;
  2046. /* tWL_DQSEN min = 25 nCK, we set it 32 */
  2047. wrlvl_dqsen = 0x5;
  2048. /*
  2049. * Write leveling sample time at least need 6 clocks
  2050. * higher than tWLO to allow enough time for progagation
  2051. * delay and sampling the prime data bits.
  2052. */
  2053. wrlvl_smpl = 0xf;
  2054. /*
  2055. * Write leveling repetition time
  2056. * at least tWLO + 6 clocks clocks
  2057. * we set it 64
  2058. */
  2059. wrlvl_wlr = 0x6;
  2060. /*
  2061. * Write leveling start time
  2062. * The value use for the DQS_ADJUST for the first sample
  2063. * when write leveling is enabled. It probably needs to be
  2064. * overridden per platform.
  2065. */
  2066. wrlvl_start = 0x8;
  2067. /*
  2068. * Override the write leveling sample and start time
  2069. * according to specific board
  2070. */
  2071. if (popts->wrlvl_override) {
  2072. wrlvl_smpl = popts->wrlvl_sample;
  2073. wrlvl_start = popts->wrlvl_start;
  2074. }
  2075. }
  2076. ddr->ddr_wrlvl_cntl = (0
  2077. | ((wrlvl_en & 0x1) << 31)
  2078. | ((wrlvl_mrd & 0x7) << 24)
  2079. | ((wrlvl_odten & 0x7) << 20)
  2080. | ((wrlvl_dqsen & 0x7) << 16)
  2081. | ((wrlvl_smpl & 0xf) << 12)
  2082. | ((wrlvl_wlr & 0x7) << 8)
  2083. | ((wrlvl_start & 0x1F) << 0)
  2084. );
  2085. debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
  2086. ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
  2087. debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
  2088. ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
  2089. debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
  2090. }
  2091. /* DDR Self Refresh Counter (DDR_SR_CNTR) */
  2092. static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
  2093. {
  2094. /* Self Refresh Idle Threshold */
  2095. ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
  2096. }
  2097. static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
  2098. {
  2099. if (popts->addr_hash) {
  2100. ddr->ddr_eor = 0x40000000; /* address hash enable */
  2101. puts("Address hashing enabled.\n");
  2102. }
  2103. }
  2104. static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
  2105. {
  2106. ddr->ddr_cdr1 = popts->ddr_cdr1;
  2107. debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
  2108. }
  2109. static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
  2110. {
  2111. ddr->ddr_cdr2 = popts->ddr_cdr2;
  2112. debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
  2113. }
  2114. unsigned int
  2115. check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
  2116. {
  2117. unsigned int res = 0;
  2118. /*
  2119. * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
  2120. * not set at the same time.
  2121. */
  2122. if (ddr->ddr_sdram_cfg & 0x10000000
  2123. && ddr->ddr_sdram_cfg & 0x00008000) {
  2124. printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
  2125. " should not be set at the same time.\n");
  2126. res++;
  2127. }
  2128. return res;
  2129. }
  2130. unsigned int
  2131. compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
  2132. const memctl_options_t *popts,
  2133. fsl_ddr_cfg_regs_t *ddr,
  2134. const common_timing_params_t *common_dimm,
  2135. const dimm_params_t *dimm_params,
  2136. unsigned int dbw_cap_adj,
  2137. unsigned int size_only)
  2138. {
  2139. unsigned int i;
  2140. unsigned int cas_latency;
  2141. unsigned int additive_latency;
  2142. unsigned int sr_it;
  2143. unsigned int zq_en;
  2144. unsigned int wrlvl_en;
  2145. unsigned int ip_rev = 0;
  2146. unsigned int unq_mrs_en = 0;
  2147. int cs_en = 1;
  2148. memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
  2149. if (common_dimm == NULL) {
  2150. printf("Error: subset DIMM params struct null pointer\n");
  2151. return 1;
  2152. }
  2153. /*
  2154. * Process overrides first.
  2155. *
  2156. * FIXME: somehow add dereated caslat to this
  2157. */
  2158. cas_latency = (popts->cas_latency_override)
  2159. ? popts->cas_latency_override_value
  2160. : common_dimm->lowest_common_spd_caslat;
  2161. additive_latency = (popts->additive_latency_override)
  2162. ? popts->additive_latency_override_value
  2163. : common_dimm->additive_latency;
  2164. sr_it = (popts->auto_self_refresh_en)
  2165. ? popts->sr_it
  2166. : 0;
  2167. /* ZQ calibration */
  2168. zq_en = (popts->zq_en) ? 1 : 0;
  2169. /* write leveling */
  2170. wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
  2171. /* Chip Select Memory Bounds (CSn_BNDS) */
  2172. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  2173. unsigned long long ea, sa;
  2174. unsigned int cs_per_dimm
  2175. = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
  2176. unsigned int dimm_number
  2177. = i / cs_per_dimm;
  2178. unsigned long long rank_density
  2179. = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
  2180. if (dimm_params[dimm_number].n_ranks == 0) {
  2181. debug("Skipping setup of CS%u "
  2182. "because n_ranks on DIMM %u is 0\n", i, dimm_number);
  2183. continue;
  2184. }
  2185. if (popts->memctl_interleaving) {
  2186. switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
  2187. case FSL_DDR_CS0_CS1_CS2_CS3:
  2188. break;
  2189. case FSL_DDR_CS0_CS1:
  2190. case FSL_DDR_CS0_CS1_AND_CS2_CS3:
  2191. if (i > 1)
  2192. cs_en = 0;
  2193. break;
  2194. case FSL_DDR_CS2_CS3:
  2195. default:
  2196. if (i > 0)
  2197. cs_en = 0;
  2198. break;
  2199. }
  2200. sa = common_dimm->base_address;
  2201. ea = sa + common_dimm->total_mem - 1;
  2202. } else if (!popts->memctl_interleaving) {
  2203. /*
  2204. * If memory interleaving between controllers is NOT
  2205. * enabled, the starting address for each memory
  2206. * controller is distinct. However, because rank
  2207. * interleaving is enabled, the starting and ending
  2208. * addresses of the total memory on that memory
  2209. * controller needs to be programmed into its
  2210. * respective CS0_BNDS.
  2211. */
  2212. switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
  2213. case FSL_DDR_CS0_CS1_CS2_CS3:
  2214. sa = common_dimm->base_address;
  2215. ea = sa + common_dimm->total_mem - 1;
  2216. break;
  2217. case FSL_DDR_CS0_CS1_AND_CS2_CS3:
  2218. if ((i >= 2) && (dimm_number == 0)) {
  2219. sa = dimm_params[dimm_number].base_address +
  2220. 2 * rank_density;
  2221. ea = sa + 2 * rank_density - 1;
  2222. } else {
  2223. sa = dimm_params[dimm_number].base_address;
  2224. ea = sa + 2 * rank_density - 1;
  2225. }
  2226. break;
  2227. case FSL_DDR_CS0_CS1:
  2228. if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
  2229. sa = dimm_params[dimm_number].base_address;
  2230. ea = sa + rank_density - 1;
  2231. if (i != 1)
  2232. sa += (i % cs_per_dimm) * rank_density;
  2233. ea += (i % cs_per_dimm) * rank_density;
  2234. } else {
  2235. sa = 0;
  2236. ea = 0;
  2237. }
  2238. if (i == 0)
  2239. ea += rank_density;
  2240. break;
  2241. case FSL_DDR_CS2_CS3:
  2242. if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
  2243. sa = dimm_params[dimm_number].base_address;
  2244. ea = sa + rank_density - 1;
  2245. if (i != 3)
  2246. sa += (i % cs_per_dimm) * rank_density;
  2247. ea += (i % cs_per_dimm) * rank_density;
  2248. } else {
  2249. sa = 0;
  2250. ea = 0;
  2251. }
  2252. if (i == 2)
  2253. ea += (rank_density >> dbw_cap_adj);
  2254. break;
  2255. default: /* No bank(chip-select) interleaving */
  2256. sa = dimm_params[dimm_number].base_address;
  2257. ea = sa + rank_density - 1;
  2258. if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
  2259. sa += (i % cs_per_dimm) * rank_density;
  2260. ea += (i % cs_per_dimm) * rank_density;
  2261. } else {
  2262. sa = 0;
  2263. ea = 0;
  2264. }
  2265. break;
  2266. }
  2267. }
  2268. sa >>= 24;
  2269. ea >>= 24;
  2270. if (cs_en) {
  2271. ddr->cs[i].bnds = (0
  2272. | ((sa & 0xffff) << 16) /* starting address */
  2273. | ((ea & 0xffff) << 0) /* ending address */
  2274. );
  2275. } else {
  2276. /* setting bnds to 0xffffffff for inactive CS */
  2277. ddr->cs[i].bnds = 0xffffffff;
  2278. }
  2279. debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
  2280. set_csn_config(dimm_number, i, ddr, popts, dimm_params);
  2281. set_csn_config_2(i, ddr);
  2282. }
  2283. /*
  2284. * In the case we only need to compute the ddr sdram size, we only need
  2285. * to set csn registers, so return from here.
  2286. */
  2287. if (size_only)
  2288. return 0;
  2289. set_ddr_eor(ddr, popts);
  2290. #if !defined(CONFIG_SYS_FSL_DDR1)
  2291. set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
  2292. #endif
  2293. set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
  2294. additive_latency);
  2295. set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
  2296. set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
  2297. cas_latency, additive_latency);
  2298. set_ddr_cdr1(ddr, popts);
  2299. set_ddr_cdr2(ddr, popts);
  2300. set_ddr_sdram_cfg(ddr, popts, common_dimm);
  2301. ip_rev = fsl_ddr_get_version(ctrl_num);
  2302. if (ip_rev > 0x40400)
  2303. unq_mrs_en = 1;
  2304. if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
  2305. ddr->debug[18] = popts->cswl_override;
  2306. set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
  2307. set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
  2308. cas_latency, additive_latency, unq_mrs_en);
  2309. set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
  2310. #ifdef CONFIG_SYS_FSL_DDR4
  2311. set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
  2312. set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
  2313. #endif
  2314. set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm);
  2315. set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
  2316. set_ddr_data_init(ddr);
  2317. set_ddr_sdram_clk_cntl(ddr, popts);
  2318. set_ddr_init_addr(ddr);
  2319. set_ddr_init_ext_addr(ddr);
  2320. set_timing_cfg_4(ddr, popts);
  2321. set_timing_cfg_5(ddr, cas_latency);
  2322. #ifdef CONFIG_SYS_FSL_DDR4
  2323. set_ddr_sdram_cfg_3(ddr, popts);
  2324. set_timing_cfg_6(ddr);
  2325. set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm);
  2326. set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
  2327. set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm);
  2328. set_ddr_dq_mapping(ddr, dimm_params);
  2329. #endif
  2330. set_ddr_zq_cntl(ddr, zq_en);
  2331. set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
  2332. set_ddr_sr_cntr(ddr, sr_it);
  2333. #ifdef CONFIG_SYS_FSL_DDR_EMU
  2334. /* disble DDR training for emulator */
  2335. ddr->debug[2] = 0x00000400;
  2336. ddr->debug[4] = 0xff800800;
  2337. ddr->debug[5] = 0x08000800;
  2338. ddr->debug[6] = 0x08000800;
  2339. ddr->debug[7] = 0x08000800;
  2340. ddr->debug[8] = 0x08000800;
  2341. #endif
  2342. #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
  2343. if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
  2344. ddr->debug[2] |= 0x00000200; /* set bit 22 */
  2345. #endif
  2346. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  2347. if (popts->cpo_sample)
  2348. ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
  2349. popts->cpo_sample;
  2350. #endif
  2351. return check_fsl_memctl_config_regs(ddr);
  2352. }
  2353. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  2354. /*
  2355. * This additional workaround of A009942 checks the condition to determine if
  2356. * the CPO value set by the existing A009942 workaround needs to be updated.
  2357. * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
  2358. * expected optimal value, the optimal value is highly board dependent.
  2359. */
  2360. void erratum_a009942_check_cpo(void)
  2361. {
  2362. struct ccsr_ddr __iomem *ddr =
  2363. (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
  2364. u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
  2365. u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
  2366. u32 cpo_max = cpo_min;
  2367. u32 sdram_cfg, i, tmp, lanes, ddr_type;
  2368. bool update_cpo = false, has_ecc = false;
  2369. sdram_cfg = ddr_in32(&ddr->sdram_cfg);
  2370. if (sdram_cfg & SDRAM_CFG_32_BE)
  2371. lanes = 4;
  2372. else if (sdram_cfg & SDRAM_CFG_16_BE)
  2373. lanes = 2;
  2374. else
  2375. lanes = 8;
  2376. if (sdram_cfg & SDRAM_CFG_ECC_EN)
  2377. has_ecc = true;
  2378. /* determine the maximum and minimum CPO values */
  2379. for (i = 9; i < 9 + lanes / 2; i++) {
  2380. cpo = ddr_in32(&ddr->debug[i]);
  2381. cpo_e = cpo >> 24;
  2382. cpo_o = (cpo >> 8) & 0xff;
  2383. tmp = min(cpo_e, cpo_o);
  2384. if (tmp < cpo_min)
  2385. cpo_min = tmp;
  2386. tmp = max(cpo_e, cpo_o);
  2387. if (tmp > cpo_max)
  2388. cpo_max = tmp;
  2389. }
  2390. if (has_ecc) {
  2391. cpo = ddr_in32(&ddr->debug[13]);
  2392. cpo = cpo >> 24;
  2393. if (cpo < cpo_min)
  2394. cpo_min = cpo;
  2395. if (cpo > cpo_max)
  2396. cpo_max = cpo;
  2397. }
  2398. cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
  2399. cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
  2400. debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
  2401. cpo_target);
  2402. debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
  2403. ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
  2404. SDRAM_CFG_SDRAM_TYPE_SHIFT;
  2405. if (ddr_type == SDRAM_TYPE_DDR4)
  2406. update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
  2407. else if (ddr_type == SDRAM_TYPE_DDR3)
  2408. update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
  2409. if (update_cpo) {
  2410. printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
  2411. printf("in <board>/ddr.c to optimize cpo\n");
  2412. }
  2413. }
  2414. #endif