p3041ds.dts 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P3041DS Device Tree Source
  4. *
  5. * Copyright 2010 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019-2020 NXP
  7. */
  8. /include/ "p3041.dtsi"
  9. / {
  10. model = "fsl,P3041DS";
  11. compatible = "fsl,P3041DS";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. aliases{
  16. phy_rgmii_0 = &phy_rgmii_0;
  17. phy_rgmii_1 = &phy_rgmii_1;
  18. phy_sgmii_1c = &phy_sgmii_1c;
  19. phy_sgmii_1d = &phy_sgmii_1d;
  20. phy_sgmii_1e = &phy_sgmii_1e;
  21. phy_sgmii_1f = &phy_sgmii_1f;
  22. phy_xgmii_1 = &phy_xgmii_1;
  23. phy_xgmii_2 = &phy_xgmii_2;
  24. emi1_rgmii = &hydra_mdio_rgmii;
  25. emi1_sgmii = &hydra_mdio_sgmii;
  26. emi2_xgmii = &hydra_mdio_xgmii;
  27. };
  28. soc: soc@ffe000000 {
  29. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  30. reg = <0xf 0xfe000000 0 0x00001000>;
  31. fman@400000{
  32. ethernet@e0000 {
  33. phy-handle = <&phy_sgmii_1c>;
  34. phy-connection-type = "sgmii";
  35. };
  36. ethernet@e2000 {
  37. phy-handle = <&phy_sgmii_1d>;
  38. phy-connection-type = "sgmii";
  39. };
  40. ethernet@e4000 {
  41. phy-handle = <&phy_sgmii_1e>;
  42. phy-connection-type = "sgmii";
  43. };
  44. ethernet@e6000 {
  45. phy-handle = <&phy_sgmii_1f>;
  46. phy-connection-type = "sgmii";
  47. };
  48. ethernet@e8000 {
  49. phy-handle = <&phy_rgmii_1>;
  50. phy-connection-type = "rgmii";
  51. };
  52. ethernet@f0000 {
  53. phy-handle = <&phy_xgmii_1>;
  54. phy-connection-type = "xgmii";
  55. };
  56. hydra_mdio_xgmii: mdio@f1000 {
  57. status = "disabled";
  58. phy_xgmii_1: ethernet-phy@4 {
  59. compatible = "ethernet-phy-ieee802.3-c45";
  60. reg = <0x4>;
  61. };
  62. phy_xgmii_2: ethernet-phy@0 {
  63. compatible = "ethernet-phy-ieee802.3-c45";
  64. reg = <0x0>;
  65. };
  66. };
  67. };
  68. };
  69. lbc: localbus@ffe124000 {
  70. reg = <0xf 0xfe124000 0 0x1000>;
  71. ranges = <0 0 0xf 0xe8000000 0x08000000
  72. 2 0 0xf 0xffa00000 0x00040000
  73. 3 0 0xf 0xffdf0000 0x00008000>;
  74. board-control@3,0 {
  75. #address-cells = <1>;
  76. #size-cells = <1>;
  77. compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
  78. reg = <3 0 0x30>;
  79. ranges = <0 3 0 0x30>;
  80. mdio-mux-emi1 {
  81. #address-cells = <1>;
  82. #size-cells = <0>;
  83. compatible = "mdio-mux-mmioreg", "mdio-mux";
  84. mdio-parent-bus = <&mdio0>;
  85. reg = <9 1>;
  86. mux-mask = <0x78>;
  87. hydra_mdio_rgmii: rgmii-mdio@8 {
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. reg = <8>;
  91. status = "disabled";
  92. phy_rgmii_0: ethernet-phy@0 {
  93. reg = <0x0>;
  94. };
  95. phy_rgmii_1: ethernet-phy@1 {
  96. reg = <0x1>;
  97. };
  98. };
  99. hydra_mdio_sgmii: sgmii-mdio@28 {
  100. #address-cells = <1>;
  101. #size-cells = <0>;
  102. reg = <0x28>;
  103. status = "disabled";
  104. phy_sgmii_1c: ethernet-phy@1c {
  105. reg = <0x1c>;
  106. };
  107. phy_sgmii_1d: ethernet-phy@1d {
  108. reg = <0x1d>;
  109. };
  110. phy_sgmii_1e: ethernet-phy@1e {
  111. reg = <0x1e>;
  112. };
  113. phy_sgmii_1f: ethernet-phy@1f {
  114. reg = <0x1f>;
  115. };
  116. };
  117. };
  118. };
  119. };
  120. };
  121. /include/ "p3041si-post.dtsi"