p2041rdb.dts 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P2041RDB Device Tree Source
  4. *
  5. * Copyright 2011 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019-2020 NXP
  7. */
  8. /include/ "p2041.dtsi"
  9. / {
  10. model = "fsl,P2041RDB";
  11. compatible = "fsl,P2041RDB";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. aliases {
  16. phy_rgmii_0 = &phy_rgmii_0;
  17. phy_rgmii_1 = &phy_rgmii_1;
  18. phy_sgmii_2 = &phy_sgmii_2;
  19. phy_sgmii_3 = &phy_sgmii_3;
  20. phy_sgmii_4 = &phy_sgmii_4;
  21. phy_sgmii_1c = &phy_sgmii_1c;
  22. phy_sgmii_1d = &phy_sgmii_1d;
  23. phy_sgmii_1e = &phy_sgmii_1e;
  24. phy_sgmii_1f = &phy_sgmii_1f;
  25. phy_xgmii_2 = &phy_xgmii_2;
  26. };
  27. soc: soc@ffe000000 {
  28. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  29. reg = <0xf 0xfe000000 0 0x00001000>;
  30. fman@400000 {
  31. ethernet@e0000 {
  32. phy-handle = <&phy_sgmii_2>;
  33. phy-connection-type = "sgmii";
  34. };
  35. mdio@e1120 {
  36. phy_rgmii_0: ethernet-phy@0 {
  37. reg = <0x0>;
  38. };
  39. phy_rgmii_1: ethernet-phy@1 {
  40. reg = <0x1>;
  41. };
  42. phy_sgmii_2: ethernet-phy@2 {
  43. reg = <0x2>;
  44. };
  45. phy_sgmii_3: ethernet-phy@3 {
  46. reg = <0x3>;
  47. };
  48. phy_sgmii_4: ethernet-phy@4 {
  49. reg = <0x4>;
  50. };
  51. phy_sgmii_1c: ethernet-phy@1c {
  52. reg = <0x1c>;
  53. };
  54. phy_sgmii_1d: ethernet-phy@1d {
  55. reg = <0x1d>;
  56. };
  57. phy_sgmii_1e: ethernet-phy@1e {
  58. reg = <0x1e>;
  59. };
  60. phy_sgmii_1f: ethernet-phy@1f {
  61. reg = <0x1f>;
  62. };
  63. };
  64. ethernet@e2000 {
  65. phy-handle = <&phy_sgmii_3>;
  66. phy-connection-type = "sgmii";
  67. };
  68. ethernet@e4000 {
  69. phy-handle = <&phy_sgmii_4>;
  70. phy-connection-type = "sgmii";
  71. };
  72. ethernet@e6000 {
  73. phy-handle = <&phy_rgmii_1>;
  74. phy-connection-type = "rgmii";
  75. };
  76. ethernet@e8000 {
  77. phy-handle = <&phy_rgmii_0>;
  78. phy-connection-type = "rgmii";
  79. };
  80. ethernet@f0000 {
  81. phy-handle = <&phy_xgmii_2>;
  82. phy-connection-type = "xgmii";
  83. };
  84. mdio@f1000 {
  85. phy_xgmii_2: ethernet-phy@0 {
  86. compatible = "ethernet-phy-ieee802.3-c45";
  87. reg = <0x0>;
  88. };
  89. };
  90. };
  91. };
  92. };
  93. /include/ "p2041si-post.dtsi"