cpu_init.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2003 Motorola Inc.
  6. * Modified by Xianghua Xiao, X.Xiao@motorola.com
  7. *
  8. * (C) Copyright 2000
  9. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10. */
  11. #include <common.h>
  12. #include <env.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <watchdog.h>
  16. #include <asm/processor.h>
  17. #include <ioports.h>
  18. #include <sata.h>
  19. #include <fm_eth.h>
  20. #include <asm/io.h>
  21. #include <asm/cache.h>
  22. #include <asm/mmu.h>
  23. #include <fsl_errata.h>
  24. #include <asm/fsl_law.h>
  25. #include <asm/fsl_serdes.h>
  26. #include <asm/fsl_srio.h>
  27. #ifdef CONFIG_FSL_CORENET
  28. #include <asm/fsl_portals.h>
  29. #include <asm/fsl_liodn.h>
  30. #include <fsl_qbman.h>
  31. #endif
  32. #include <fsl_usb.h>
  33. #include <hwconfig.h>
  34. #include <linux/compiler.h>
  35. #include <linux/delay.h>
  36. #include "mp.h"
  37. #ifdef CONFIG_CHAIN_OF_TRUST
  38. #include <fsl_validate.h>
  39. #endif
  40. #ifdef CONFIG_FSL_CAAM
  41. #include <fsl_sec.h>
  42. #endif
  43. #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
  44. #include <asm/fsl_pamu.h>
  45. #include <fsl_secboot_err.h>
  46. #endif
  47. #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
  48. #include <nand.h>
  49. #include <errno.h>
  50. #endif
  51. #ifndef CONFIG_ARCH_QEMU_E500
  52. #include <fsl_ddr.h>
  53. #endif
  54. #include "../../../../drivers/ata/fsl_sata.h"
  55. #ifdef CONFIG_U_QE
  56. #include <fsl_qe.h>
  57. #endif
  58. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  59. /*
  60. * For deriving usb clock from 100MHz sysclk, reference divisor is set
  61. * to a value of 5, which gives an intermediate value 20(100/5). The
  62. * multiplication factor integer is set to 24, which when multiplied to
  63. * above intermediate value provides clock for usb ip.
  64. */
  65. void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
  66. {
  67. sys_info_t sysinfo;
  68. get_sys_info(&sysinfo);
  69. if (sysinfo.diff_sysclk == 1) {
  70. clrbits_be32(&usb_phy->pllprg[1],
  71. CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
  72. setbits_be32(&usb_phy->pllprg[1],
  73. CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
  74. CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
  75. CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
  76. }
  77. }
  78. #endif
  79. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  80. void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
  81. {
  82. #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  83. u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
  84. /* Increase Disconnect Threshold by 50mV */
  85. xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  86. INC_DCNT_THRESHOLD_50MV;
  87. /* Enable programming of USB High speed Disconnect threshold */
  88. xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  89. out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
  90. xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
  91. /* Increase Disconnect Threshold by 50mV */
  92. xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  93. INC_DCNT_THRESHOLD_50MV;
  94. /* Enable programming of USB High speed Disconnect threshold */
  95. xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  96. out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
  97. #else
  98. u32 temp = 0;
  99. u32 status = in_be32(&usb_phy->status1);
  100. u32 squelch_prog_rd_0_2 =
  101. (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
  102. & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  103. u32 squelch_prog_rd_3_5 =
  104. (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
  105. & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  106. setbits_be32(&usb_phy->config1,
  107. CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
  108. setbits_be32(&usb_phy->config2,
  109. CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
  110. temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
  111. out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  112. temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
  113. out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  114. #endif
  115. }
  116. #endif
  117. #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
  118. extern qe_iop_conf_t qe_iop_conf_tab[];
  119. extern void qe_config_iopin(u8 port, u8 pin, int dir,
  120. int open_drain, int assign);
  121. extern void qe_init(uint qe_base);
  122. extern void qe_reset(void);
  123. static void config_qe_ioports(void)
  124. {
  125. u8 port, pin;
  126. int dir, open_drain, assign;
  127. int i;
  128. for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  129. port = qe_iop_conf_tab[i].port;
  130. pin = qe_iop_conf_tab[i].pin;
  131. dir = qe_iop_conf_tab[i].dir;
  132. open_drain = qe_iop_conf_tab[i].open_drain;
  133. assign = qe_iop_conf_tab[i].assign;
  134. qe_config_iopin(port, pin, dir, open_drain, assign);
  135. }
  136. }
  137. #endif
  138. #ifdef CONFIG_CPM2
  139. void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  140. {
  141. int portnum;
  142. for (portnum = 0; portnum < 4; portnum++) {
  143. uint pmsk = 0,
  144. ppar = 0,
  145. psor = 0,
  146. pdir = 0,
  147. podr = 0,
  148. pdat = 0;
  149. iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  150. iop_conf_t *eiopc = iopc + 32;
  151. uint msk = 1;
  152. /*
  153. * NOTE:
  154. * index 0 refers to pin 31,
  155. * index 31 refers to pin 0
  156. */
  157. while (iopc < eiopc) {
  158. if (iopc->conf) {
  159. pmsk |= msk;
  160. if (iopc->ppar)
  161. ppar |= msk;
  162. if (iopc->psor)
  163. psor |= msk;
  164. if (iopc->pdir)
  165. pdir |= msk;
  166. if (iopc->podr)
  167. podr |= msk;
  168. if (iopc->pdat)
  169. pdat |= msk;
  170. }
  171. msk <<= 1;
  172. iopc++;
  173. }
  174. if (pmsk != 0) {
  175. volatile ioport_t *iop = ioport_addr (cpm, portnum);
  176. uint tpmsk = ~pmsk;
  177. /*
  178. * the (somewhat confused) paragraph at the
  179. * bottom of page 35-5 warns that there might
  180. * be "unknown behaviour" when programming
  181. * PSORx and PDIRx, if PPARx = 1, so I
  182. * decided this meant I had to disable the
  183. * dedicated function first, and enable it
  184. * last.
  185. */
  186. iop->ppar &= tpmsk;
  187. iop->psor = (iop->psor & tpmsk) | psor;
  188. iop->podr = (iop->podr & tpmsk) | podr;
  189. iop->pdat = (iop->pdat & tpmsk) | pdat;
  190. iop->pdir = (iop->pdir & tpmsk) | pdir;
  191. iop->ppar |= ppar;
  192. }
  193. }
  194. }
  195. #endif
  196. #ifdef CONFIG_SYS_FSL_CPC
  197. #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
  198. void disable_cpc_sram(void)
  199. {
  200. int i;
  201. cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  202. for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  203. if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
  204. /* find and disable LAW of SRAM */
  205. struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
  206. if (law.index == -1) {
  207. printf("\nFatal error happened\n");
  208. return;
  209. }
  210. disable_law(law.index);
  211. clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
  212. out_be32(&cpc->cpccsr0, 0);
  213. out_be32(&cpc->cpcsrcr0, 0);
  214. }
  215. }
  216. }
  217. #endif
  218. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  219. #ifdef CONFIG_POST
  220. #error POST memory test cannot be enabled with TDM
  221. #endif
  222. static void enable_tdm_law(void)
  223. {
  224. int ret;
  225. char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  226. int tdm_hwconfig_enabled = 0;
  227. /*
  228. * Extract hwconfig from environment since environment
  229. * is not setup properly yet. Search for tdm entry in
  230. * hwconfig.
  231. */
  232. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  233. if (ret > 0) {
  234. tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
  235. /* If tdm is defined in hwconfig, set law for tdm workaround */
  236. if (tdm_hwconfig_enabled)
  237. set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
  238. LAW_TRGT_IF_CCSR);
  239. }
  240. }
  241. #endif
  242. void enable_cpc(void)
  243. {
  244. int i;
  245. int ret;
  246. u32 size = 0;
  247. u32 cpccfg0;
  248. char buffer[HWCONFIG_BUFFER_SIZE];
  249. char cpc_subarg[16];
  250. bool have_hwconfig = false;
  251. int cpc_args = 0;
  252. cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  253. /* Extract hwconfig from environment */
  254. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  255. if (ret > 0) {
  256. /*
  257. * If "en_cpc" is not defined in hwconfig then by default all
  258. * cpcs are enable. If this config is defined then individual
  259. * cpcs which have to be enabled should also be defined.
  260. * e.g en_cpc:cpc1,cpc2;
  261. */
  262. if (hwconfig_f("en_cpc", buffer))
  263. have_hwconfig = true;
  264. }
  265. for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  266. if (have_hwconfig) {
  267. sprintf(cpc_subarg, "cpc%u", i + 1);
  268. cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
  269. if (cpc_args == 0)
  270. continue;
  271. }
  272. cpccfg0 = in_be32(&cpc->cpccfg0);
  273. size += CPC_CFG0_SZ_K(cpccfg0);
  274. #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
  275. setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
  276. #endif
  277. #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
  278. setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
  279. #endif
  280. #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
  281. setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
  282. #endif
  283. #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
  284. if (has_erratum_a006379()) {
  285. setbits_be32(&cpc->cpchdbcr0,
  286. CPC_HDBCR0_SPLRU_LEVEL_EN);
  287. }
  288. #endif
  289. out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
  290. /* Read back to sync write */
  291. in_be32(&cpc->cpccsr0);
  292. }
  293. puts("Corenet Platform Cache: ");
  294. print_size(size * 1024, " enabled\n");
  295. }
  296. static void invalidate_cpc(void)
  297. {
  298. int i;
  299. cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  300. for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  301. /* skip CPC when it used as all SRAM */
  302. if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
  303. continue;
  304. /* Flash invalidate the CPC and clear all the locks */
  305. out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
  306. while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
  307. ;
  308. }
  309. }
  310. #else
  311. #define enable_cpc()
  312. #define invalidate_cpc()
  313. #define disable_cpc_sram()
  314. #endif /* CONFIG_SYS_FSL_CPC */
  315. /*
  316. * Breathe some life into the CPU...
  317. *
  318. * Set up the memory map
  319. * initialize a bunch of registers
  320. */
  321. #ifdef CONFIG_FSL_CORENET
  322. static void corenet_tb_init(void)
  323. {
  324. volatile ccsr_rcpm_t *rcpm =
  325. (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  326. volatile ccsr_pic_t *pic =
  327. (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  328. u32 whoami = in_be32(&pic->whoami);
  329. /* Enable the timebase register for this core */
  330. out_be32(&rcpm->ctbenrl, (1 << whoami));
  331. }
  332. #endif
  333. #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
  334. void fsl_erratum_a007212_workaround(void)
  335. {
  336. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  337. u32 ddr_pll_ratio;
  338. u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
  339. u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
  340. u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
  341. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  342. u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
  343. u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
  344. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  345. u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
  346. u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
  347. #endif
  348. #endif
  349. /*
  350. * Even this workaround applies to selected version of SoCs, it is
  351. * safe to apply to all versions, with the limitation of odd ratios.
  352. * If RCW has disabled DDR PLL, we have to apply this workaround,
  353. * otherwise DDR will not work.
  354. */
  355. ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
  356. FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
  357. FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  358. /* check if RCW sets ratio to 0, required by this workaround */
  359. if (ddr_pll_ratio != 0)
  360. return;
  361. ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
  362. FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
  363. FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  364. /* check if reserved bits have the desired ratio */
  365. if (ddr_pll_ratio == 0) {
  366. printf("Error: Unknown DDR PLL ratio!\n");
  367. return;
  368. }
  369. ddr_pll_ratio >>= 1;
  370. setbits_be32(plldadcr1, 0x02000001);
  371. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  372. setbits_be32(plldadcr2, 0x02000001);
  373. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  374. setbits_be32(plldadcr3, 0x02000001);
  375. #endif
  376. #endif
  377. setbits_be32(dpdovrcr4, 0xe0000000);
  378. out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
  379. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  380. out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
  381. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  382. out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
  383. #endif
  384. #endif
  385. udelay(100);
  386. clrbits_be32(plldadcr1, 0x02000001);
  387. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  388. clrbits_be32(plldadcr2, 0x02000001);
  389. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  390. clrbits_be32(plldadcr3, 0x02000001);
  391. #endif
  392. #endif
  393. clrbits_be32(dpdovrcr4, 0xe0000000);
  394. }
  395. #endif
  396. ulong cpu_init_f(void)
  397. {
  398. extern void m8560_cpm_reset (void);
  399. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  400. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  401. #endif
  402. #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
  403. struct law_entry law;
  404. #endif
  405. #ifdef CONFIG_ARCH_MPC8548
  406. ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  407. uint svr = get_svr();
  408. /*
  409. * CPU2 errata workaround: A core hang possible while executing
  410. * a msync instruction and a snoopable transaction from an I/O
  411. * master tagged to make quick forward progress is present.
  412. * Fixed in silicon rev 2.1.
  413. */
  414. if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
  415. out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
  416. #endif
  417. disable_tlb(14);
  418. disable_tlb(15);
  419. #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
  420. /* Disable the LAW created for NOR flash by the PBI commands */
  421. law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
  422. if (law.index != -1)
  423. disable_law(law.index);
  424. #if defined(CONFIG_SYS_CPC_REINIT_F)
  425. disable_cpc_sram();
  426. #endif
  427. #endif
  428. #ifdef CONFIG_CPM2
  429. config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
  430. #endif
  431. init_early_memctl_regs();
  432. #if defined(CONFIG_CPM2)
  433. m8560_cpm_reset();
  434. #endif
  435. #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
  436. /* Config QE ioports */
  437. config_qe_ioports();
  438. #endif
  439. #if defined(CONFIG_FSL_DMA)
  440. dma_init();
  441. #endif
  442. #ifdef CONFIG_FSL_CORENET
  443. corenet_tb_init();
  444. #endif
  445. init_used_tlb_cams();
  446. /* Invalidate the CPC before DDR gets enabled */
  447. invalidate_cpc();
  448. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  449. /* set DCSRCR so that DCSR space is 1G */
  450. setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
  451. in_be32(&gur->dcsrcr);
  452. #endif
  453. #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
  454. fsl_erratum_a007212_workaround();
  455. #endif
  456. return 0;
  457. }
  458. /* Implement a dummy function for those platforms w/o SERDES */
  459. static void __fsl_serdes__init(void)
  460. {
  461. return ;
  462. }
  463. __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
  464. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  465. int enable_cluster_l2(void)
  466. {
  467. int i = 0;
  468. u32 cluster, svr = get_svr();
  469. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  470. struct ccsr_cluster_l2 __iomem *l2cache;
  471. /* only the L2 of first cluster should be enabled as expected on T4080,
  472. * but there is no EOC in the first cluster as HW sake, so return here
  473. * to skip enabling L2 cache of the 2nd cluster.
  474. */
  475. if (SVR_SOC_VER(svr) == SVR_T4080)
  476. return 0;
  477. cluster = in_be32(&gur->tp_cluster[i].lower);
  478. if (cluster & TP_CLUSTER_EOC)
  479. return 0;
  480. /* The first cache has already been set up, so skip it */
  481. i++;
  482. /* Look through the remaining clusters, and set up their caches */
  483. do {
  484. int j, cluster_valid = 0;
  485. l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
  486. cluster = in_be32(&gur->tp_cluster[i].lower);
  487. /* check that at least one core/accel is enabled in cluster */
  488. for (j = 0; j < 4; j++) {
  489. u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
  490. u32 type = in_be32(&gur->tp_ityp[idx]);
  491. if ((type & TP_ITYP_AV) &&
  492. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
  493. cluster_valid = 1;
  494. }
  495. if (cluster_valid) {
  496. /* set stash ID to (cluster) * 2 + 32 + 1 */
  497. clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
  498. printf("enable l2 for cluster %d %p\n", i, l2cache);
  499. out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
  500. while ((in_be32(&l2cache->l2csr0)
  501. & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
  502. ;
  503. out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
  504. }
  505. i++;
  506. } while (!(cluster & TP_CLUSTER_EOC));
  507. return 0;
  508. }
  509. #endif
  510. /*
  511. * Initialize L2 as cache.
  512. */
  513. int l2cache_init(void)
  514. {
  515. __maybe_unused u32 svr = get_svr();
  516. #ifdef CONFIG_L2_CACHE
  517. ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
  518. #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  519. struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
  520. #endif
  521. puts ("L2: ");
  522. #if defined(CONFIG_L2_CACHE)
  523. volatile uint cache_ctl;
  524. uint ver;
  525. u32 l2siz_field;
  526. ver = SVR_SOC_VER(svr);
  527. asm("msync;isync");
  528. cache_ctl = l2cache->l2ctl;
  529. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
  530. if (cache_ctl & MPC85xx_L2CTL_L2E) {
  531. /* Clear L2 SRAM memory-mapped base address */
  532. out_be32(&l2cache->l2srbar0, 0x0);
  533. out_be32(&l2cache->l2srbar1, 0x0);
  534. /* set MBECCDIS=0, SBECCDIS=0 */
  535. clrbits_be32(&l2cache->l2errdis,
  536. (MPC85xx_L2ERRDIS_MBECC |
  537. MPC85xx_L2ERRDIS_SBECC));
  538. /* set L2E=0, L2SRAM=0 */
  539. clrbits_be32(&l2cache->l2ctl,
  540. (MPC85xx_L2CTL_L2E |
  541. MPC85xx_L2CTL_L2SRAM_ENTIRE));
  542. }
  543. #endif
  544. l2siz_field = (cache_ctl >> 28) & 0x3;
  545. switch (l2siz_field) {
  546. case 0x0:
  547. printf(" unknown size (0x%08x)\n", cache_ctl);
  548. return -1;
  549. break;
  550. case 0x1:
  551. if (ver == SVR_8540 || ver == SVR_8560 ||
  552. ver == SVR_8541 || ver == SVR_8555) {
  553. puts("128 KiB ");
  554. /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
  555. cache_ctl = 0xc4000000;
  556. } else {
  557. puts("256 KiB ");
  558. cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
  559. }
  560. break;
  561. case 0x2:
  562. if (ver == SVR_8540 || ver == SVR_8560 ||
  563. ver == SVR_8541 || ver == SVR_8555) {
  564. puts("256 KiB ");
  565. /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
  566. cache_ctl = 0xc8000000;
  567. } else {
  568. puts("512 KiB ");
  569. /* set L2E=1, L2I=1, & L2SRAM=0 */
  570. cache_ctl = 0xc0000000;
  571. }
  572. break;
  573. case 0x3:
  574. puts("1024 KiB ");
  575. /* set L2E=1, L2I=1, & L2SRAM=0 */
  576. cache_ctl = 0xc0000000;
  577. break;
  578. }
  579. if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
  580. puts("already enabled");
  581. #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
  582. u32 l2srbar = l2cache->l2srbar0;
  583. if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
  584. && l2srbar >= CONFIG_SYS_FLASH_BASE) {
  585. l2srbar = CONFIG_SYS_INIT_L2_ADDR;
  586. l2cache->l2srbar0 = l2srbar;
  587. printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
  588. }
  589. #endif /* CONFIG_SYS_INIT_L2_ADDR */
  590. puts("\n");
  591. } else {
  592. asm("msync;isync");
  593. l2cache->l2ctl = cache_ctl; /* invalidate & enable */
  594. asm("msync;isync");
  595. puts("enabled\n");
  596. }
  597. #elif defined(CONFIG_BACKSIDE_L2_CACHE)
  598. if (SVR_SOC_VER(svr) == SVR_P2040) {
  599. puts("N/A\n");
  600. goto skip_l2;
  601. }
  602. u32 l2cfg0 = mfspr(SPRN_L2CFG0);
  603. /* invalidate the L2 cache */
  604. mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
  605. while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
  606. ;
  607. #ifdef CONFIG_SYS_CACHE_STASHING
  608. /* set stash id to (coreID) * 2 + 32 + L2 (1) */
  609. mtspr(SPRN_L2CSR1, (32 + 1));
  610. #endif
  611. /* enable the cache */
  612. mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
  613. if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
  614. while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
  615. ;
  616. print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
  617. }
  618. skip_l2:
  619. #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  620. if (l2cache->l2csr0 & L2CSR0_L2E)
  621. print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
  622. " enabled\n");
  623. enable_cluster_l2();
  624. #else
  625. puts("disabled\n");
  626. #endif
  627. return 0;
  628. }
  629. /*
  630. *
  631. * The newer 8548, etc, parts have twice as much cache, but
  632. * use the same bit-encoding as the older 8555, etc, parts.
  633. *
  634. */
  635. int cpu_init_r(void)
  636. {
  637. __maybe_unused u32 svr = get_svr();
  638. #ifdef CONFIG_SYS_LBC_LCRR
  639. fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
  640. #endif
  641. #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
  642. extern int spin_table_compat;
  643. const char *spin;
  644. #endif
  645. #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  646. ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
  647. #endif
  648. #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
  649. defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
  650. /*
  651. * CPU22 and NMG_CPU_A011 share the same workaround.
  652. * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  653. * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  654. * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
  655. * fixed in 2.0. NMG_CPU_A011 is activated by default and can
  656. * be disabled by hwconfig with syntax:
  657. *
  658. * fsl_cpu_a011:disable
  659. */
  660. extern int enable_cpu_a011_workaround;
  661. #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
  662. enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
  663. #else
  664. char buffer[HWCONFIG_BUFFER_SIZE];
  665. char *buf = NULL;
  666. int n, res;
  667. n = env_get_f("hwconfig", buffer, sizeof(buffer));
  668. if (n > 0)
  669. buf = buffer;
  670. res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
  671. if (res > 0) {
  672. enable_cpu_a011_workaround = 0;
  673. } else {
  674. if (n >= HWCONFIG_BUFFER_SIZE) {
  675. printf("fsl_cpu_a011 was not found. hwconfig variable "
  676. "may be too long\n");
  677. }
  678. enable_cpu_a011_workaround =
  679. (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
  680. (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
  681. }
  682. #endif
  683. if (enable_cpu_a011_workaround) {
  684. flush_dcache();
  685. mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
  686. sync();
  687. }
  688. #endif
  689. #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
  690. flush_dcache();
  691. mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
  692. sync();
  693. #endif
  694. #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
  695. /*
  696. * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
  697. * in write shadow mode. Checking DCWS before setting SPR 976.
  698. */
  699. if (mfspr(L1CSR2) & L1CSR2_DCWS)
  700. mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
  701. #endif
  702. #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
  703. spin = env_get("spin_table_compat");
  704. if (spin && (*spin == 'n'))
  705. spin_table_compat = 0;
  706. else
  707. spin_table_compat = 1;
  708. #endif
  709. #ifdef CONFIG_FSL_CORENET
  710. set_liodns();
  711. #ifdef CONFIG_SYS_DPAA_QBMAN
  712. setup_qbman_portals();
  713. #endif
  714. #endif
  715. l2cache_init();
  716. #if defined(CONFIG_RAMBOOT_PBL)
  717. disable_cpc_sram();
  718. #endif
  719. enable_cpc();
  720. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  721. enable_tdm_law();
  722. #endif
  723. #ifndef CONFIG_SYS_FSL_NO_SERDES
  724. /* needs to be in ram since code uses global static vars */
  725. fsl_serdes_init();
  726. #endif
  727. #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  728. #define MCFGR_AXIPIPE 0x000000f0
  729. if (IS_SVR_REV(svr, 1, 0))
  730. sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
  731. #endif
  732. #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
  733. if (IS_SVR_REV(svr, 1, 0)) {
  734. int i;
  735. __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
  736. for (i = 0; i < 12; i++) {
  737. p += i + (i > 5 ? 11 : 0);
  738. out_be32(p, 0x2);
  739. }
  740. p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
  741. out_be32(p, 0x34);
  742. }
  743. #endif
  744. #ifdef CONFIG_SYS_SRIO
  745. srio_init();
  746. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  747. char *s = env_get("bootmaster");
  748. if (s) {
  749. if (!strcmp(s, "SRIO1")) {
  750. srio_boot_master(1);
  751. srio_boot_master_release_slave(1);
  752. }
  753. if (!strcmp(s, "SRIO2")) {
  754. srio_boot_master(2);
  755. srio_boot_master_release_slave(2);
  756. }
  757. }
  758. #endif
  759. #endif
  760. #if defined(CONFIG_MP)
  761. setup_mp();
  762. #endif
  763. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
  764. {
  765. if (SVR_MAJ(svr) < 3) {
  766. void *p;
  767. p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
  768. setbits_be32(p, 1 << (31 - 14));
  769. }
  770. }
  771. #endif
  772. #ifdef CONFIG_SYS_LBC_LCRR
  773. /*
  774. * Modify the CLKDIV field of LCRR register to improve the writing
  775. * speed for NOR flash.
  776. */
  777. clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
  778. __raw_readl(&lbc->lcrr);
  779. isync();
  780. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
  781. udelay(100);
  782. #endif
  783. #endif
  784. #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
  785. {
  786. struct ccsr_usb_phy __iomem *usb_phy1 =
  787. (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
  788. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  789. if (has_erratum_a006261())
  790. fsl_erratum_a006261_workaround(usb_phy1);
  791. #endif
  792. out_be32(&usb_phy1->usb_enable_override,
  793. CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
  794. }
  795. #endif
  796. #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
  797. {
  798. struct ccsr_usb_phy __iomem *usb_phy2 =
  799. (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
  800. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  801. if (has_erratum_a006261())
  802. fsl_erratum_a006261_workaround(usb_phy2);
  803. #endif
  804. out_be32(&usb_phy2->usb_enable_override,
  805. CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
  806. }
  807. #endif
  808. #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
  809. /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
  810. * multi-bit ECC errors which has impact on performance, so software
  811. * should disable all ECC reporting from USB1 and USB2.
  812. */
  813. if (IS_SVR_REV(get_svr(), 1, 0)) {
  814. struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
  815. (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
  816. setbits_be32(&dcfg->ecccr1,
  817. (DCSR_DCFG_ECC_DISABLE_USB1 |
  818. DCSR_DCFG_ECC_DISABLE_USB2));
  819. }
  820. #endif
  821. #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
  822. struct ccsr_usb_phy __iomem *usb_phy =
  823. (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
  824. setbits_be32(&usb_phy->pllprg[1],
  825. CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
  826. CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
  827. CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
  828. CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
  829. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  830. usb_single_source_clk_configure(usb_phy);
  831. #endif
  832. setbits_be32(&usb_phy->port1.ctrl,
  833. CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
  834. setbits_be32(&usb_phy->port1.drvvbuscfg,
  835. CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
  836. setbits_be32(&usb_phy->port1.pwrfltcfg,
  837. CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
  838. setbits_be32(&usb_phy->port2.ctrl,
  839. CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
  840. setbits_be32(&usb_phy->port2.drvvbuscfg,
  841. CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
  842. setbits_be32(&usb_phy->port2.pwrfltcfg,
  843. CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
  844. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  845. if (has_erratum_a006261())
  846. fsl_erratum_a006261_workaround(usb_phy);
  847. #endif
  848. #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
  849. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  850. erratum_a009942_check_cpo();
  851. #endif
  852. #ifdef CONFIG_FMAN_ENET
  853. #ifndef CONFIG_DM_ETH
  854. fman_enet_init();
  855. #endif
  856. #endif
  857. #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
  858. if (pamu_init() < 0)
  859. fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
  860. #endif
  861. #ifdef CONFIG_FSL_CAAM
  862. sec_init();
  863. #if defined(CONFIG_ARCH_C29X)
  864. if ((SVR_SOC_VER(svr) == SVR_C292) ||
  865. (SVR_SOC_VER(svr) == SVR_C293))
  866. sec_init_idx(1);
  867. if (SVR_SOC_VER(svr) == SVR_C293)
  868. sec_init_idx(2);
  869. #endif
  870. #endif
  871. #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
  872. /*
  873. * For P1022/1013 Rev1.0 silicon, after power on SATA host
  874. * controller is configured in legacy mode instead of the
  875. * expected enterprise mode. Software needs to clear bit[28]
  876. * of HControl register to change to enterprise mode from
  877. * legacy mode. We assume that the controller is offline.
  878. */
  879. if (IS_SVR_REV(svr, 1, 0) &&
  880. ((SVR_SOC_VER(svr) == SVR_P1022) ||
  881. (SVR_SOC_VER(svr) == SVR_P1013))) {
  882. fsl_sata_reg_t *reg;
  883. /* first SATA controller */
  884. reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
  885. clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
  886. /* second SATA controller */
  887. reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
  888. clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
  889. }
  890. #endif
  891. init_used_tlb_cams();
  892. return 0;
  893. }
  894. void arch_preboot_os(void)
  895. {
  896. u32 msr;
  897. /*
  898. * We are changing interrupt offsets and are about to boot the OS so
  899. * we need to make sure we disable all async interrupts. EE is already
  900. * disabled by the time we get called.
  901. */
  902. msr = mfmsr();
  903. msr &= ~(MSR_ME|MSR_CE);
  904. mtmsr(msr);
  905. }
  906. void cpu_secondary_init_r(void)
  907. {
  908. #ifdef CONFIG_QE
  909. #ifdef CONFIG_U_QE
  910. uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
  911. #else
  912. uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
  913. #endif
  914. qe_init(qe_base);
  915. qe_reset();
  916. #endif
  917. }
  918. #ifdef CONFIG_BOARD_LATE_INIT
  919. int board_late_init(void)
  920. {
  921. #ifdef CONFIG_CHAIN_OF_TRUST
  922. fsl_setenv_chain_of_trust();
  923. #endif
  924. return 0;
  925. }
  926. #endif