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- if ARCH_STM32MP
- config SPL
- select SPL_BOARD_INIT
- select SPL_CLK
- select SPL_DM
- select SPL_DM_SEQ_ALIAS
- select SPL_DRIVERS_MISC_SUPPORT
- select SPL_FRAMEWORK
- select SPL_GPIO_SUPPORT
- select SPL_LIBCOMMON_SUPPORT
- select SPL_LIBGENERIC_SUPPORT
- select SPL_OF_CONTROL
- select SPL_OF_TRANSLATE
- select SPL_PINCTRL
- select SPL_REGMAP
- select SPL_DM_RESET
- select SPL_SERIAL_SUPPORT
- select SPL_SYSCON
- select SPL_WATCHDOG if WATCHDOG
- imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
- imply SPL_BOOTSTAGE if BOOTSTAGE
- imply SPL_DISPLAY_PRINT
- imply SPL_LIBDISK_SUPPORT
- imply SPL_SPI_LOAD if SPL_SPI_SUPPORT
- config SYS_SOC
- default "stm32mp"
- config SYS_MALLOC_LEN
- default 0x2000000
- config ENV_SIZE
- default 0x2000
- config STM32MP15x
- bool "Support STMicroelectronics STM32MP15x Soc"
- select ARCH_SUPPORT_PSCI if !TFABOOT
- select ARM_SMCCC if TFABOOT
- select CPU_V7A
- select CPU_V7_HAS_NONSEC if !TFABOOT
- select CPU_V7_HAS_VIRT
- select OF_BOARD_SETUP
- select PINCTRL_STM32
- select STM32_RCC
- select STM32_RESET
- select STM32_SERIAL
- select SYS_ARCH_TIMER
- imply CMD_NVEDIT_INFO
- imply SYSRESET_PSCI if TFABOOT
- imply SYSRESET_SYSCON if !TFABOOT
- help
- support of STMicroelectronics SOC STM32MP15x family
- STM32MP157, STM32MP153 or STM32MP151
- STMicroelectronics MPU with core ARMv7
- dual core A7 for STM32MP157/3, monocore for STM32MP151
- target all the STMicroelectronics board with SOC STM32MP1 family
- choice
- prompt "STM32MP15x board select"
- optional
- config TARGET_ST_STM32MP15x
- bool "STMicroelectronics STM32MP15x boards"
- select STM32MP15x
- imply BOOTCOUNT_LIMIT
- imply BOOTSTAGE
- imply CMD_BOOTCOUNT
- imply CMD_BOOTSTAGE
- imply CMD_CLS if CMD_BMP
- imply DISABLE_CONSOLE
- imply PRE_CONSOLE_BUFFER
- imply SILENT_CONSOLE
- help
- target the STMicroelectronics board with SOC STM32MP15x
- managed by board/st/stm32mp1:
- Evalulation board (EV1) or Discovery board (DK1 and DK2).
- The difference between board are managed with devicetree
- config TARGET_MICROGEA_STM32MP1
- bool "Engicam MicroGEA STM32MP1 SOM"
- select STM32MP15x
- imply BOOTCOUNT_LIMIT
- imply BOOTSTAGE
- imply CMD_BOOTCOUNT
- imply CMD_BOOTSTAGE
- imply CMD_CLS if CMD_BMP
- imply DISABLE_CONSOLE
- imply PRE_CONSOLE_BUFFER
- imply SILENT_CONSOLE
- help
- MicroGEA STM32MP1 is a STM32MP157A based Micro SOM.
- MicroGEA STM32MP1 MicroDev 2.0:
- * MicroDev 2.0 is a general purpose miniature carrier board with CAN,
- LTE and LVDS panel interfaces.
- * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
- for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
- MicroGEA STM32MP1 MicroDev 2.0 7" OF:
- * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS
- panel and toucscreen.
- * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
- pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7"
- Open Frame Solution board.
- config TARGET_ICORE_STM32MP1
- bool "Engicam i.Core STM32MP1 SOM"
- select STM32MP15x
- imply BOOTCOUNT_LIMIT
- imply BOOTSTAGE
- imply CMD_BOOTCOUNT
- imply CMD_BOOTSTAGE
- imply CMD_CLS if CMD_BMP
- imply DISABLE_CONSOLE
- imply PRE_CONSOLE_BUFFER
- imply SILENT_CONSOLE
- help
- i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
- i.Core STM32MP1 EDIMM2.2:
- * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
- * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
- creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
- i.Core STM32MP1 C.TOUCH 2.0
- * C.TOUCH 2.0 is a general purpose Carrier board.
- * i.Core STM32MP1 needs to mount on top of this Carrier board
- for creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
- config TARGET_DH_STM32MP1_PDK2
- bool "DH STM32MP1 PDK2"
- select STM32MP15x
- imply BOOTCOUNT_LIMIT
- imply CMD_BOOTCOUNT
- help
- Target the DH PDK2 development kit with STM32MP15x SoM.
- endchoice
- config SYS_TEXT_BASE
- default 0xC0100000
- config NR_DRAM_BANKS
- default 1
- config DDR_CACHEABLE_SIZE
- hex "Size of the DDR marked cacheable in pre-reloc stage"
- default 0x10000000 if TFABOOT
- default 0x40000000
- help
- Define the size of the DDR marked as cacheable in U-Boot
- pre-reloc stage.
- This option can be useful to avoid speculatif access
- to secured area of DDR used by TF-A or OP-TEE before U-Boot
- initialization.
- The areas marked "no-map" in device tree should be located
- before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
- config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
- hex "Partition on MMC2 to use to load U-Boot from"
- depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- default 1
- help
- Partition on the second MMC to load U-Boot from when the MMC is being
- used in raw mode
- config STM32_ETZPC
- bool "STM32 Extended TrustZone Protection"
- depends on STM32MP15x
- default y
- help
- Say y to enable STM32 Extended TrustZone Protection
- config CMD_STM32KEY
- bool "command stm32key to fuse public key hash"
- default n
- help
- fuse public key hash in corresponding fuse used to authenticate
- binary.
- This command is used to evaluate the secure boot on stm32mp SOC,
- it is deactivated by default in real products.
- config PRE_CON_BUF_ADDR
- default 0xC02FF000
- config PRE_CON_BUF_SZ
- default 4096
- config BOOTSTAGE_STASH_ADDR
- default 0xC3000000
- if BOOTCOUNT_LIMIT
- config SYS_BOOTCOUNT_SINGLEWORD
- default y
- # TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
- config SYS_BOOTCOUNT_ADDR
- default 0x5C00A154
- endif
- if DEBUG_UART
- config DEBUG_UART_BOARD_INIT
- default y
- # debug on UART4 by default
- config DEBUG_UART_BASE
- default 0x40010000
- # clock source is HSI on reset
- config DEBUG_UART_CLOCK
- default 64000000
- endif
- source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
- source "board/dhelectronics/dh_stm32mp1/Kconfig"
- source "board/engicam/stm32mp1/Kconfig"
- source "board/st/stm32mp1/Kconfig"
- endif
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