clk_stm32f.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #define LOG_CATEGORY UCLASS_CLK
  7. #include <common.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <stm32_rcc.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/stm32.h>
  14. #include <asm/arch/stm32_pwr.h>
  15. #include <dm/device_compat.h>
  16. #include <dt-bindings/mfd/stm32f7-rcc.h>
  17. #include <linux/bitops.h>
  18. #define RCC_CR_HSION BIT(0)
  19. #define RCC_CR_HSEON BIT(16)
  20. #define RCC_CR_HSERDY BIT(17)
  21. #define RCC_CR_HSEBYP BIT(18)
  22. #define RCC_CR_CSSON BIT(19)
  23. #define RCC_CR_PLLON BIT(24)
  24. #define RCC_CR_PLLRDY BIT(25)
  25. #define RCC_CR_PLLSAION BIT(28)
  26. #define RCC_CR_PLLSAIRDY BIT(29)
  27. #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
  28. #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
  29. #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
  30. #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
  31. #define RCC_PLLCFGR_PLLSRC BIT(22)
  32. #define RCC_PLLCFGR_PLLM_SHIFT 0
  33. #define RCC_PLLCFGR_PLLN_SHIFT 6
  34. #define RCC_PLLCFGR_PLLP_SHIFT 16
  35. #define RCC_PLLCFGR_PLLQ_SHIFT 24
  36. #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
  37. #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
  38. #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
  39. #define RCC_CFGR_SW0 BIT(0)
  40. #define RCC_CFGR_SW1 BIT(1)
  41. #define RCC_CFGR_SW_MASK GENMASK(1, 0)
  42. #define RCC_CFGR_SW_HSI 0
  43. #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
  44. #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
  45. #define RCC_CFGR_SWS0 BIT(2)
  46. #define RCC_CFGR_SWS1 BIT(3)
  47. #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
  48. #define RCC_CFGR_SWS_HSI 0
  49. #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
  50. #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
  51. #define RCC_CFGR_HPRE_SHIFT 4
  52. #define RCC_CFGR_PPRE1_SHIFT 10
  53. #define RCC_CFGR_PPRE2_SHIFT 13
  54. #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
  55. #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
  56. #define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
  57. #define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
  58. #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
  59. #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
  60. #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
  61. #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
  62. #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
  63. #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
  64. #define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
  65. #define RCC_DCKCFGRX_TIMPRE BIT(24)
  66. #define RCC_DCKCFGRX_CK48MSEL BIT(27)
  67. #define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
  68. #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
  69. #define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
  70. #define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
  71. #define RCC_DCKCFGR_PLLSAIDIVR_2 0
  72. /*
  73. * RCC AHB1ENR specific definitions
  74. */
  75. #define RCC_AHB1ENR_ETHMAC_EN BIT(25)
  76. #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
  77. #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
  78. /*
  79. * RCC APB1ENR specific definitions
  80. */
  81. #define RCC_APB1ENR_TIM2EN BIT(0)
  82. #define RCC_APB1ENR_PWREN BIT(28)
  83. /*
  84. * RCC APB2ENR specific definitions
  85. */
  86. #define RCC_APB2ENR_SYSCFGEN BIT(14)
  87. #define RCC_APB2ENR_SAI1EN BIT(22)
  88. enum pllsai_div {
  89. PLLSAIP,
  90. PLLSAIQ,
  91. PLLSAIR,
  92. };
  93. static const struct stm32_clk_info stm32f4_clk_info = {
  94. /* 180 MHz */
  95. .sys_pll_psc = {
  96. .pll_n = 360,
  97. .pll_p = 2,
  98. .pll_q = 8,
  99. .ahb_psc = AHB_PSC_1,
  100. .apb1_psc = APB_PSC_4,
  101. .apb2_psc = APB_PSC_2,
  102. },
  103. .has_overdrive = false,
  104. .v2 = false,
  105. };
  106. static const struct stm32_clk_info stm32f7_clk_info = {
  107. /* 200 MHz */
  108. .sys_pll_psc = {
  109. .pll_n = 400,
  110. .pll_p = 2,
  111. .pll_q = 8,
  112. .ahb_psc = AHB_PSC_1,
  113. .apb1_psc = APB_PSC_4,
  114. .apb2_psc = APB_PSC_2,
  115. },
  116. .has_overdrive = true,
  117. .v2 = true,
  118. };
  119. struct stm32_clk {
  120. struct stm32_rcc_regs *base;
  121. struct stm32_pwr_regs *pwr_regs;
  122. struct stm32_clk_info info;
  123. unsigned long hse_rate;
  124. bool pllsaip;
  125. };
  126. #ifdef CONFIG_VIDEO_STM32
  127. static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
  128. #endif
  129. static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
  130. static int configure_clocks(struct udevice *dev)
  131. {
  132. struct stm32_clk *priv = dev_get_priv(dev);
  133. struct stm32_rcc_regs *regs = priv->base;
  134. struct stm32_pwr_regs *pwr = priv->pwr_regs;
  135. struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
  136. /* Reset RCC configuration */
  137. setbits_le32(&regs->cr, RCC_CR_HSION);
  138. writel(0, &regs->cfgr); /* Reset CFGR */
  139. clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
  140. | RCC_CR_PLLON | RCC_CR_PLLSAION));
  141. writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
  142. clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
  143. writel(0, &regs->cir); /* Disable all interrupts */
  144. /* Configure for HSE+PLL operation */
  145. setbits_le32(&regs->cr, RCC_CR_HSEON);
  146. while (!(readl(&regs->cr) & RCC_CR_HSERDY))
  147. ;
  148. setbits_le32(&regs->cfgr, ((
  149. sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
  150. | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
  151. | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
  152. /* Configure the main PLL */
  153. setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
  154. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
  155. sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
  156. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
  157. sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
  158. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
  159. ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
  160. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
  161. sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
  162. /* configure SDMMC clock */
  163. if (priv->info.v2) { /*stm32f7 case */
  164. if (priv->pllsaip)
  165. /* select PLLSAIP as 48MHz clock source */
  166. setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
  167. else
  168. /* select PLLQ as 48MHz clock source */
  169. clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
  170. /* select 48MHz as SDMMC1 clock source */
  171. clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
  172. /* select 48MHz as SDMMC2 clock source */
  173. clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
  174. } else { /* stm32f4 case */
  175. if (priv->pllsaip)
  176. /* select PLLSAIP as 48MHz clock source */
  177. setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
  178. else
  179. /* select PLLQ as 48MHz clock source */
  180. clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
  181. /* select 48MHz as SDMMC1 clock source */
  182. clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
  183. }
  184. /*
  185. * Configure the SAI PLL to generate LTDC pixel clock and
  186. * 48 Mhz for SDMMC and USB
  187. */
  188. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIP_MASK,
  189. RCC_PLLSAICFGR_PLLSAIP_4);
  190. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
  191. RCC_PLLSAICFGR_PLLSAIR_3);
  192. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
  193. 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
  194. clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
  195. RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
  196. /* Enable the main PLL */
  197. setbits_le32(&regs->cr, RCC_CR_PLLON);
  198. while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
  199. ;
  200. /* Enable the SAI PLL */
  201. setbits_le32(&regs->cr, RCC_CR_PLLSAION);
  202. while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
  203. ;
  204. setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
  205. if (priv->info.has_overdrive) {
  206. /*
  207. * Enable high performance mode
  208. * System frequency up to 200 MHz
  209. */
  210. setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
  211. /* Infinite wait! */
  212. while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
  213. ;
  214. /* Enable the Over-drive switch */
  215. setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
  216. /* Infinite wait! */
  217. while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
  218. ;
  219. }
  220. stm32_flash_latency_cfg(5);
  221. clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
  222. setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
  223. while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
  224. RCC_CFGR_SWS_PLL)
  225. ;
  226. #ifdef CONFIG_ETH_DESIGNWARE
  227. /* gate the SYSCFG clock, needed to set RMII ethernet interface */
  228. setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
  229. #endif
  230. return 0;
  231. }
  232. static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
  233. {
  234. struct stm32_rcc_regs *regs = priv->base;
  235. if (priv->info.v2) /*stm32f7 case */
  236. return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
  237. else
  238. return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
  239. }
  240. static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
  241. {
  242. struct stm32_rcc_regs *regs = priv->base;
  243. u16 pllm, pllsain;
  244. pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
  245. pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
  246. >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
  247. return ((priv->hse_rate / pllm) * pllsain);
  248. }
  249. static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
  250. enum pllsai_div output)
  251. {
  252. struct stm32_rcc_regs *regs = priv->base;
  253. u16 pll_div_output;
  254. switch (output) {
  255. case PLLSAIP:
  256. pll_div_output = ((((readl(&regs->pllsaicfgr)
  257. & RCC_PLLSAICFGR_PLLSAIP_MASK)
  258. >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
  259. break;
  260. case PLLSAIQ:
  261. pll_div_output = (readl(&regs->pllsaicfgr)
  262. & RCC_PLLSAICFGR_PLLSAIQ_MASK)
  263. >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
  264. break;
  265. case PLLSAIR:
  266. pll_div_output = (readl(&regs->pllsaicfgr)
  267. & RCC_PLLSAICFGR_PLLSAIR_MASK)
  268. >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
  269. break;
  270. default:
  271. log_err("incorrect PLLSAI output %d\n", output);
  272. return -EINVAL;
  273. }
  274. return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
  275. }
  276. static bool stm32_get_timpre(struct stm32_clk *priv)
  277. {
  278. struct stm32_rcc_regs *regs = priv->base;
  279. u32 val;
  280. if (priv->info.v2) /*stm32f7 case */
  281. val = readl(&regs->dckcfgr2);
  282. else
  283. val = readl(&regs->dckcfgr);
  284. /* get timer prescaler */
  285. return !!(val & RCC_DCKCFGRX_TIMPRE);
  286. }
  287. static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
  288. {
  289. u8 shift;
  290. /* Prescaler table lookups for clock computation */
  291. u8 ahb_psc_table[16] = {
  292. 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
  293. };
  294. shift = ahb_psc_table[(
  295. (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
  296. >> RCC_CFGR_HPRE_SHIFT)];
  297. return sysclk >> shift;
  298. };
  299. static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
  300. {
  301. /* Prescaler table lookups for clock computation */
  302. u8 apb_psc_table[8] = {
  303. 0, 0, 0, 0, 1, 2, 3, 4
  304. };
  305. if (apb == APB1)
  306. return apb_psc_table[(
  307. (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
  308. >> RCC_CFGR_PPRE1_SHIFT)];
  309. else /* APB2 */
  310. return apb_psc_table[(
  311. (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
  312. >> RCC_CFGR_PPRE2_SHIFT)];
  313. };
  314. static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
  315. enum apb apb)
  316. {
  317. struct stm32_rcc_regs *regs = priv->base;
  318. u8 shift = stm32_get_apb_shift(regs, apb);
  319. if (stm32_get_timpre(priv))
  320. /*
  321. * if APB prescaler is configured to a
  322. * division factor of 1, 2 or 4
  323. */
  324. switch (shift) {
  325. case 0:
  326. case 1:
  327. case 2:
  328. return stm32_get_hclk_rate(regs, sysclk);
  329. default:
  330. return (sysclk >> shift) * 4;
  331. }
  332. else
  333. /*
  334. * if APB prescaler is configured to a
  335. * division factor of 1
  336. */
  337. if (shift == 0)
  338. return sysclk;
  339. else
  340. return (sysclk >> shift) * 2;
  341. };
  342. static ulong stm32_clk_get_rate(struct clk *clk)
  343. {
  344. struct stm32_clk *priv = dev_get_priv(clk->dev);
  345. struct stm32_rcc_regs *regs = priv->base;
  346. u32 sysclk = 0;
  347. u32 vco;
  348. u32 sdmmcxsel_bit;
  349. u32 saidivr;
  350. u32 pllsai_rate;
  351. u16 pllm, plln, pllp, pllq;
  352. if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
  353. RCC_CFGR_SWS_PLL) {
  354. pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
  355. plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
  356. >> RCC_PLLCFGR_PLLN_SHIFT);
  357. pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
  358. >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
  359. pllq = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
  360. >> RCC_PLLCFGR_PLLQ_SHIFT);
  361. vco = (priv->hse_rate / pllm) * plln;
  362. sysclk = vco / pllp;
  363. } else {
  364. return -EINVAL;
  365. }
  366. switch (clk->id) {
  367. /*
  368. * AHB CLOCK: 3 x 32 bits consecutive registers are used :
  369. * AHB1, AHB2 and AHB3
  370. */
  371. case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
  372. return stm32_get_hclk_rate(regs, sysclk);
  373. /* APB1 CLOCK */
  374. case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
  375. /* For timer clock, an additionnal prescaler is used*/
  376. switch (clk->id) {
  377. case STM32F7_APB1_CLOCK(TIM2):
  378. case STM32F7_APB1_CLOCK(TIM3):
  379. case STM32F7_APB1_CLOCK(TIM4):
  380. case STM32F7_APB1_CLOCK(TIM5):
  381. case STM32F7_APB1_CLOCK(TIM6):
  382. case STM32F7_APB1_CLOCK(TIM7):
  383. case STM32F7_APB1_CLOCK(TIM12):
  384. case STM32F7_APB1_CLOCK(TIM13):
  385. case STM32F7_APB1_CLOCK(TIM14):
  386. return stm32_get_timer_rate(priv, sysclk, APB1);
  387. }
  388. return (sysclk >> stm32_get_apb_shift(regs, APB1));
  389. /* APB2 CLOCK */
  390. case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
  391. switch (clk->id) {
  392. /*
  393. * particular case for SDMMC1 and SDMMC2 :
  394. * 48Mhz source clock can be from main PLL or from
  395. * PLLSAIP
  396. */
  397. case STM32F7_APB2_CLOCK(SDMMC1):
  398. case STM32F7_APB2_CLOCK(SDMMC2):
  399. if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
  400. sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
  401. else
  402. sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
  403. if (readl(&regs->dckcfgr2) & sdmmcxsel_bit)
  404. /* System clock is selected as SDMMC1 clock */
  405. return sysclk;
  406. /*
  407. * 48 MHz can be generated by either PLLSAIP
  408. * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
  409. */
  410. if (stm32_clk_get_ck48msel(priv))
  411. return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
  412. else
  413. return (vco / pllq);
  414. break;
  415. /* For timer clock, an additionnal prescaler is used*/
  416. case STM32F7_APB2_CLOCK(TIM1):
  417. case STM32F7_APB2_CLOCK(TIM8):
  418. case STM32F7_APB2_CLOCK(TIM9):
  419. case STM32F7_APB2_CLOCK(TIM10):
  420. case STM32F7_APB2_CLOCK(TIM11):
  421. return stm32_get_timer_rate(priv, sysclk, APB2);
  422. break;
  423. /* particular case for LTDC clock */
  424. case STM32F7_APB2_CLOCK(LTDC):
  425. saidivr = readl(&regs->dckcfgr);
  426. saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
  427. >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
  428. pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
  429. return pllsai_rate / pllsaidivr_table[saidivr];
  430. }
  431. return (sysclk >> stm32_get_apb_shift(regs, APB2));
  432. default:
  433. dev_err(clk->dev, "clock index %ld out of range\n", clk->id);
  434. return -EINVAL;
  435. }
  436. }
  437. static ulong stm32_set_rate(struct clk *clk, ulong rate)
  438. {
  439. #ifdef CONFIG_VIDEO_STM32
  440. struct stm32_clk *priv = dev_get_priv(clk->dev);
  441. struct stm32_rcc_regs *regs = priv->base;
  442. u32 pllsair_rate, pllsai_vco_rate, current_rate;
  443. u32 best_div, best_diff, diff;
  444. u16 div;
  445. u8 best_plldivr, best_pllsaidivr;
  446. u8 i, j;
  447. bool found = false;
  448. /* Only set_rate for LTDC clock is implemented */
  449. if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
  450. dev_err(clk->dev,
  451. "set_rate not implemented for clock index %ld\n",
  452. clk->id);
  453. return 0;
  454. }
  455. if (rate == stm32_clk_get_rate(clk))
  456. /* already set to requested rate */
  457. return rate;
  458. /* get the current PLLSAIR output freq */
  459. pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
  460. best_div = pllsair_rate / rate;
  461. /* look into pllsaidivr_table if this divider is available*/
  462. for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
  463. if (best_div == pllsaidivr_table[i]) {
  464. /* set pll_saidivr with found value */
  465. clrsetbits_le32(&regs->dckcfgr,
  466. RCC_DCKCFGR_PLLSAIDIVR_MASK,
  467. pllsaidivr_table[i]);
  468. return rate;
  469. }
  470. /*
  471. * As no pllsaidivr value is suitable to obtain requested freq,
  472. * test all combination of pllsaidivr * pllsair and find the one
  473. * which give freq closest to requested rate.
  474. */
  475. pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
  476. best_diff = ULONG_MAX;
  477. best_pllsaidivr = 0;
  478. best_plldivr = 0;
  479. /*
  480. * start at index 2 of plldivr_table as divider value at index 0
  481. * and 1 are 0)
  482. */
  483. for (i = 2; i < sizeof(plldivr_table); i++) {
  484. for (j = 0; j < sizeof(pllsaidivr_table); j++) {
  485. div = plldivr_table[i] * pllsaidivr_table[j];
  486. current_rate = pllsai_vco_rate / div;
  487. /* perfect combination is found ? */
  488. if (current_rate == rate) {
  489. best_pllsaidivr = j;
  490. best_plldivr = i;
  491. found = true;
  492. break;
  493. }
  494. diff = (current_rate > rate) ?
  495. current_rate - rate : rate - current_rate;
  496. /* found a better combination ? */
  497. if (diff < best_diff) {
  498. best_diff = diff;
  499. best_pllsaidivr = j;
  500. best_plldivr = i;
  501. }
  502. }
  503. if (found)
  504. break;
  505. }
  506. /* Disable the SAI PLL */
  507. clrbits_le32(&regs->cr, RCC_CR_PLLSAION);
  508. /* set pll_saidivr with found value */
  509. clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
  510. best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
  511. /* set pllsair with found value */
  512. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
  513. plldivr_table[best_plldivr]
  514. << RCC_PLLSAICFGR_PLLSAIR_SHIFT);
  515. /* Enable the SAI PLL */
  516. setbits_le32(&regs->cr, RCC_CR_PLLSAION);
  517. while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
  518. ;
  519. div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
  520. return pllsai_vco_rate / div;
  521. #else
  522. return 0;
  523. #endif
  524. }
  525. static int stm32_clk_enable(struct clk *clk)
  526. {
  527. struct stm32_clk *priv = dev_get_priv(clk->dev);
  528. struct stm32_rcc_regs *regs = priv->base;
  529. u32 offset = clk->id / 32;
  530. u32 bit_index = clk->id % 32;
  531. dev_dbg(clk->dev, "clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
  532. clk->id, offset, bit_index);
  533. setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
  534. return 0;
  535. }
  536. static int stm32_clk_probe(struct udevice *dev)
  537. {
  538. struct ofnode_phandle_args args;
  539. struct udevice *fixed_clock_dev = NULL;
  540. struct clk clk;
  541. int err;
  542. dev_dbg(dev, "%s\n", __func__);
  543. struct stm32_clk *priv = dev_get_priv(dev);
  544. fdt_addr_t addr;
  545. addr = dev_read_addr(dev);
  546. if (addr == FDT_ADDR_T_NONE)
  547. return -EINVAL;
  548. priv->base = (struct stm32_rcc_regs *)addr;
  549. priv->pllsaip = true;
  550. switch (dev_get_driver_data(dev)) {
  551. case STM32F42X:
  552. priv->pllsaip = false;
  553. /* fallback into STM32F469 case */
  554. case STM32F469:
  555. memcpy(&priv->info, &stm32f4_clk_info,
  556. sizeof(struct stm32_clk_info));
  557. break;
  558. case STM32F7:
  559. memcpy(&priv->info, &stm32f7_clk_info,
  560. sizeof(struct stm32_clk_info));
  561. break;
  562. default:
  563. return -EINVAL;
  564. }
  565. /* retrieve HSE frequency (external oscillator) */
  566. err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
  567. &fixed_clock_dev);
  568. if (err) {
  569. dev_err(dev, "Can't find fixed clock (%d)", err);
  570. return err;
  571. }
  572. err = clk_request(fixed_clock_dev, &clk);
  573. if (err) {
  574. dev_err(dev, "Can't request %s clk (%d)",
  575. fixed_clock_dev->name, err);
  576. return err;
  577. }
  578. /*
  579. * set pllm factor accordingly to the external oscillator
  580. * frequency (HSE). For STM32F4 and STM32F7, we want VCO
  581. * freq at 1MHz
  582. * if input PLL frequency is 25Mhz, divide it by 25
  583. */
  584. clk.id = 0;
  585. priv->hse_rate = clk_get_rate(&clk);
  586. if (priv->hse_rate < 1000000) {
  587. dev_err(dev, "unexpected HSE clock rate = %ld \"n",
  588. priv->hse_rate);
  589. return -EINVAL;
  590. }
  591. priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
  592. if (priv->info.has_overdrive) {
  593. err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
  594. &args);
  595. if (err) {
  596. dev_err(dev, "can't find syscon device (%d)\n", err);
  597. return err;
  598. }
  599. priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
  600. }
  601. configure_clocks(dev);
  602. return 0;
  603. }
  604. static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  605. {
  606. dev_dbg(clk->dev, "clk=%p\n", clk);
  607. if (args->args_count != 2) {
  608. dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count);
  609. return -EINVAL;
  610. }
  611. if (args->args_count)
  612. clk->id = args->args[1];
  613. else
  614. clk->id = 0;
  615. return 0;
  616. }
  617. static struct clk_ops stm32_clk_ops = {
  618. .of_xlate = stm32_clk_of_xlate,
  619. .enable = stm32_clk_enable,
  620. .get_rate = stm32_clk_get_rate,
  621. .set_rate = stm32_set_rate,
  622. };
  623. U_BOOT_DRIVER(stm32fx_clk) = {
  624. .name = "stm32fx_rcc_clock",
  625. .id = UCLASS_CLK,
  626. .ops = &stm32_clk_ops,
  627. .probe = stm32_clk_probe,
  628. .priv_auto = sizeof(struct stm32_clk),
  629. .flags = DM_FLAG_PRE_RELOC,
  630. };