usb_ohci.h 11 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * usb-ohci.h
  8. */
  9. static int cc_to_error[16] = {
  10. /* mapping of the OHCI CC status to error codes */
  11. /* No Error */ 0,
  12. /* CRC Error */ USB_ST_CRC_ERR,
  13. /* Bit Stuff */ USB_ST_BIT_ERR,
  14. /* Data Togg */ USB_ST_CRC_ERR,
  15. /* Stall */ USB_ST_STALLED,
  16. /* DevNotResp */ -1,
  17. /* PIDCheck */ USB_ST_BIT_ERR,
  18. /* UnExpPID */ USB_ST_BIT_ERR,
  19. /* DataOver */ USB_ST_BUF_ERR,
  20. /* DataUnder */ USB_ST_BUF_ERR,
  21. /* reservd */ -1,
  22. /* reservd */ -1,
  23. /* BufferOver */ USB_ST_BUF_ERR,
  24. /* BuffUnder */ USB_ST_BUF_ERR,
  25. /* Not Access */ -1,
  26. /* Not Access */ -1
  27. };
  28. /* ED States */
  29. #define ED_NEW 0x00
  30. #define ED_UNLINK 0x01
  31. #define ED_OPER 0x02
  32. #define ED_DEL 0x04
  33. #define ED_URB_DEL 0x08
  34. /* usb_ohci_ed */
  35. struct ed {
  36. __u32 hwINFO;
  37. __u32 hwTailP;
  38. __u32 hwHeadP;
  39. __u32 hwNextED;
  40. struct ed *ed_prev;
  41. __u8 int_period;
  42. __u8 int_branch;
  43. __u8 int_load;
  44. __u8 int_interval;
  45. __u8 state;
  46. __u8 type;
  47. __u16 last_iso;
  48. struct ed *ed_rm_list;
  49. struct usb_device *usb_dev;
  50. __u32 unused[3];
  51. } __attribute__((aligned(16)));
  52. typedef struct ed ed_t;
  53. /* TD info field */
  54. #define TD_CC 0xf0000000
  55. #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
  56. #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
  57. #define TD_EC 0x0C000000
  58. #define TD_T 0x03000000
  59. #define TD_T_DATA0 0x02000000
  60. #define TD_T_DATA1 0x03000000
  61. #define TD_T_TOGGLE 0x00000000
  62. #define TD_R 0x00040000
  63. #define TD_DI 0x00E00000
  64. #define TD_DI_SET(X) (((X) & 0x07)<< 21)
  65. #define TD_DP 0x00180000
  66. #define TD_DP_SETUP 0x00000000
  67. #define TD_DP_IN 0x00100000
  68. #define TD_DP_OUT 0x00080000
  69. #define TD_ISO 0x00010000
  70. #define TD_DEL 0x00020000
  71. /* CC Codes */
  72. #define TD_CC_NOERROR 0x00
  73. #define TD_CC_CRC 0x01
  74. #define TD_CC_BITSTUFFING 0x02
  75. #define TD_CC_DATATOGGLEM 0x03
  76. #define TD_CC_STALL 0x04
  77. #define TD_DEVNOTRESP 0x05
  78. #define TD_PIDCHECKFAIL 0x06
  79. #define TD_UNEXPECTEDPID 0x07
  80. #define TD_DATAOVERRUN 0x08
  81. #define TD_DATAUNDERRUN 0x09
  82. #define TD_BUFFEROVERRUN 0x0C
  83. #define TD_BUFFERUNDERRUN 0x0D
  84. #define TD_NOTACCESSED 0x0F
  85. #define MAXPSW 1
  86. struct td {
  87. __u32 hwINFO;
  88. __u32 hwCBP; /* Current Buffer Pointer */
  89. __u32 hwNextTD; /* Next TD Pointer */
  90. __u32 hwBE; /* Memory Buffer End Pointer */
  91. __u16 hwPSW[MAXPSW];
  92. __u8 unused;
  93. __u8 index;
  94. struct ed *ed;
  95. struct td *next_dl_td;
  96. struct usb_device *usb_dev;
  97. int transfer_len;
  98. __u32 data;
  99. __u32 unused2[2];
  100. } __attribute__((aligned(32)));
  101. typedef struct td td_t;
  102. #define OHCI_ED_SKIP (1 << 14)
  103. /*
  104. * The HCCA (Host Controller Communications Area) is a 256 byte
  105. * structure defined in the OHCI spec. that the host controller is
  106. * told the base address of. It must be 256-byte aligned.
  107. */
  108. #define NUM_INTS 32 /* part of the OHCI standard */
  109. struct ohci_hcca {
  110. __u32 int_table[NUM_INTS]; /* Interrupt ED table */
  111. __u16 frame_no; /* current frame number */
  112. __u16 pad1; /* set to 0 on each frame_no change */
  113. __u32 done_head; /* info returned for an interrupt */
  114. u8 reserved_for_hc[116];
  115. } __attribute__((aligned(256)));
  116. /*
  117. * Maximum number of root hub ports.
  118. */
  119. #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
  120. /*
  121. * This is the structure of the OHCI controller's memory mapped I/O
  122. * region. This is Memory Mapped I/O. You must use the readl() and
  123. * writel() macros defined in asm/io.h to access these!!
  124. */
  125. struct ohci_regs {
  126. /* control and status registers */
  127. __u32 revision;
  128. __u32 control;
  129. __u32 cmdstatus;
  130. __u32 intrstatus;
  131. __u32 intrenable;
  132. __u32 intrdisable;
  133. /* memory pointers */
  134. __u32 hcca;
  135. __u32 ed_periodcurrent;
  136. __u32 ed_controlhead;
  137. __u32 ed_controlcurrent;
  138. __u32 ed_bulkhead;
  139. __u32 ed_bulkcurrent;
  140. __u32 donehead;
  141. /* frame counters */
  142. __u32 fminterval;
  143. __u32 fmremaining;
  144. __u32 fmnumber;
  145. __u32 periodicstart;
  146. __u32 lsthresh;
  147. /* Root hub ports */
  148. struct ohci_roothub_regs {
  149. __u32 a;
  150. __u32 b;
  151. __u32 status;
  152. __u32 portstatus[MAX_ROOT_PORTS];
  153. } roothub;
  154. } __attribute__((aligned(32)));
  155. /* OHCI CONTROL AND STATUS REGISTER MASKS */
  156. /*
  157. * HcControl (control) register masks
  158. */
  159. #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
  160. #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
  161. #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
  162. #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
  163. #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
  164. #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
  165. #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
  166. #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
  167. #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
  168. /* pre-shifted values for HCFS */
  169. # define OHCI_USB_RESET (0 << 6)
  170. # define OHCI_USB_RESUME (1 << 6)
  171. # define OHCI_USB_OPER (2 << 6)
  172. # define OHCI_USB_SUSPEND (3 << 6)
  173. /*
  174. * HcCommandStatus (cmdstatus) register masks
  175. */
  176. #define OHCI_HCR (1 << 0) /* host controller reset */
  177. #define OHCI_CLF (1 << 1) /* control list filled */
  178. #define OHCI_BLF (1 << 2) /* bulk list filled */
  179. #define OHCI_OCR (1 << 3) /* ownership change request */
  180. #define OHCI_SOC (3 << 16) /* scheduling overrun count */
  181. /*
  182. * masks used with interrupt registers:
  183. * HcInterruptStatus (intrstatus)
  184. * HcInterruptEnable (intrenable)
  185. * HcInterruptDisable (intrdisable)
  186. */
  187. #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
  188. #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
  189. #define OHCI_INTR_SF (1 << 2) /* start frame */
  190. #define OHCI_INTR_RD (1 << 3) /* resume detect */
  191. #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
  192. #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
  193. #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
  194. #define OHCI_INTR_OC (1 << 30) /* ownership change */
  195. #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
  196. /* Virtual Root HUB */
  197. struct virt_root_hub {
  198. int devnum; /* Address of Root Hub endpoint */
  199. void *dev; /* was urb */
  200. void *int_addr;
  201. int send;
  202. int interval;
  203. };
  204. /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
  205. /* destination of request */
  206. #define RH_INTERFACE 0x01
  207. #define RH_ENDPOINT 0x02
  208. #define RH_OTHER 0x03
  209. #define RH_CLASS 0x20
  210. #define RH_VENDOR 0x40
  211. /* Requests: bRequest << 8 | bmRequestType */
  212. #define RH_GET_STATUS 0x0080
  213. #define RH_CLEAR_FEATURE 0x0100
  214. #define RH_SET_FEATURE 0x0300
  215. #define RH_SET_ADDRESS 0x0500
  216. #define RH_GET_DESCRIPTOR 0x0680
  217. #define RH_SET_DESCRIPTOR 0x0700
  218. #define RH_GET_CONFIGURATION 0x0880
  219. #define RH_SET_CONFIGURATION 0x0900
  220. #define RH_GET_STATE 0x0280
  221. #define RH_GET_INTERFACE 0x0A80
  222. #define RH_SET_INTERFACE 0x0B00
  223. #define RH_SYNC_FRAME 0x0C80
  224. /* Our Vendor Specific Request */
  225. #define RH_SET_EP 0x2000
  226. /* Hub port features */
  227. #define RH_PORT_CONNECTION 0x00
  228. #define RH_PORT_ENABLE 0x01
  229. #define RH_PORT_SUSPEND 0x02
  230. #define RH_PORT_OVER_CURRENT 0x03
  231. #define RH_PORT_RESET 0x04
  232. #define RH_PORT_POWER 0x08
  233. #define RH_PORT_LOW_SPEED 0x09
  234. #define RH_C_PORT_CONNECTION 0x10
  235. #define RH_C_PORT_ENABLE 0x11
  236. #define RH_C_PORT_SUSPEND 0x12
  237. #define RH_C_PORT_OVER_CURRENT 0x13
  238. #define RH_C_PORT_RESET 0x14
  239. /* Hub features */
  240. #define RH_C_HUB_LOCAL_POWER 0x00
  241. #define RH_C_HUB_OVER_CURRENT 0x01
  242. #define RH_DEVICE_REMOTE_WAKEUP 0x00
  243. #define RH_ENDPOINT_STALL 0x01
  244. #define RH_ACK 0x01
  245. #define RH_REQ_ERR -1
  246. #define RH_NACK 0x00
  247. /* OHCI ROOT HUB REGISTER MASKS */
  248. /* roothub.portstatus [i] bits */
  249. #define RH_PS_CCS 0x00000001 /* current connect status */
  250. #define RH_PS_PES 0x00000002 /* port enable status */
  251. #define RH_PS_PSS 0x00000004 /* port suspend status */
  252. #define RH_PS_POCI 0x00000008 /* port over current indicator */
  253. #define RH_PS_PRS 0x00000010 /* port reset status */
  254. #define RH_PS_PPS 0x00000100 /* port power status */
  255. #define RH_PS_LSDA 0x00000200 /* low speed device attached */
  256. #define RH_PS_CSC 0x00010000 /* connect status change */
  257. #define RH_PS_PESC 0x00020000 /* port enable status change */
  258. #define RH_PS_PSSC 0x00040000 /* port suspend status change */
  259. #define RH_PS_OCIC 0x00080000 /* over current indicator change */
  260. #define RH_PS_PRSC 0x00100000 /* port reset status change */
  261. /* roothub.status bits */
  262. #define RH_HS_LPS 0x00000001 /* local power status */
  263. #define RH_HS_OCI 0x00000002 /* over current indicator */
  264. #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
  265. #define RH_HS_LPSC 0x00010000 /* local power status change */
  266. #define RH_HS_OCIC 0x00020000 /* over current indicator change */
  267. #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
  268. /* roothub.b masks */
  269. #define RH_B_DR 0x0000ffff /* device removable flags */
  270. #define RH_B_PPCM 0xffff0000 /* port power control mask */
  271. /* roothub.a masks */
  272. #define RH_A_NDP (0xff << 0) /* number of downstream ports */
  273. #define RH_A_PSM (1 << 8) /* power switching mode */
  274. #define RH_A_NPS (1 << 9) /* no power switching */
  275. #define RH_A_DT (1 << 10) /* device type (mbz) */
  276. #define RH_A_OCPM (1 << 11) /* over current protection mode */
  277. #define RH_A_NOCP (1 << 12) /* no over current protection */
  278. #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
  279. /* urb */
  280. #define N_URB_TD 48
  281. typedef struct {
  282. ed_t *ed;
  283. __u16 length; /* number of tds associated with this request */
  284. __u16 td_cnt; /* number of tds already serviced */
  285. int state;
  286. unsigned long pipe;
  287. int actual_length;
  288. td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
  289. } urb_priv_t;
  290. #define URB_DEL 1
  291. /*
  292. * This is the full ohci controller description
  293. *
  294. * Note how the "proper" USB information is just
  295. * a subset of what the full implementation needs. (Linus)
  296. */
  297. typedef struct ohci {
  298. struct ohci_hcca *hcca; /* hcca */
  299. /*dma_addr_t hcca_dma; */
  300. int irq;
  301. int disabled; /* e.g. got a UE, we're hung */
  302. int sleeping;
  303. unsigned long flags; /* for HC bugs */
  304. struct ohci_regs *regs; /* OHCI controller's memory */
  305. ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
  306. ed_t *ed_bulktail; /* last endpoint of bulk list */
  307. ed_t *ed_controltail; /* last endpoint of control list */
  308. int intrstatus;
  309. __u32 hc_control; /* copy of the hc control reg */
  310. struct usb_device *dev[32];
  311. struct virt_root_hub rh;
  312. const char *slot_name;
  313. } ohci_t;
  314. #define NUM_EDS 8 /* num of preallocated endpoint descriptors */
  315. struct ohci_device {
  316. ed_t ed[NUM_EDS];
  317. int ed_cnt;
  318. };
  319. /* hcd */
  320. /* endpoint */
  321. static int ep_link(ohci_t * ohci, ed_t * ed);
  322. static int ep_unlink(ohci_t * ohci, ed_t * ed);
  323. static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
  324. /*-------------------------------------------------------------------------*/
  325. /* we need more TDs than EDs */
  326. #define NUM_TD 64
  327. /* +1 so we can align the storage */
  328. td_t gtd[NUM_TD + 1];
  329. /* pointers to aligned storage */
  330. td_t *ptd;
  331. /* TDs ... */
  332. static inline struct td *td_alloc(struct usb_device *usb_dev)
  333. {
  334. int i;
  335. struct td *td;
  336. td = NULL;
  337. for (i = 0; i < NUM_TD; i++) {
  338. if (ptd[i].usb_dev == NULL) {
  339. td = &ptd[i];
  340. td->usb_dev = usb_dev;
  341. break;
  342. }
  343. }
  344. return td;
  345. }
  346. static inline void ed_free(struct ed *ed)
  347. {
  348. ed->usb_dev = NULL;
  349. }