clock.c 3.8 KB

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  1. /*
  2. * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
  3. *
  4. * Copyright (C) 2011 Andreas Bießmann
  5. * Copyright (C) 2005 David Brownell
  6. * Copyright (C) 2005 Ivan Kokshaysky
  7. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <common.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/at91_pmc.h>
  18. #include <asm/arch/clk.h>
  19. #if !defined(CONFIG_AT91FAMILY)
  20. # error You need to define CONFIG_AT91FAMILY in your board config!
  21. #endif
  22. DECLARE_GLOBAL_DATA_PTR;
  23. static unsigned long at91_css_to_rate(unsigned long css)
  24. {
  25. switch (css) {
  26. case AT91_PMC_MCKR_CSS_SLOW:
  27. return CONFIG_SYS_AT91_SLOW_CLOCK;
  28. case AT91_PMC_MCKR_CSS_MAIN:
  29. return gd->main_clk_rate_hz;
  30. case AT91_PMC_MCKR_CSS_PLLA:
  31. return gd->plla_rate_hz;
  32. case AT91_PMC_MCKR_CSS_PLLB:
  33. return gd->pllb_rate_hz;
  34. }
  35. return 0;
  36. }
  37. #ifdef CONFIG_USB_ATMEL
  38. static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
  39. {
  40. unsigned i, div = 0, mul = 0, diff = 1 << 30;
  41. unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
  42. /* PLL output max 240 MHz (or 180 MHz per errata) */
  43. if (out_freq > 240000000)
  44. goto fail;
  45. for (i = 1; i < 256; i++) {
  46. int diff1;
  47. unsigned input, mul1;
  48. /*
  49. * PLL input between 1MHz and 32MHz per spec, but lower
  50. * frequences seem necessary in some cases so allow 100K.
  51. * Warning: some newer products need 2MHz min.
  52. */
  53. input = main_freq / i;
  54. if (input < 100000)
  55. continue;
  56. if (input > 32000000)
  57. continue;
  58. mul1 = out_freq / input;
  59. if (mul1 > 2048)
  60. continue;
  61. if (mul1 < 2)
  62. goto fail;
  63. diff1 = out_freq - input * mul1;
  64. if (diff1 < 0)
  65. diff1 = -diff1;
  66. if (diff > diff1) {
  67. diff = diff1;
  68. div = i;
  69. mul = mul1;
  70. if (diff == 0)
  71. break;
  72. }
  73. }
  74. if (i == 256 && diff > (out_freq >> 5))
  75. goto fail;
  76. return ret | ((mul - 1) << 16) | div;
  77. fail:
  78. return 0;
  79. }
  80. #endif
  81. static u32 at91_pll_rate(u32 freq, u32 reg)
  82. {
  83. unsigned mul, div;
  84. div = reg & 0xff;
  85. mul = (reg >> 16) & 0x7ff;
  86. if (div && mul) {
  87. freq /= div;
  88. freq *= mul + 1;
  89. } else
  90. freq = 0;
  91. return freq;
  92. }
  93. int at91_clock_init(unsigned long main_clock)
  94. {
  95. unsigned freq, mckr;
  96. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  97. #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
  98. unsigned tmp;
  99. /*
  100. * When the bootloader initialized the main oscillator correctly,
  101. * there's no problem using the cycle counter. But if it didn't,
  102. * or when using oscillator bypass mode, we must be told the speed
  103. * of the main clock.
  104. */
  105. if (!main_clock) {
  106. do {
  107. tmp = readl(&pmc->mcfr);
  108. } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
  109. tmp &= AT91_PMC_MCFR_MAINF_MASK;
  110. main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
  111. }
  112. #endif
  113. gd->main_clk_rate_hz = main_clock;
  114. /* report if PLLA is more than mildly overclocked */
  115. gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
  116. #ifdef CONFIG_USB_ATMEL
  117. /*
  118. * USB clock init: choose 48 MHz PLLB value,
  119. * disable 48MHz clock during usb peripheral suspend.
  120. *
  121. * REVISIT: assumes MCK doesn't derive from PLLB!
  122. */
  123. gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
  124. AT91_PMC_PLLBR_USBDIV_2;
  125. gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
  126. #endif
  127. /*
  128. * MCK and CPU derive from one of those primary clocks.
  129. * For now, assume this parentage won't change.
  130. */
  131. mckr = readl(&pmc->mckr);
  132. gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
  133. freq = gd->mck_rate_hz;
  134. freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
  135. /* mdiv */
  136. gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
  137. gd->cpu_clk_rate_hz = freq;
  138. return 0;
  139. }