tegra210_qspi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NVIDIA Tegra210 QSPI controller driver
  4. *
  5. * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
  6. *
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <time.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch-tegra/clk_rst.h>
  16. #include <spi.h>
  17. #include <fdtdec.h>
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. #include "tegra_spi.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /* COMMAND1 */
  23. #define QSPI_CMD1_GO BIT(31)
  24. #define QSPI_CMD1_M_S BIT(30)
  25. #define QSPI_CMD1_MODE_MASK GENMASK(1,0)
  26. #define QSPI_CMD1_MODE_SHIFT 28
  27. #define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0)
  28. #define QSPI_CMD1_CS_SEL_SHIFT 26
  29. #define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22)
  30. #define QSPI_CMD1_CS_SW_HW BIT(21)
  31. #define QSPI_CMD1_CS_SW_VAL BIT(20)
  32. #define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0)
  33. #define QSPI_CMD1_IDLE_SDA_SHIFT 18
  34. #define QSPI_CMD1_BIDIR BIT(17)
  35. #define QSPI_CMD1_LSBI_FE BIT(16)
  36. #define QSPI_CMD1_LSBY_FE BIT(15)
  37. #define QSPI_CMD1_BOTH_EN_BIT BIT(14)
  38. #define QSPI_CMD1_BOTH_EN_BYTE BIT(13)
  39. #define QSPI_CMD1_RX_EN BIT(12)
  40. #define QSPI_CMD1_TX_EN BIT(11)
  41. #define QSPI_CMD1_PACKED BIT(5)
  42. #define QSPI_CMD1_BITLEN_MASK GENMASK(4,0)
  43. #define QSPI_CMD1_BITLEN_SHIFT 0
  44. /* COMMAND2 */
  45. #define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
  46. #define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10)
  47. #define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
  48. #define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0)
  49. /* TRANSFER STATUS */
  50. #define QSPI_XFER_STS_RDY BIT(30)
  51. /* FIFO STATUS */
  52. #define QSPI_FIFO_STS_CS_INACTIVE BIT(31)
  53. #define QSPI_FIFO_STS_FRAME_END BIT(30)
  54. #define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
  55. #define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
  56. #define QSPI_FIFO_STS_ERR BIT(8)
  57. #define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7)
  58. #define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6)
  59. #define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5)
  60. #define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4)
  61. #define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3)
  62. #define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
  63. #define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1)
  64. #define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
  65. #define QSPI_TIMEOUT 1000
  66. struct qspi_regs {
  67. u32 command1; /* 000:QSPI_COMMAND1 register */
  68. u32 command2; /* 004:QSPI_COMMAND2 register */
  69. u32 timing1; /* 008:QSPI_CS_TIM1 register */
  70. u32 timing2; /* 00c:QSPI_CS_TIM2 register */
  71. u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
  72. u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
  73. u32 tx_data; /* 018:QSPI_TX_DATA register */
  74. u32 rx_data; /* 01c:QSPI_RX_DATA register */
  75. u32 dma_ctl; /* 020:QSPI_DMA_CTL register */
  76. u32 dma_blk; /* 024:QSPI_DMA_BLK register */
  77. u32 rsvd[56]; /* 028-107 reserved */
  78. u32 tx_fifo; /* 108:QSPI_FIFO1 register */
  79. u32 rsvd2[31]; /* 10c-187 reserved */
  80. u32 rx_fifo; /* 188:QSPI_FIFO2 register */
  81. u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */
  82. };
  83. struct tegra210_qspi_priv {
  84. struct qspi_regs *regs;
  85. unsigned int freq;
  86. unsigned int mode;
  87. int periph_id;
  88. int valid;
  89. int last_transaction_us;
  90. };
  91. static int tegra210_qspi_of_to_plat(struct udevice *bus)
  92. {
  93. struct tegra_spi_plat *plat = dev_get_plat(bus);
  94. plat->base = dev_read_addr(bus);
  95. plat->periph_id = clock_decode_periph_id(bus);
  96. if (plat->periph_id == PERIPH_ID_NONE) {
  97. debug("%s: could not decode periph id %d\n", __func__,
  98. plat->periph_id);
  99. return -FDT_ERR_NOTFOUND;
  100. }
  101. /* Use 500KHz as a suitable default */
  102. plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
  103. 500000);
  104. plat->deactivate_delay_us = dev_read_u32_default(bus,
  105. "spi-deactivate-delay",
  106. 0);
  107. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  108. __func__, plat->base, plat->periph_id, plat->frequency,
  109. plat->deactivate_delay_us);
  110. return 0;
  111. }
  112. static int tegra210_qspi_probe(struct udevice *bus)
  113. {
  114. struct tegra_spi_plat *plat = dev_get_plat(bus);
  115. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  116. priv->regs = (struct qspi_regs *)plat->base;
  117. struct qspi_regs *regs = priv->regs;
  118. priv->last_transaction_us = timer_get_us();
  119. priv->freq = plat->frequency;
  120. priv->periph_id = plat->periph_id;
  121. debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
  122. priv->periph_id);
  123. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  124. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
  125. /* Set tap delays here, clock change above resets QSPI controller */
  126. u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
  127. (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
  128. writel(reg, &regs->command2);
  129. debug("%s: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
  130. return 0;
  131. }
  132. static int tegra210_qspi_claim_bus(struct udevice *dev)
  133. {
  134. struct udevice *bus = dev->parent;
  135. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  136. struct qspi_regs *regs = priv->regs;
  137. debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
  138. /* Set master mode and sw controlled CS */
  139. setbits_le32(&regs->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW |
  140. (priv->mode << QSPI_CMD1_MODE_SHIFT));
  141. debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
  142. return 0;
  143. }
  144. /**
  145. * Activate the CS by driving it LOW
  146. *
  147. * @param slave Pointer to spi_slave to which controller has to
  148. * communicate with
  149. */
  150. static void spi_cs_activate(struct udevice *dev)
  151. {
  152. struct udevice *bus = dev->parent;
  153. struct tegra_spi_plat *pdata = dev_get_plat(bus);
  154. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  155. /* If it's too soon to do another transaction, wait */
  156. if (pdata->deactivate_delay_us &&
  157. priv->last_transaction_us) {
  158. ulong delay_us; /* The delay completed so far */
  159. delay_us = timer_get_us() - priv->last_transaction_us;
  160. if (delay_us < pdata->deactivate_delay_us)
  161. udelay(pdata->deactivate_delay_us - delay_us);
  162. }
  163. clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
  164. }
  165. /**
  166. * Deactivate the CS by driving it HIGH
  167. *
  168. * @param slave Pointer to spi_slave to which controller has to
  169. * communicate with
  170. */
  171. static void spi_cs_deactivate(struct udevice *dev)
  172. {
  173. struct udevice *bus = dev->parent;
  174. struct tegra_spi_plat *pdata = dev_get_plat(bus);
  175. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  176. setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
  177. /* Remember time of this transaction so we can honour the bus delay */
  178. if (pdata->deactivate_delay_us)
  179. priv->last_transaction_us = timer_get_us();
  180. debug("Deactivate CS, bus '%s'\n", bus->name);
  181. }
  182. static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  183. const void *data_out, void *data_in,
  184. unsigned long flags)
  185. {
  186. struct udevice *bus = dev->parent;
  187. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  188. struct qspi_regs *regs = priv->regs;
  189. u32 reg, tmpdout, tmpdin = 0;
  190. const u8 *dout = data_out;
  191. u8 *din = data_in;
  192. int num_bytes, tm, ret;
  193. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  194. __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen);
  195. if (bitlen % 8)
  196. return -1;
  197. num_bytes = bitlen / 8;
  198. ret = 0;
  199. /* clear all error status bits */
  200. reg = readl(&regs->fifo_status);
  201. writel(reg, &regs->fifo_status);
  202. /* flush RX/TX FIFOs */
  203. setbits_le32(&regs->fifo_status,
  204. (QSPI_FIFO_STS_RX_FIFO_FLUSH |
  205. QSPI_FIFO_STS_TX_FIFO_FLUSH));
  206. tm = QSPI_TIMEOUT;
  207. while ((tm && readl(&regs->fifo_status) &
  208. (QSPI_FIFO_STS_RX_FIFO_FLUSH |
  209. QSPI_FIFO_STS_TX_FIFO_FLUSH))) {
  210. tm--;
  211. udelay(1);
  212. }
  213. if (!tm) {
  214. printf("%s: timeout during QSPI FIFO flush!\n",
  215. __func__);
  216. return -1;
  217. }
  218. /*
  219. * Notes:
  220. * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs;
  221. * 2. don't set RX_EN and TX_EN yet.
  222. * (SW needs to make sure that while programming the blk_size,
  223. * tx_en and rx_en bits must be zero)
  224. * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set
  225. * i.e., both dout and din are not NULL.
  226. */
  227. clrsetbits_le32(&regs->command1,
  228. (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE |
  229. QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN),
  230. (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT));
  231. /* set xfer size to 1 block (32 bits) */
  232. writel(0, &regs->dma_blk);
  233. if (flags & SPI_XFER_BEGIN)
  234. spi_cs_activate(dev);
  235. /* handle data in 32-bit chunks */
  236. while (num_bytes > 0) {
  237. int bytes;
  238. tmpdout = 0;
  239. bytes = (num_bytes > 4) ? 4 : num_bytes;
  240. if (dout != NULL) {
  241. memcpy((void *)&tmpdout, (void *)dout, bytes);
  242. dout += bytes;
  243. num_bytes -= bytes;
  244. writel(tmpdout, &regs->tx_fifo);
  245. setbits_le32(&regs->command1, QSPI_CMD1_TX_EN);
  246. }
  247. if (din != NULL)
  248. setbits_le32(&regs->command1, QSPI_CMD1_RX_EN);
  249. /* clear ready bit */
  250. setbits_le32(&regs->xfer_status, QSPI_XFER_STS_RDY);
  251. clrsetbits_le32(&regs->command1,
  252. QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT,
  253. (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT);
  254. /* Need to stabilize other reg bits before GO bit set.
  255. * As per the TRM:
  256. * "For successful operation at various freq combinations,
  257. * a minimum of 4-5 spi_clk cycle delay might be required
  258. * before enabling the PIO or DMA bits. The worst case delay
  259. * calculation can be done considering slowest qspi_clk as
  260. * 1MHz. Based on that 1us delay should be enough before
  261. * enabling PIO or DMA." Padded another 1us for safety.
  262. */
  263. udelay(2);
  264. setbits_le32(&regs->command1, QSPI_CMD1_GO);
  265. udelay(1);
  266. /*
  267. * Wait for SPI transmit FIFO to empty, or to time out.
  268. * The RX FIFO status will be read and cleared last
  269. */
  270. for (tm = 0; tm < QSPI_TIMEOUT; ++tm) {
  271. u32 fifo_status, xfer_status;
  272. xfer_status = readl(&regs->xfer_status);
  273. if (!(xfer_status & QSPI_XFER_STS_RDY))
  274. continue;
  275. fifo_status = readl(&regs->fifo_status);
  276. if (fifo_status & QSPI_FIFO_STS_ERR) {
  277. debug("%s: got a fifo error: ", __func__);
  278. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF)
  279. debug("tx FIFO overflow ");
  280. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR)
  281. debug("tx FIFO underrun ");
  282. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF)
  283. debug("rx FIFO overflow ");
  284. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR)
  285. debug("rx FIFO underrun ");
  286. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL)
  287. debug("tx FIFO full ");
  288. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY)
  289. debug("tx FIFO empty ");
  290. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL)
  291. debug("rx FIFO full ");
  292. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)
  293. debug("rx FIFO empty ");
  294. debug("\n");
  295. break;
  296. }
  297. if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) {
  298. tmpdin = readl(&regs->rx_fifo);
  299. if (din != NULL) {
  300. memcpy(din, &tmpdin, bytes);
  301. din += bytes;
  302. num_bytes -= bytes;
  303. }
  304. }
  305. break;
  306. }
  307. if (tm >= QSPI_TIMEOUT)
  308. ret = tm;
  309. /* clear ACK RDY, etc. bits */
  310. writel(readl(&regs->fifo_status), &regs->fifo_status);
  311. }
  312. if (flags & SPI_XFER_END)
  313. spi_cs_deactivate(dev);
  314. debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
  315. __func__, tmpdin, readl(&regs->fifo_status));
  316. if (ret) {
  317. printf("%s: timeout during SPI transfer, tm %d\n",
  318. __func__, ret);
  319. return -1;
  320. }
  321. return ret;
  322. }
  323. static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
  324. {
  325. struct tegra_spi_plat *plat = dev_get_plat(bus);
  326. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  327. if (speed > plat->frequency)
  328. speed = plat->frequency;
  329. priv->freq = speed;
  330. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  331. return 0;
  332. }
  333. static int tegra210_qspi_set_mode(struct udevice *bus, uint mode)
  334. {
  335. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  336. priv->mode = mode;
  337. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  338. return 0;
  339. }
  340. static const struct dm_spi_ops tegra210_qspi_ops = {
  341. .claim_bus = tegra210_qspi_claim_bus,
  342. .xfer = tegra210_qspi_xfer,
  343. .set_speed = tegra210_qspi_set_speed,
  344. .set_mode = tegra210_qspi_set_mode,
  345. /*
  346. * cs_info is not needed, since we require all chip selects to be
  347. * in the device tree explicitly
  348. */
  349. };
  350. static const struct udevice_id tegra210_qspi_ids[] = {
  351. { .compatible = "nvidia,tegra210-qspi" },
  352. { }
  353. };
  354. U_BOOT_DRIVER(tegra210_qspi) = {
  355. .name = "tegra210-qspi",
  356. .id = UCLASS_SPI,
  357. .of_match = tegra210_qspi_ids,
  358. .ops = &tegra210_qspi_ops,
  359. .of_to_plat = tegra210_qspi_of_to_plat,
  360. .plat_auto = sizeof(struct tegra_spi_plat),
  361. .priv_auto = sizeof(struct tegra210_qspi_priv),
  362. .per_child_auto = sizeof(struct spi_slave),
  363. .probe = tegra210_qspi_probe,
  364. };