ksz9477.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2020
  4. * Tim Harvey, Gateworks Corporation
  5. */
  6. #include <dm.h>
  7. #include <dm/device_compat.h>
  8. #include <dm/device-internal.h>
  9. #include <dm/lists.h>
  10. #include <eth_phy.h>
  11. #include <linux/delay.h>
  12. #include <miiphy.h>
  13. #include <i2c.h>
  14. #include <net/dsa.h>
  15. #include <asm-generic/gpio.h>
  16. /* Global registers */
  17. /* Chip ID */
  18. #define REG_CHIP_ID0__1 0x0000
  19. /* Operation control */
  20. #define REG_SW_OPERATION 0x0300
  21. #define SW_RESET BIT(1)
  22. #define SW_START BIT(0)
  23. /* Port Specific Registers */
  24. #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
  25. /* Port Control */
  26. #define REG_PORT_XMII_CTRL_1 0x0301
  27. #define PORT_MII_NOT_1GBIT BIT(6)
  28. #define PORT_MII_SEL_EDGE BIT(5)
  29. #define PORT_RGMII_ID_IG_ENABLE BIT(4)
  30. #define PORT_RGMII_ID_EG_ENABLE BIT(3)
  31. #define PORT_MII_MAC_MODE BIT(2)
  32. #define PORT_MII_SEL_M 0x3
  33. #define PORT_RGMII_SEL 0x0
  34. #define PORT_RMII_SEL 0x1
  35. #define PORT_GMII_SEL 0x2
  36. #define PORT_MII_SEL 0x3
  37. /* Port MSTP State Register */
  38. #define REG_PORT_MSTP_STATE 0x0b04
  39. #define PORT_TX_ENABLE BIT(2)
  40. #define PORT_RX_ENABLE BIT(1)
  41. #define PORT_LEARN_DISABLE BIT(0)
  42. /* MMD */
  43. #define REG_PORT_PHY_MMD_SETUP 0x011A
  44. #define PORT_MMD_OP_MODE_M 0x3
  45. #define PORT_MMD_OP_MODE_S 14
  46. #define PORT_MMD_OP_INDEX 0
  47. #define PORT_MMD_OP_DATA_NO_INCR 1
  48. #define PORT_MMD_OP_DATA_INCR_RW 2
  49. #define PORT_MMD_OP_DATA_INCR_W 3
  50. #define PORT_MMD_DEVICE_ID_M 0x1F
  51. #define MMD_SETUP(mode, dev) (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))
  52. #define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
  53. struct ksz_dsa_priv {
  54. struct udevice *dev;
  55. int active_port;
  56. };
  57. static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val)
  58. {
  59. int ret = dm_i2c_read(dev, reg, val, 1);
  60. dev_dbg(dev, "%s 0x%04x<<0x%02x\n", __func__, reg, *val);
  61. return ret;
  62. }
  63. static inline int ksz_pread8(struct udevice *dev, int port, int reg, u8 *val)
  64. {
  65. return ksz_read8(dev, PORT_CTRL_ADDR(port, reg), val);
  66. }
  67. static inline int ksz_write8(struct udevice *dev, u32 reg, u8 val)
  68. {
  69. dev_dbg(dev, "%s 0x%04x>>0x%02x\n", __func__, reg, val);
  70. return dm_i2c_write(dev, reg, &val, 1);
  71. }
  72. static inline int ksz_pwrite8(struct udevice *dev, int port, int reg, u8 val)
  73. {
  74. return ksz_write8(dev, PORT_CTRL_ADDR(port, reg), val);
  75. }
  76. static inline int ksz_write16(struct udevice *dev, u32 reg, u16 val)
  77. {
  78. u8 buf[2];
  79. buf[1] = val & 0xff;
  80. buf[0] = val >> 8;
  81. dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
  82. return dm_i2c_write(dev, reg, buf, 2);
  83. }
  84. static inline int ksz_pwrite16(struct udevice *dev, int port, int reg, u16 val)
  85. {
  86. return ksz_write16(dev, PORT_CTRL_ADDR(port, reg), val);
  87. }
  88. static inline int ksz_read16(struct udevice *dev, u32 reg, u16 *val)
  89. {
  90. u8 buf[2];
  91. int ret;
  92. ret = dm_i2c_read(dev, reg, buf, 2);
  93. *val = (buf[0] << 8) | buf[1];
  94. dev_dbg(dev, "%s 0x%04x<<0x%04x\n", __func__, reg, *val);
  95. return ret;
  96. }
  97. static inline int ksz_pread16(struct udevice *dev, int port, int reg, u16 *val)
  98. {
  99. return ksz_read16(dev, PORT_CTRL_ADDR(port, reg), val);
  100. }
  101. static inline int ksz_read32(struct udevice *dev, u32 reg, u32 *val)
  102. {
  103. return dm_i2c_read(dev, reg, (u8 *)val, 4);
  104. }
  105. static inline int ksz_pread32(struct udevice *dev, int port, int reg, u32 *val)
  106. {
  107. return ksz_read32(dev, PORT_CTRL_ADDR(port, reg), val);
  108. }
  109. static inline int ksz_write32(struct udevice *dev, u32 reg, u32 val)
  110. {
  111. u8 buf[4];
  112. buf[3] = val & 0xff;
  113. buf[2] = (val >> 24) & 0xff;
  114. buf[1] = (val >> 16) & 0xff;
  115. buf[0] = (val >> 8) & 0xff;
  116. dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
  117. return dm_i2c_write(dev, reg, buf, 4);
  118. }
  119. static inline int ksz_pwrite32(struct udevice *dev, int port, int reg, u32 val)
  120. {
  121. return ksz_write32(dev, PORT_CTRL_ADDR(port, reg), val);
  122. }
  123. static __maybe_unused void ksz_port_mmd_read(struct udevice *dev, int port,
  124. u8 addr, u16 reg, u16 *val)
  125. {
  126. ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_INDEX, addr));
  127. ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg);
  128. ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, addr));
  129. ksz_pread16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
  130. dev_dbg(dev, "%s P%d 0x%02x:0x%04x<<0x%04x\n", __func__, port + 1, addr, reg, *val);
  131. }
  132. static void ksz_port_mmd_write(struct udevice *dev, int port, u8 addr, u16 reg, u16 val)
  133. {
  134. dev_dbg(dev, "%s P%d 0x%02x:0x%04x>>0x%04x\n", __func__, port + 1, addr, addr, val);
  135. ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_INDEX, addr));
  136. ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, addr);
  137. ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, addr));
  138. ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
  139. }
  140. /* Apply PHY settings to address errata listed in KSZ9477, KSZ9897, KSZ9896, KSZ9567
  141. * Silicon Errata and Data Sheet Clarification documents
  142. */
  143. static void ksz_phy_errata_setup(struct udevice *dev, int port)
  144. {
  145. dev_dbg(dev, "%s P%d\n", __func__, port + 1);
  146. /* Register settings are needed to improve PHY receive performance */
  147. ksz_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
  148. ksz_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
  149. ksz_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
  150. ksz_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
  151. ksz_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
  152. ksz_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
  153. ksz_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
  154. /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
  155. ksz_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
  156. /* Energy Efficient Ethernet (EEE) feature select must be manually disabled */
  157. ksz_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
  158. /* Register settings are required to meet data sheet supply current specifications */
  159. ksz_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
  160. ksz_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
  161. ksz_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
  162. ksz_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
  163. ksz_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
  164. ksz_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
  165. ksz_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
  166. ksz_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
  167. ksz_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
  168. ksz_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
  169. ksz_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
  170. ksz_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
  171. ksz_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
  172. }
  173. /*
  174. * mii bus driver
  175. */
  176. #define KSZ_MDIO_CHILD_DRV_NAME "ksz_mdio"
  177. struct ksz_mdio_priv {
  178. struct ksz_dsa_priv *ksz;
  179. };
  180. static int dm_ksz_mdio_read(struct udevice *dev, int addr, int devad, int reg)
  181. {
  182. struct ksz_mdio_priv *priv = dev_get_priv(dev);
  183. struct ksz_dsa_priv *ksz = priv->ksz;
  184. u16 val = 0xffff;
  185. ksz_pread16(ksz->dev, addr, 0x100 + (reg << 1), &val);
  186. dev_dbg(ksz->dev, "%s P%d reg=0x%04x:0x%04x<<0x%04x\n", __func__,
  187. addr + 1, reg, 0x100 + (reg << 1), val);
  188. return val;
  189. };
  190. static int dm_ksz_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val)
  191. {
  192. struct ksz_mdio_priv *priv = dev_get_priv(dev);
  193. struct ksz_dsa_priv *ksz = priv->ksz;
  194. dev_dbg(ksz->dev, "%s P%d reg=0x%04x:%04x>>0x%04x\n",
  195. __func__, addr + 1, reg, 0x100 + (reg << 1), val);
  196. ksz_pwrite16(ksz->dev, addr, 0x100 + (reg << 1), val);
  197. return 0;
  198. }
  199. static const struct mdio_ops ksz_mdio_ops = {
  200. .read = dm_ksz_mdio_read,
  201. .write = dm_ksz_mdio_write,
  202. };
  203. static int ksz_mdio_bind(struct udevice *dev)
  204. {
  205. char name[16];
  206. static int num_devices;
  207. dev_dbg(dev, "%s\n", __func__);
  208. sprintf(name, "ksz-mdio-%d", num_devices++);
  209. device_set_name(dev, name);
  210. return 0;
  211. }
  212. static int ksz_mdio_probe(struct udevice *dev)
  213. {
  214. struct ksz_mdio_priv *priv = dev_get_priv(dev);
  215. dev_dbg(dev, "%s\n", __func__);
  216. priv->ksz = dev_get_parent_priv(dev->parent);
  217. return 0;
  218. }
  219. static const struct udevice_id ksz_mdio_ids[] = {
  220. { .compatible = "microchip,ksz-mdio" },
  221. { }
  222. };
  223. U_BOOT_DRIVER(ksz_mdio) = {
  224. .name = KSZ_MDIO_CHILD_DRV_NAME,
  225. .id = UCLASS_MDIO,
  226. .of_match = ksz_mdio_ids,
  227. .bind = ksz_mdio_bind,
  228. .probe = ksz_mdio_probe,
  229. .ops = &ksz_mdio_ops,
  230. .priv_auto = sizeof(struct ksz_mdio_priv),
  231. .plat_auto = sizeof(struct mdio_perdev_priv),
  232. };
  233. static int ksz_port_setup(struct udevice *dev, int port,
  234. phy_interface_t interface)
  235. {
  236. struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
  237. u8 data8;
  238. dev_dbg(dev, "%s P%d %s\n", __func__, port + 1,
  239. (port == pdata->cpu_port) ? "cpu" : "");
  240. if (port != pdata->cpu_port) {
  241. /* phy port: config errata and leds */
  242. ksz_phy_errata_setup(dev, port);
  243. } else {
  244. /* cpu port: configure MAC interface mode */
  245. ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
  246. dev_dbg(dev, "%s P%d cpu interface %s\n", __func__, port + 1,
  247. phy_string_for_interface(interface));
  248. switch (interface) {
  249. case PHY_INTERFACE_MODE_MII:
  250. data8 &= ~PORT_MII_SEL_M;
  251. data8 |= PORT_MII_SEL;
  252. data8 |= PORT_MII_NOT_1GBIT;
  253. break;
  254. case PHY_INTERFACE_MODE_RMII:
  255. data8 &= ~PORT_MII_SEL_M;
  256. data8 |= PORT_RMII_SEL;
  257. data8 |= PORT_MII_NOT_1GBIT;
  258. break;
  259. case PHY_INTERFACE_MODE_GMII:
  260. data8 &= ~PORT_MII_SEL_M;
  261. data8 |= PORT_GMII_SEL;
  262. data8 &= ~PORT_MII_NOT_1GBIT;
  263. break;
  264. default:
  265. data8 &= ~PORT_MII_SEL_M;
  266. data8 |= PORT_RGMII_SEL;
  267. data8 &= ~PORT_MII_NOT_1GBIT;
  268. data8 &= ~PORT_RGMII_ID_IG_ENABLE;
  269. data8 &= ~PORT_RGMII_ID_EG_ENABLE;
  270. if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
  271. interface == PHY_INTERFACE_MODE_RGMII_RXID)
  272. data8 |= PORT_RGMII_ID_IG_ENABLE;
  273. if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
  274. interface == PHY_INTERFACE_MODE_RGMII_TXID)
  275. data8 |= PORT_RGMII_ID_EG_ENABLE;
  276. break;
  277. }
  278. ksz_write8(dev, PORT_CTRL_ADDR(port, REG_PORT_XMII_CTRL_1), data8);
  279. }
  280. return 0;
  281. }
  282. static int ksz_port_enable(struct udevice *dev, int port, struct phy_device *phy)
  283. {
  284. struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
  285. struct ksz_dsa_priv *priv = dev_get_priv(dev);
  286. int supported = PHY_GBIT_FEATURES;
  287. u8 data8;
  288. int ret;
  289. dev_dbg(dev, "%s P%d 0x%x %s\n", __func__, port + 1, phy->phy_id,
  290. phy_string_for_interface(phy->interface));
  291. /* setup this port */
  292. ret = ksz_port_setup(dev, port, phy->interface);
  293. if (ret) {
  294. dev_err(dev, "port setup failed: %d\n", ret);
  295. return ret;
  296. }
  297. /* enable port forwarding for this port */
  298. ksz_pread8(priv->dev, port, REG_PORT_MSTP_STATE, &data8);
  299. data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
  300. data8 |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
  301. ksz_pwrite8(priv->dev, port, REG_PORT_MSTP_STATE, data8);
  302. /* if cpu master we are done */
  303. if (port == pdata->cpu_port)
  304. return 0;
  305. /* configure phy */
  306. phy->supported &= supported;
  307. phy->advertising &= supported;
  308. ret = phy_config(phy);
  309. if (ret)
  310. return ret;
  311. ret = phy_startup(phy);
  312. if (ret)
  313. return ret;
  314. /* start switch */
  315. ksz_read8(priv->dev, REG_SW_OPERATION, &data8);
  316. data8 |= SW_START;
  317. ksz_write8(priv->dev, REG_SW_OPERATION, data8);
  318. /* keep track of current enabled non-cpu port */
  319. priv->active_port = port;
  320. return 0;
  321. }
  322. static void ksz_port_disable(struct udevice *dev, int port, struct phy_device *phy)
  323. {
  324. struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
  325. struct ksz_dsa_priv *priv = dev_get_priv(dev);
  326. u8 data8;
  327. dev_dbg(dev, "%s P%d 0x%x\n", __func__, port + 1, phy->phy_id);
  328. /* can't disable CPU port without re-configuring/re-starting switch */
  329. if (port == pdata->cpu_port)
  330. return;
  331. /* disable port */
  332. ksz_pread8(priv->dev, port, REG_PORT_MSTP_STATE, &data8);
  333. data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
  334. data8 |= PORT_LEARN_DISABLE;
  335. ksz_pwrite8(priv->dev, port, REG_PORT_MSTP_STATE, data8);
  336. /*
  337. * we don't call phy_shutdown here to avoid waiting next time we use
  338. * the port, but the downside is that remote side will think we're
  339. * actively processing traffic although we are not.
  340. */
  341. }
  342. static int ksz_xmit(struct udevice *dev, int port, void *packet, int length)
  343. {
  344. dev_dbg(dev, "%s P%d %d\n", __func__, port + 1, length);
  345. return 0;
  346. }
  347. static int ksz_recv(struct udevice *dev, int *port, void *packet, int length)
  348. {
  349. struct ksz_dsa_priv *priv = dev_get_priv(dev);
  350. dev_dbg(dev, "%s P%d %d\n", __func__, priv->active_port + 1, length);
  351. *port = priv->active_port;
  352. return 0;
  353. };
  354. static const struct dsa_ops ksz_dsa_ops = {
  355. .port_enable = ksz_port_enable,
  356. .port_disable = ksz_port_disable,
  357. .xmit = ksz_xmit,
  358. .rcv = ksz_recv,
  359. };
  360. static int ksz_probe_mdio(struct udevice *dev)
  361. {
  362. ofnode node, mdios;
  363. int ret;
  364. mdios = dev_read_subnode(dev, "mdios");
  365. if (ofnode_valid(mdios)) {
  366. ofnode_for_each_subnode(node, mdios) {
  367. const char *name = ofnode_get_name(node);
  368. struct udevice *pdev;
  369. ret = device_bind_driver_to_node(dev,
  370. KSZ_MDIO_CHILD_DRV_NAME,
  371. name, node, &pdev);
  372. if (ret)
  373. dev_err(dev, "failed to probe %s: %d\n", name, ret);
  374. }
  375. }
  376. return 0;
  377. }
  378. /*
  379. * I2C driver
  380. */
  381. static int ksz_i2c_probe(struct udevice *dev)
  382. {
  383. struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
  384. struct ksz_dsa_priv *priv = dev_get_priv(dev);
  385. struct udevice *master = dsa_get_master(dev);
  386. int i, ret;
  387. u8 data8;
  388. u32 id;
  389. if (!master)
  390. return -ENODEV;
  391. dev_dbg(dev, "%s %s master:%s\n", __func__, dev->name, master->name);
  392. dev_set_parent_priv(dev, priv);
  393. ret = i2c_set_chip_offset_len(dev, 2);
  394. if (ret) {
  395. printf("i2c_set_chip_offset_len failed: %d\n", ret);
  396. return ret;
  397. }
  398. /* default config */
  399. priv->dev = dev;
  400. /* chip level reset */
  401. ksz_read8(priv->dev, REG_SW_OPERATION, &data8);
  402. data8 |= SW_RESET;
  403. ksz_write8(priv->dev, REG_SW_OPERATION, data8);
  404. /* read chip id */
  405. ret = ksz_read32(dev, REG_CHIP_ID0__1, &id);
  406. if (ret)
  407. return ret;
  408. id = __swab32(id);
  409. dev_dbg(dev, "%s id=0x%08x\n", __func__, id);
  410. switch (id & 0xffffff00) {
  411. case 0x00947700:
  412. puts("KSZ9477S: ");
  413. break;
  414. case 0x00956700:
  415. puts("KSZ9567R: ");
  416. break;
  417. case 0x00989700:
  418. puts("KSZ9897S: ");
  419. break;
  420. default:
  421. dev_err(dev, "invalid chip id: 0x%08x\n", id);
  422. return -EINVAL;
  423. }
  424. /* probe mdio bus */
  425. ret = ksz_probe_mdio(dev);
  426. if (ret)
  427. return ret;
  428. /* disable ports by default */
  429. for (i = 0; i < pdata->num_ports; i++) {
  430. ksz_pread8(priv->dev, i, REG_PORT_MSTP_STATE, &data8);
  431. data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
  432. ksz_pwrite8(priv->dev, i, REG_PORT_MSTP_STATE, data8);
  433. }
  434. dsa_set_tagging(dev, 0, 0);
  435. return 0;
  436. };
  437. static const struct udevice_id ksz_i2c_ids[] = {
  438. { .compatible = "microchip,ksz9897" },
  439. { .compatible = "microchip,ksz9477" },
  440. { .compatible = "microchip,ksz9567" },
  441. { }
  442. };
  443. U_BOOT_DRIVER(ksz) = {
  444. .name = "ksz-switch",
  445. .id = UCLASS_DSA,
  446. .of_match = ksz_i2c_ids,
  447. .probe = ksz_i2c_probe,
  448. .ops = &ksz_dsa_ops,
  449. .priv_auto = sizeof(struct ksz_dsa_priv),
  450. };