pg-wcom-ls102xa.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2020 Hitachi Power Grids. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/immap_ls102xa.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <asm/arch/ls102xa_devdis.h>
  12. #include <asm/arch/ls102xa_soc.h>
  13. #include <hwconfig.h>
  14. #include <mmc.h>
  15. #include <fsl_csu.h>
  16. #include <fsl_esdhc.h>
  17. #include <fsl_ifc.h>
  18. #include <fsl_immap.h>
  19. #include <netdev.h>
  20. #include <fsl_mdio.h>
  21. #include <tsec.h>
  22. #include <fsl_sec.h>
  23. #include <fsl_devdis.h>
  24. #include <fsl_ddr.h>
  25. #include <spl.h>
  26. #include <fdt_support.h>
  27. #include <fsl_qe.h>
  28. #include <fsl_validate.h>
  29. #include "../common/common.h"
  30. #include "../common/qrio.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  33. int checkboard(void)
  34. {
  35. show_qrio();
  36. return 0;
  37. }
  38. int dram_init(void)
  39. {
  40. return fsl_initdram();
  41. }
  42. int board_early_init_f(void)
  43. {
  44. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  45. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  46. struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  47. /* Disable unused MCK1 */
  48. setbits_be32(&gur->ddrclkdr, 2);
  49. /* IFC Global Configuration */
  50. setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  51. setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) |
  52. IFC_CCR_INV_CLK_EN);
  53. /* clear BD & FR bits for BE BD's and frame data */
  54. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  55. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  56. init_early_memctl_regs();
  57. /* QRIO Configuration */
  58. qrio_uprstreq(UPREQ_CORE_RST);
  59. #if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8)
  60. qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
  61. qrio_wdmask(KM_LIU_RST, true);
  62. qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
  63. qrio_wdmask(KM_PAXK_RST, true);
  64. #endif
  65. #if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1)
  66. qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST);
  67. qrio_wdmask(WCOM_TMG_RST, true);
  68. qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
  69. qrio_prst(WCOM_PHY_RST, false, false);
  70. qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST);
  71. qrio_wdmask(WCOM_QSFP_RST, true);
  72. qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
  73. qrio_prst(WCOM_CLIPS_RST, false, false);
  74. #endif
  75. qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  76. qrio_prst(KM_DBG_ETH_RST, false, false);
  77. i2c_deblock_gpio_cfg();
  78. /* enable the Unit LED (red) & Boot LED (on) */
  79. qrio_set_leds();
  80. /* enable Application Buffer */
  81. qrio_enable_app_buffer();
  82. arch_soc_init();
  83. return 0;
  84. }
  85. int board_init(void)
  86. {
  87. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
  88. erratum_a010315();
  89. fsl_serdes_init();
  90. ls102xa_smmu_stream_id_init();
  91. u_qe_init();
  92. return 0;
  93. }
  94. int board_late_init(void)
  95. {
  96. return 0;
  97. }
  98. int misc_init_r(void)
  99. {
  100. if (IS_ENABLED(CONFIG_FSL_DEVICE_DISABLE))
  101. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  102. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
  103. CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
  104. return 0;
  105. }
  106. int ft_board_setup(void *blob, struct bd_info *bd)
  107. {
  108. ft_cpu_setup(blob, bd);
  109. if (IS_ENABLED(CONFIG_PCI))
  110. ft_pci_setup(blob, bd);
  111. return 0;
  112. }
  113. #if defined(CONFIG_POST)
  114. int post_hotkeys_pressed(void)
  115. {
  116. /* DIC26_SELFTEST: GPRTA0, GPA0 */
  117. qrio_gpio_direction_input(QRIO_GPIO_A, 0);
  118. return qrio_get_gpio(QRIO_GPIO_A, 0);
  119. }
  120. ulong post_word_load(void)
  121. {
  122. /* POST word is located at the beginning of reserved physical RAM */
  123. void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
  124. gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
  125. return in_le32(addr);
  126. }
  127. void post_word_store(ulong value)
  128. {
  129. /* POST word is located at the beginning of reserved physical RAM */
  130. void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
  131. gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
  132. out_le32(addr, value);
  133. }
  134. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  135. {
  136. /* Define only 1MiB range for mem_regions at the middle of the RAM */
  137. /* For 1GiB range mem_regions takes approx. 4min */
  138. *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
  139. *size = 1 << 20;
  140. return 0;
  141. }
  142. #endif
  143. u8 flash_read8(void *addr)
  144. {
  145. return __raw_readb(addr + 1);
  146. }
  147. void flash_write16(u16 val, void *addr)
  148. {
  149. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  150. __raw_writew(shftval, addr);
  151. }
  152. u16 flash_read16(void *addr)
  153. {
  154. u16 val = __raw_readw(addr);
  155. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  156. }
  157. int hush_init_var(void)
  158. {
  159. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  160. return 0;
  161. }
  162. int last_stage_init(void)
  163. {
  164. set_km_env();
  165. return 0;
  166. }