xhci.h 43 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * USB HOST XHCI Controller
  4. *
  5. * Based on xHCI host controller driver in linux-kernel
  6. * by Sarah Sharp.
  7. *
  8. * Copyright (C) 2008 Intel Corp.
  9. * Author: Sarah Sharp
  10. *
  11. * Copyright (C) 2013 Samsung Electronics Co.Ltd
  12. * Authors: Vivek Gautam <gautam.vivek@samsung.com>
  13. * Vikas Sajjan <vikas.sajjan@samsung.com>
  14. */
  15. #ifndef HOST_XHCI_H_
  16. #define HOST_XHCI_H_
  17. #include <phys2bus.h>
  18. #include <asm/types.h>
  19. #include <asm/cache.h>
  20. #include <asm/io.h>
  21. #include <linux/list.h>
  22. #include <linux/compat.h>
  23. #define MAX_EP_CTX_NUM 31
  24. #define XHCI_ALIGNMENT 64
  25. /* Generic timeout for XHCI events */
  26. #define XHCI_TIMEOUT 5000
  27. /* Max number of USB devices for any host controller - limit in section 6.1 */
  28. #define MAX_HC_SLOTS 256
  29. /* Section 5.3.3 - MaxPorts */
  30. #define MAX_HC_PORTS 255
  31. /* Up to 16 ms to halt an HC */
  32. #define XHCI_MAX_HALT_USEC (16*1000)
  33. #define XHCI_MAX_RESET_USEC (250*1000)
  34. /*
  35. * These bits are Read Only (RO) and should be saved and written to the
  36. * registers: 0, 3, 10:13, 30
  37. * connect status, over-current status, port speed, and device removable.
  38. * connect status and port speed are also sticky - meaning they're in
  39. * the AUX well and they aren't changed by a hot, warm, or cold reset.
  40. */
  41. #define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30))
  42. /*
  43. * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  44. * bits 5:8, 9, 14:15, 25:27
  45. * link state, port power, port indicator state, "wake on" enable state
  46. */
  47. #define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25))
  48. /*
  49. * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  50. * bit 4 (port reset)
  51. */
  52. #define XHCI_PORT_RW1S ((1 << 4))
  53. /*
  54. * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  55. * bits 1, 17, 18, 19, 20, 21, 22, 23
  56. * port enable/disable, and
  57. * change bits: connect, PED,
  58. * warm port reset changed (reserved zero for USB 2.0 ports),
  59. * over-current, reset, link state, and L1 change
  60. */
  61. #define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17))
  62. /*
  63. * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  64. * latched in
  65. */
  66. #define XHCI_PORT_RW ((1 << 16))
  67. /*
  68. * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  69. * bits 2, 24, 28:31
  70. */
  71. #define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28))
  72. /*
  73. * XHCI Register Space.
  74. */
  75. struct xhci_hccr {
  76. uint32_t cr_capbase;
  77. uint32_t cr_hcsparams1;
  78. uint32_t cr_hcsparams2;
  79. uint32_t cr_hcsparams3;
  80. uint32_t cr_hccparams;
  81. uint32_t cr_dboff;
  82. uint32_t cr_rtsoff;
  83. /* hc_capbase bitmasks */
  84. /* bits 7:0 - how long is the Capabilities register */
  85. #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
  86. /* bits 31:16 */
  87. #define HC_VERSION(p) (((p) >> 16) & 0xffff)
  88. /* HCSPARAMS1 - hcs_params1 - bitmasks */
  89. /* bits 0:7, Max Device Slots */
  90. #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
  91. #define HCS_SLOTS_MASK 0xff
  92. /* bits 8:18, Max Interrupters */
  93. #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
  94. /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
  95. #define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff)
  96. /* HCSPARAMS2 - hcs_params2 - bitmasks */
  97. /* bits 0:3, frames or uframes that SW needs to queue transactions
  98. * ahead of the HW to meet periodic deadlines */
  99. #define HCS_IST(p) (((p) >> 0) & 0xf)
  100. /* bits 4:7, max number of Event Ring segments */
  101. #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
  102. /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
  103. /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
  104. /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
  105. #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
  106. /* HCSPARAMS3 - hcs_params3 - bitmasks */
  107. /* bits 0:7, Max U1 to U0 latency for the roothub ports */
  108. #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
  109. /* bits 16:31, Max U2 to U0 latency for the roothub ports */
  110. #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
  111. /* HCCPARAMS - hcc_params - bitmasks */
  112. /* true: HC can use 64-bit address pointers */
  113. #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
  114. /* true: HC can do bandwidth negotiation */
  115. #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
  116. /* true: HC uses 64-byte Device Context structures
  117. * FIXME 64-byte context structures aren't supported yet.
  118. */
  119. #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
  120. /* true: HC has port power switches */
  121. #define HCC_PPC(p) ((p) & (1 << 3))
  122. /* true: HC has port indicators */
  123. #define HCS_INDICATOR(p) ((p) & (1 << 4))
  124. /* true: HC has Light HC Reset Capability */
  125. #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
  126. /* true: HC supports latency tolerance messaging */
  127. #define HCC_LTC(p) ((p) & (1 << 6))
  128. /* true: no secondary Stream ID Support */
  129. #define HCC_NSS(p) ((p) & (1 << 7))
  130. /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
  131. #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
  132. /* Extended Capabilities pointer from PCI base - section 5.3.6 */
  133. #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
  134. /* db_off bitmask - bits 0:1 reserved */
  135. #define DBOFF_MASK (~0x3)
  136. /* run_regs_off bitmask - bits 0:4 reserved */
  137. #define RTSOFF_MASK (~0x1f)
  138. };
  139. struct xhci_hcor_port_regs {
  140. volatile uint32_t or_portsc;
  141. volatile uint32_t or_portpmsc;
  142. volatile uint32_t or_portli;
  143. volatile uint32_t reserved_3;
  144. };
  145. struct xhci_hcor {
  146. volatile uint32_t or_usbcmd;
  147. volatile uint32_t or_usbsts;
  148. volatile uint32_t or_pagesize;
  149. volatile uint32_t reserved_0[2];
  150. volatile uint32_t or_dnctrl;
  151. volatile uint64_t or_crcr;
  152. volatile uint32_t reserved_1[4];
  153. volatile uint64_t or_dcbaap;
  154. volatile uint32_t or_config;
  155. volatile uint32_t reserved_2[241];
  156. struct xhci_hcor_port_regs portregs[MAX_HC_PORTS];
  157. };
  158. /* USBCMD - USB command - command bitmasks */
  159. /* start/stop HC execution - do not write unless HC is halted*/
  160. #define CMD_RUN XHCI_CMD_RUN
  161. /* Reset HC - resets internal HC state machine and all registers (except
  162. * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
  163. * The xHCI driver must reinitialize the xHC after setting this bit.
  164. */
  165. #define CMD_RESET (1 << 1)
  166. /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
  167. #define CMD_EIE XHCI_CMD_EIE
  168. /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
  169. #define CMD_HSEIE XHCI_CMD_HSEIE
  170. /* bits 4:6 are reserved (and should be preserved on writes). */
  171. /* light reset (port status stays unchanged) - reset completed when this is 0 */
  172. #define CMD_LRESET (1 << 7)
  173. /* host controller save/restore state. */
  174. #define CMD_CSS (1 << 8)
  175. #define CMD_CRS (1 << 9)
  176. /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
  177. #define CMD_EWE XHCI_CMD_EWE
  178. /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
  179. * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
  180. * '0' means the xHC can power it off if all ports are in the disconnect,
  181. * disabled, or powered-off state.
  182. */
  183. #define CMD_PM_INDEX (1 << 11)
  184. /* bits 12:31 are reserved (and should be preserved on writes). */
  185. /* USBSTS - USB status - status bitmasks */
  186. /* HC not running - set to 1 when run/stop bit is cleared. */
  187. #define STS_HALT XHCI_STS_HALT
  188. /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
  189. #define STS_FATAL (1 << 2)
  190. /* event interrupt - clear this prior to clearing any IP flags in IR set*/
  191. #define STS_EINT (1 << 3)
  192. /* port change detect */
  193. #define STS_PORT (1 << 4)
  194. /* bits 5:7 reserved and zeroed */
  195. /* save state status - '1' means xHC is saving state */
  196. #define STS_SAVE (1 << 8)
  197. /* restore state status - '1' means xHC is restoring state */
  198. #define STS_RESTORE (1 << 9)
  199. /* true: save or restore error */
  200. #define STS_SRE (1 << 10)
  201. /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
  202. #define STS_CNR XHCI_STS_CNR
  203. /* true: internal Host Controller Error - SW needs to reset and reinitialize */
  204. #define STS_HCE (1 << 12)
  205. /* bits 13:31 reserved and should be preserved */
  206. /*
  207. * DNCTRL - Device Notification Control Register - dev_notification bitmasks
  208. * Generate a device notification event when the HC sees a transaction with a
  209. * notification type that matches a bit set in this bit field.
  210. */
  211. #define DEV_NOTE_MASK (0xffff)
  212. #define ENABLE_DEV_NOTE(x) (1 << (x))
  213. /* Most of the device notification types should only be used for debug.
  214. * SW does need to pay attention to function wake notifications.
  215. */
  216. #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
  217. /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
  218. /* bit 0 is the command ring cycle state */
  219. /* stop ring operation after completion of the currently executing command */
  220. #define CMD_RING_PAUSE (1 << 1)
  221. /* stop ring immediately - abort the currently executing command */
  222. #define CMD_RING_ABORT (1 << 2)
  223. /* true: command ring is running */
  224. #define CMD_RING_RUNNING (1 << 3)
  225. /* bits 4:5 reserved and should be preserved */
  226. /* Command Ring pointer - bit mask for the lower 32 bits. */
  227. #define CMD_RING_RSVD_BITS (0x3f)
  228. /* CONFIG - Configure Register - config_reg bitmasks */
  229. /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
  230. #define MAX_DEVS(p) ((p) & 0xff)
  231. /* bits 8:31 - reserved and should be preserved */
  232. /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
  233. /* true: device connected */
  234. #define PORT_CONNECT (1 << 0)
  235. /* true: port enabled */
  236. #define PORT_PE (1 << 1)
  237. /* bit 2 reserved and zeroed */
  238. /* true: port has an over-current condition */
  239. #define PORT_OC (1 << 3)
  240. /* true: port reset signaling asserted */
  241. #define PORT_RESET (1 << 4)
  242. /* Port Link State - bits 5:8
  243. * A read gives the current link PM state of the port,
  244. * a write with Link State Write Strobe set sets the link state.
  245. */
  246. #define PORT_PLS_MASK (0xf << 5)
  247. #define XDEV_U0 (0x0 << 5)
  248. #define XDEV_U2 (0x2 << 5)
  249. #define XDEV_U3 (0x3 << 5)
  250. #define XDEV_RESUME (0xf << 5)
  251. /* true: port has power (see HCC_PPC) */
  252. #define PORT_POWER (1 << 9)
  253. /* bits 10:13 indicate device speed:
  254. * 0 - undefined speed - port hasn't be initialized by a reset yet
  255. * 1 - full speed
  256. * 2 - low speed
  257. * 3 - high speed
  258. * 4 - super speed
  259. * 5-15 reserved
  260. */
  261. #define DEV_SPEED_MASK (0xf << 10)
  262. #define XDEV_FS (0x1 << 10)
  263. #define XDEV_LS (0x2 << 10)
  264. #define XDEV_HS (0x3 << 10)
  265. #define XDEV_SS (0x4 << 10)
  266. #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
  267. #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
  268. #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
  269. #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
  270. #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
  271. /* Bits 20:23 in the Slot Context are the speed for the device */
  272. #define SLOT_SPEED_FS (XDEV_FS << 10)
  273. #define SLOT_SPEED_LS (XDEV_LS << 10)
  274. #define SLOT_SPEED_HS (XDEV_HS << 10)
  275. #define SLOT_SPEED_SS (XDEV_SS << 10)
  276. /* Port Indicator Control */
  277. #define PORT_LED_OFF (0 << 14)
  278. #define PORT_LED_AMBER (1 << 14)
  279. #define PORT_LED_GREEN (2 << 14)
  280. #define PORT_LED_MASK (3 << 14)
  281. /* Port Link State Write Strobe - set this when changing link state */
  282. #define PORT_LINK_STROBE (1 << 16)
  283. /* true: connect status change */
  284. #define PORT_CSC (1 << 17)
  285. /* true: port enable change */
  286. #define PORT_PEC (1 << 18)
  287. /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
  288. * into an enabled state, and the device into the default state. A "warm" reset
  289. * also resets the link, forcing the device through the link training sequence.
  290. * SW can also look at the Port Reset register to see when warm reset is done.
  291. */
  292. #define PORT_WRC (1 << 19)
  293. /* true: over-current change */
  294. #define PORT_OCC (1 << 20)
  295. /* true: reset change - 1 to 0 transition of PORT_RESET */
  296. #define PORT_RC (1 << 21)
  297. /* port link status change - set on some port link state transitions:
  298. * Transition Reason
  299. * --------------------------------------------------------------------------
  300. * - U3 to Resume Wakeup signaling from a device
  301. * - Resume to Recovery to U0 USB 3.0 device resume
  302. * - Resume to U0 USB 2.0 device resume
  303. * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
  304. * - U3 to U0 Software resume of USB 2.0 device complete
  305. * - U2 to U0 L1 resume of USB 2.1 device complete
  306. * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
  307. * - U0 to disabled L1 entry error with USB 2.1 device
  308. * - Any state to inactive Error on USB 3.0 port
  309. */
  310. #define PORT_PLC (1 << 22)
  311. /* port configure error change - port failed to configure its link partner */
  312. #define PORT_CEC (1 << 23)
  313. /* bit 24 reserved */
  314. /* wake on connect (enable) */
  315. #define PORT_WKCONN_E (1 << 25)
  316. /* wake on disconnect (enable) */
  317. #define PORT_WKDISC_E (1 << 26)
  318. /* wake on over-current (enable) */
  319. #define PORT_WKOC_E (1 << 27)
  320. /* bits 28:29 reserved */
  321. /* true: device is removable - for USB 3.0 roothub emulation */
  322. #define PORT_DEV_REMOVE (1 << 30)
  323. /* Initiate a warm port reset - complete when PORT_WRC is '1' */
  324. #define PORT_WR (1 << 31)
  325. /* We mark duplicate entries with -1 */
  326. #define DUPLICATE_ENTRY ((u8)(-1))
  327. /* Port Power Management Status and Control - port_power_base bitmasks */
  328. /* Inactivity timer value for transitions into U1, in microseconds.
  329. * Timeout can be up to 127us. 0xFF means an infinite timeout.
  330. */
  331. #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
  332. /* Inactivity timer value for transitions into U2 */
  333. #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
  334. /* Bits 24:31 for port testing */
  335. /* USB2 Protocol PORTSPMSC */
  336. #define PORT_L1S_MASK 7
  337. #define PORT_L1S_SUCCESS 1
  338. #define PORT_RWE (1 << 3)
  339. #define PORT_HIRD(p) (((p) & 0xf) << 4)
  340. #define PORT_HIRD_MASK (0xf << 4)
  341. #define PORT_L1DS(p) (((p) & 0xff) << 8)
  342. #define PORT_HLE (1 << 16)
  343. /**
  344. * struct xhci_intr_reg - Interrupt Register Set
  345. * @irq_pending: IMAN - Interrupt Management Register. Used to enable
  346. * interrupts and check for pending interrupts.
  347. * @irq_control: IMOD - Interrupt Moderation Register.
  348. * Used to throttle interrupts.
  349. * @erst_size: Number of segments in the
  350. Event Ring Segment Table (ERST).
  351. * @erst_base: ERST base address.
  352. * @erst_dequeue: Event ring dequeue pointer.
  353. *
  354. * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
  355. * Ring Segment Table (ERST) associated with it.
  356. * The event ring is comprised of multiple segments of the same size.
  357. * The HC places events on the ring and "updates the Cycle bit in the TRBs to
  358. * indicate to software the current position of the Enqueue Pointer."
  359. * The HCD (Linux) processes those events and updates the dequeue pointer.
  360. */
  361. struct xhci_intr_reg {
  362. volatile __le32 irq_pending;
  363. volatile __le32 irq_control;
  364. volatile __le32 erst_size;
  365. volatile __le32 rsvd;
  366. volatile __le64 erst_base;
  367. volatile __le64 erst_dequeue;
  368. };
  369. /* irq_pending bitmasks */
  370. #define ER_IRQ_PENDING(p) ((p) & 0x1)
  371. /* bits 2:31 need to be preserved */
  372. /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
  373. #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
  374. #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
  375. #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
  376. /* irq_control bitmasks */
  377. /* Minimum interval between interrupts (in 250ns intervals). The interval
  378. * between interrupts will be longer if there are no events on the event ring.
  379. * Default is 4000 (1 ms).
  380. */
  381. #define ER_IRQ_INTERVAL_MASK (0xffff)
  382. /* Counter used to count down the time to the next interrupt - HW use only */
  383. #define ER_IRQ_COUNTER_MASK (0xffff << 16)
  384. /* erst_size bitmasks */
  385. /* Preserve bits 16:31 of erst_size */
  386. #define ERST_SIZE_MASK (0xffff << 16)
  387. /* erst_dequeue bitmasks */
  388. /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
  389. * where the current dequeue pointer lies. This is an optional HW hint.
  390. */
  391. #define ERST_DESI_MASK (0x7)
  392. /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
  393. * a work queue (or delayed service routine)?
  394. */
  395. #define ERST_EHB (1 << 3)
  396. #define ERST_PTR_MASK (0xf)
  397. /**
  398. * struct xhci_run_regs
  399. * @microframe_index: MFINDEX - current microframe number
  400. *
  401. * Section 5.5 Host Controller Runtime Registers:
  402. * "Software should read and write these registers using only Dword (32 bit)
  403. * or larger accesses"
  404. */
  405. struct xhci_run_regs {
  406. __le32 microframe_index;
  407. __le32 rsvd[7];
  408. struct xhci_intr_reg ir_set[128];
  409. };
  410. /**
  411. * struct doorbell_array
  412. *
  413. * Bits 0 - 7: Endpoint target
  414. * Bits 8 - 15: RsvdZ
  415. * Bits 16 - 31: Stream ID
  416. *
  417. * Section 5.6
  418. */
  419. struct xhci_doorbell_array {
  420. volatile __le32 doorbell[256];
  421. };
  422. #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
  423. #define DB_VALUE_HOST 0x00000000
  424. /**
  425. * struct xhci_protocol_caps
  426. * @revision: major revision, minor revision, capability ID,
  427. * and next capability pointer.
  428. * @name_string: Four ASCII characters to say which spec this xHC
  429. * follows, typically "USB ".
  430. * @port_info: Port offset, count, and protocol-defined information.
  431. */
  432. struct xhci_protocol_caps {
  433. u32 revision;
  434. u32 name_string;
  435. u32 port_info;
  436. };
  437. #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
  438. #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
  439. #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
  440. /**
  441. * struct xhci_container_ctx
  442. * @type: Type of context. Used to calculated offsets to contained contexts.
  443. * @size: Size of the context data
  444. * @bytes: The raw context data given to HW
  445. *
  446. * Represents either a Device or Input context. Holds a pointer to the raw
  447. * memory used for the context (bytes).
  448. */
  449. struct xhci_container_ctx {
  450. unsigned type;
  451. #define XHCI_CTX_TYPE_DEVICE 0x1
  452. #define XHCI_CTX_TYPE_INPUT 0x2
  453. int size;
  454. u8 *bytes;
  455. };
  456. /**
  457. * struct xhci_slot_ctx
  458. * @dev_info: Route string, device speed, hub info, and last valid endpoint
  459. * @dev_info2: Max exit latency for device number, root hub port number
  460. * @tt_info: tt_info is used to construct split transaction tokens
  461. * @dev_state: slot state and device address
  462. *
  463. * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
  464. * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
  465. * reserved at the end of the slot context for HC internal use.
  466. */
  467. struct xhci_slot_ctx {
  468. __le32 dev_info;
  469. __le32 dev_info2;
  470. __le32 tt_info;
  471. __le32 dev_state;
  472. /* offset 0x10 to 0x1f reserved for HC internal use */
  473. __le32 reserved[4];
  474. };
  475. /* dev_info bitmasks */
  476. /* Route String - 0:19 */
  477. #define ROUTE_STRING_MASK (0xfffff)
  478. /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
  479. #define DEV_SPEED (0xf << 20)
  480. /* bit 24 reserved */
  481. /* Is this LS/FS device connected through a HS hub? - bit 25 */
  482. #define DEV_MTT (0x1 << 25)
  483. /* Set if the device is a hub - bit 26 */
  484. #define DEV_HUB (0x1 << 26)
  485. /* Index of the last valid endpoint context in this device context - 27:31 */
  486. #define LAST_CTX_MASK (0x1f << 27)
  487. #define LAST_CTX(p) ((p) << 27)
  488. #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
  489. #define SLOT_FLAG (1 << 0)
  490. #define EP0_FLAG (1 << 1)
  491. /* dev_info2 bitmasks */
  492. /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
  493. #define MAX_EXIT (0xffff)
  494. /* Root hub port number that is needed to access the USB device */
  495. #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
  496. #define ROOT_HUB_PORT_MASK (0xff)
  497. #define ROOT_HUB_PORT_SHIFT (16)
  498. #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
  499. /* Maximum number of ports under a hub device */
  500. #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
  501. /* tt_info bitmasks */
  502. /*
  503. * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
  504. * The Slot ID of the hub that isolates the high speed signaling from
  505. * this low or full-speed device. '0' if attached to root hub port.
  506. */
  507. #define TT_SLOT(p) (((p) & 0xff) << 0)
  508. /*
  509. * The number of the downstream facing port of the high-speed hub
  510. * '0' if the device is not low or full speed.
  511. */
  512. #define TT_PORT(p) (((p) & 0xff) << 8)
  513. #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
  514. /* dev_state bitmasks */
  515. /* USB device address - assigned by the HC */
  516. #define DEV_ADDR_MASK (0xff)
  517. /* bits 8:26 reserved */
  518. /* Slot state */
  519. #define SLOT_STATE (0x1f << 27)
  520. #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
  521. #define SLOT_STATE_DISABLED 0
  522. #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
  523. #define SLOT_STATE_DEFAULT 1
  524. #define SLOT_STATE_ADDRESSED 2
  525. #define SLOT_STATE_CONFIGURED 3
  526. /**
  527. * struct xhci_ep_ctx
  528. * @ep_info: endpoint state, streams, mult, and interval information.
  529. * @ep_info2: information on endpoint type, max packet size, max burst size,
  530. * error count, and whether the HC will force an event for all
  531. * transactions.
  532. * @deq: 64-bit ring dequeue pointer address. If the endpoint only
  533. * defines one stream, this points to the endpoint transfer ring.
  534. * Otherwise, it points to a stream context array, which has a
  535. * ring pointer for each flow.
  536. * @tx_info:
  537. * Average TRB lengths for the endpoint ring and
  538. * max payload within an Endpoint Service Interval Time (ESIT).
  539. *
  540. * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context
  541. * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes
  542. * reserved at the end of the endpoint context for HC internal use.
  543. */
  544. struct xhci_ep_ctx {
  545. __le32 ep_info;
  546. __le32 ep_info2;
  547. __le64 deq;
  548. __le32 tx_info;
  549. /* offset 0x14 - 0x1f reserved for HC internal use */
  550. __le32 reserved[3];
  551. };
  552. /* ep_info bitmasks */
  553. /*
  554. * Endpoint State - bits 0:2
  555. * 0 - disabled
  556. * 1 - running
  557. * 2 - halted due to halt condition - ok to manipulate endpoint ring
  558. * 3 - stopped
  559. * 4 - TRB error
  560. * 5-7 - reserved
  561. */
  562. #define EP_STATE_MASK (0xf)
  563. #define EP_STATE_DISABLED 0
  564. #define EP_STATE_RUNNING 1
  565. #define EP_STATE_HALTED 2
  566. #define EP_STATE_STOPPED 3
  567. #define EP_STATE_ERROR 4
  568. /* Mult - Max number of burtst within an interval, in EP companion desc. */
  569. #define EP_MULT(p) (((p) & 0x3) << 8)
  570. #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
  571. /* bits 10:14 are Max Primary Streams */
  572. /* bit 15 is Linear Stream Array */
  573. /* Interval - period between requests to an endpoint - 125u increments. */
  574. #define EP_INTERVAL(p) (((p) & 0xff) << 16)
  575. #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
  576. #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
  577. #define EP_MAXPSTREAMS_MASK (0x1f << 10)
  578. #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
  579. /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
  580. #define EP_HAS_LSA (1 << 15)
  581. /* ep_info2 bitmasks */
  582. /*
  583. * Force Event - generate transfer events for all TRBs for this endpoint
  584. * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
  585. */
  586. #define FORCE_EVENT (0x1)
  587. #define ERROR_COUNT(p) (((p) & 0x3) << 1)
  588. #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
  589. #define EP_TYPE(p) ((p) << 3)
  590. #define ISOC_OUT_EP 1
  591. #define BULK_OUT_EP 2
  592. #define INT_OUT_EP 3
  593. #define CTRL_EP 4
  594. #define ISOC_IN_EP 5
  595. #define BULK_IN_EP 6
  596. #define INT_IN_EP 7
  597. /* bit 6 reserved */
  598. /* bit 7 is Host Initiate Disable - for disabling stream selection */
  599. #define MAX_BURST(p) (((p)&0xff) << 8)
  600. #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
  601. #define MAX_PACKET(p) (((p)&0xffff) << 16)
  602. #define MAX_PACKET_MASK (0xffff)
  603. #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
  604. /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
  605. * USB2.0 spec 9.6.6.
  606. */
  607. #define GET_MAX_PACKET(p) ((p) & 0x7ff)
  608. /* tx_info bitmasks */
  609. #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
  610. #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
  611. #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
  612. #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
  613. /* deq bitmasks */
  614. #define EP_CTX_CYCLE_MASK (1 << 0)
  615. /* reserved[0] bitmasks, MediaTek xHCI used */
  616. #define EP_BPKTS(p) (((p) & 0x7f) << 0)
  617. #define EP_BBM(p) (((p) & 0x1) << 11)
  618. /**
  619. * struct xhci_input_control_context
  620. * Input control context; see section 6.2.5.
  621. *
  622. * @drop_context: set the bit of the endpoint context you want to disable
  623. * @add_context: set the bit of the endpoint context you want to enable
  624. */
  625. struct xhci_input_control_ctx {
  626. volatile __le32 drop_flags;
  627. volatile __le32 add_flags;
  628. __le32 rsvd2[6];
  629. };
  630. /**
  631. * struct xhci_device_context_array
  632. * @dev_context_ptr array of 64-bit DMA addresses for device contexts
  633. */
  634. struct xhci_device_context_array {
  635. /* 64-bit device addresses; we only write 32-bit addresses */
  636. __le64 dev_context_ptrs[MAX_HC_SLOTS];
  637. };
  638. /* TODO: write function to set the 64-bit device DMA address */
  639. /*
  640. * TODO: change this to be dynamically sized at HC mem init time since the HC
  641. * might not be able to handle the maximum number of devices possible.
  642. */
  643. struct xhci_transfer_event {
  644. /* 64-bit buffer address, or immediate data */
  645. __le64 buffer;
  646. __le32 transfer_len;
  647. /* This field is interpreted differently based on the type of TRB */
  648. volatile __le32 flags;
  649. };
  650. /* Transfer event TRB length bit mask */
  651. /* bits 0:23 */
  652. #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
  653. /** Transfer Event bit fields **/
  654. #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
  655. /* Completion Code - only applicable for some types of TRBs */
  656. #define COMP_CODE_MASK (0xff << 24)
  657. #define COMP_CODE_SHIFT (24)
  658. #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
  659. typedef enum {
  660. COMP_SUCCESS = 1,
  661. /* Data Buffer Error */
  662. COMP_DB_ERR, /* 2 */
  663. /* Babble Detected Error */
  664. COMP_BABBLE, /* 3 */
  665. /* USB Transaction Error */
  666. COMP_TX_ERR, /* 4 */
  667. /* TRB Error - some TRB field is invalid */
  668. COMP_TRB_ERR, /* 5 */
  669. /* Stall Error - USB device is stalled */
  670. COMP_STALL, /* 6 */
  671. /* Resource Error - HC doesn't have memory for that device configuration */
  672. COMP_ENOMEM, /* 7 */
  673. /* Bandwidth Error - not enough room in schedule for this dev config */
  674. COMP_BW_ERR, /* 8 */
  675. /* No Slots Available Error - HC ran out of device slots */
  676. COMP_ENOSLOTS, /* 9 */
  677. /* Invalid Stream Type Error */
  678. COMP_STREAM_ERR, /* 10 */
  679. /* Slot Not Enabled Error - doorbell rung for disabled device slot */
  680. COMP_EBADSLT, /* 11 */
  681. /* Endpoint Not Enabled Error */
  682. COMP_EBADEP,/* 12 */
  683. /* Short Packet */
  684. COMP_SHORT_TX, /* 13 */
  685. /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
  686. COMP_UNDERRUN, /* 14 */
  687. /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
  688. COMP_OVERRUN, /* 15 */
  689. /* Virtual Function Event Ring Full Error */
  690. COMP_VF_FULL, /* 16 */
  691. /* Parameter Error - Context parameter is invalid */
  692. COMP_EINVAL, /* 17 */
  693. /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
  694. COMP_BW_OVER,/* 18 */
  695. /* Context State Error - illegal context state transition requested */
  696. COMP_CTX_STATE,/* 19 */
  697. /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
  698. COMP_PING_ERR,/* 20 */
  699. /* Event Ring is full */
  700. COMP_ER_FULL,/* 21 */
  701. /* Incompatible Device Error */
  702. COMP_DEV_ERR,/* 22 */
  703. /* Missed Service Error - HC couldn't service an isoc ep within interval */
  704. COMP_MISSED_INT,/* 23 */
  705. /* Successfully stopped command ring */
  706. COMP_CMD_STOP, /* 24 */
  707. /* Successfully aborted current command and stopped command ring */
  708. COMP_CMD_ABORT, /* 25 */
  709. /* Stopped - transfer was terminated by a stop endpoint command */
  710. COMP_STOP,/* 26 */
  711. /* Same as COMP_EP_STOPPED, but the transferred length in the event
  712. * is invalid */
  713. COMP_STOP_INVAL, /* 27*/
  714. /* Control Abort Error - Debug Capability - control pipe aborted */
  715. COMP_DBG_ABORT, /* 28 */
  716. /* Max Exit Latency Too Large Error */
  717. COMP_MEL_ERR,/* 29 */
  718. /* TRB type 30 reserved */
  719. /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
  720. COMP_BUFF_OVER = 31,
  721. /* Event Lost Error - xHC has an "internal event overrun condition" */
  722. COMP_ISSUES, /* 32 */
  723. /* Undefined Error - reported when other error codes don't apply */
  724. COMP_UNKNOWN, /* 33 */
  725. /* Invalid Stream ID Error */
  726. COMP_STRID_ERR, /* 34 */
  727. /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
  728. COMP_2ND_BW_ERR, /* 35 */
  729. /* Split Transaction Error */
  730. COMP_SPLIT_ERR /* 36 */
  731. } xhci_comp_code;
  732. struct xhci_link_trb {
  733. /* 64-bit segment pointer*/
  734. volatile __le64 segment_ptr;
  735. volatile __le32 intr_target;
  736. volatile __le32 control;
  737. };
  738. /* control bitfields */
  739. #define LINK_TOGGLE (0x1 << 1)
  740. /* Command completion event TRB */
  741. struct xhci_event_cmd {
  742. /* Pointer to command TRB, or the value passed by the event data trb */
  743. volatile __le64 cmd_trb;
  744. volatile __le32 status;
  745. volatile __le32 flags;
  746. };
  747. /* flags bitmasks */
  748. /* bits 16:23 are the virtual function ID */
  749. /* bits 24:31 are the slot ID */
  750. #define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24)
  751. #define TRB_TO_SLOT_ID_SHIFT (24)
  752. #define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT)
  753. #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
  754. #define SLOT_ID_FOR_TRB_MASK (0xff)
  755. #define SLOT_ID_FOR_TRB_SHIFT (24)
  756. /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
  757. #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
  758. #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
  759. #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
  760. #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
  761. #define LAST_EP_INDEX 30
  762. /* Set TR Dequeue Pointer command TRB fields */
  763. #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
  764. #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
  765. /* Port Status Change Event TRB fields */
  766. /* Port ID - bits 31:24 */
  767. #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
  768. #define PORT_ID_SHIFT (24)
  769. #define PORT_ID_MASK (0xff << PORT_ID_SHIFT)
  770. /* Normal TRB fields */
  771. /* transfer_len bitmasks - bits 0:16 */
  772. #define TRB_LEN(p) ((p) & 0x1ffff)
  773. /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
  774. #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
  775. /* Interrupter Target - which MSI-X vector to target the completion event at */
  776. #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
  777. #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
  778. #define TRB_TBC(p) (((p) & 0x3) << 7)
  779. #define TRB_TLBPC(p) (((p) & 0xf) << 16)
  780. /* Cycle bit - indicates TRB ownership by HC or HCD */
  781. #define TRB_CYCLE (1<<0)
  782. /*
  783. * Force next event data TRB to be evaluated before task switch.
  784. * Used to pass OS data back after a TD completes.
  785. */
  786. #define TRB_ENT (1<<1)
  787. /* Interrupt on short packet */
  788. #define TRB_ISP (1<<2)
  789. /* Set PCIe no snoop attribute */
  790. #define TRB_NO_SNOOP (1<<3)
  791. /* Chain multiple TRBs into a TD */
  792. #define TRB_CHAIN (1<<4)
  793. /* Interrupt on completion */
  794. #define TRB_IOC (1<<5)
  795. /* The buffer pointer contains immediate data */
  796. #define TRB_IDT (1<<6)
  797. /* Block Event Interrupt */
  798. #define TRB_BEI (1<<9)
  799. /* Control transfer TRB specific fields */
  800. #define TRB_DIR_IN (1<<16)
  801. #define TRB_TX_TYPE(p) ((p) << 16)
  802. #define TRB_DATA_OUT 2
  803. #define TRB_DATA_IN 3
  804. /* Isochronous TRB specific fields */
  805. #define TRB_SIA (1 << 31)
  806. struct xhci_generic_trb {
  807. volatile __le32 field[4];
  808. };
  809. union xhci_trb {
  810. struct xhci_link_trb link;
  811. struct xhci_transfer_event trans_event;
  812. struct xhci_event_cmd event_cmd;
  813. struct xhci_generic_trb generic;
  814. };
  815. /* TRB bit mask */
  816. #define TRB_TYPE_BITMASK (0xfc00)
  817. #define TRB_TYPE(p) ((p) << 10)
  818. #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
  819. /* TRB type IDs */
  820. typedef enum {
  821. /* bulk, interrupt, isoc scatter/gather, and control data stage */
  822. TRB_NORMAL = 1,
  823. /* setup stage for control transfers */
  824. TRB_SETUP, /* 2 */
  825. /* data stage for control transfers */
  826. TRB_DATA, /* 3 */
  827. /* status stage for control transfers */
  828. TRB_STATUS, /* 4 */
  829. /* isoc transfers */
  830. TRB_ISOC, /* 5 */
  831. /* TRB for linking ring segments */
  832. TRB_LINK, /* 6 */
  833. /* TRB for EVENT DATA */
  834. TRB_EVENT_DATA, /* 7 */
  835. /* Transfer Ring No-op (not for the command ring) */
  836. TRB_TR_NOOP, /* 8 */
  837. /* Command TRBs */
  838. /* Enable Slot Command */
  839. TRB_ENABLE_SLOT, /* 9 */
  840. /* Disable Slot Command */
  841. TRB_DISABLE_SLOT, /* 10 */
  842. /* Address Device Command */
  843. TRB_ADDR_DEV, /* 11 */
  844. /* Configure Endpoint Command */
  845. TRB_CONFIG_EP, /* 12 */
  846. /* Evaluate Context Command */
  847. TRB_EVAL_CONTEXT, /* 13 */
  848. /* Reset Endpoint Command */
  849. TRB_RESET_EP, /* 14 */
  850. /* Stop Transfer Ring Command */
  851. TRB_STOP_RING, /* 15 */
  852. /* Set Transfer Ring Dequeue Pointer Command */
  853. TRB_SET_DEQ, /* 16 */
  854. /* Reset Device Command */
  855. TRB_RESET_DEV, /* 17 */
  856. /* Force Event Command (opt) */
  857. TRB_FORCE_EVENT, /* 18 */
  858. /* Negotiate Bandwidth Command (opt) */
  859. TRB_NEG_BANDWIDTH, /* 19 */
  860. /* Set Latency Tolerance Value Command (opt) */
  861. TRB_SET_LT, /* 20 */
  862. /* Get port bandwidth Command */
  863. TRB_GET_BW, /* 21 */
  864. /* Force Header Command - generate a transaction or link management packet */
  865. TRB_FORCE_HEADER, /* 22 */
  866. /* No-op Command - not for transfer rings */
  867. TRB_CMD_NOOP, /* 23 */
  868. /* TRB IDs 24-31 reserved */
  869. /* Event TRBS */
  870. /* Transfer Event */
  871. TRB_TRANSFER = 32,
  872. /* Command Completion Event */
  873. TRB_COMPLETION, /* 33 */
  874. /* Port Status Change Event */
  875. TRB_PORT_STATUS, /* 34 */
  876. /* Bandwidth Request Event (opt) */
  877. TRB_BANDWIDTH_EVENT, /* 35 */
  878. /* Doorbell Event (opt) */
  879. TRB_DOORBELL, /* 36 */
  880. /* Host Controller Event */
  881. TRB_HC_EVENT, /* 37 */
  882. /* Device Notification Event - device sent function wake notification */
  883. TRB_DEV_NOTE, /* 38 */
  884. /* MFINDEX Wrap Event - microframe counter wrapped */
  885. TRB_MFINDEX_WRAP, /* 39 */
  886. /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
  887. /* Nec vendor-specific command completion event. */
  888. TRB_NEC_CMD_COMP = 48, /* 48 */
  889. /* Get NEC firmware revision. */
  890. TRB_NEC_GET_FW, /* 49 */
  891. } trb_type;
  892. #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
  893. /* Above, but for __le32 types -- can avoid work by swapping constants: */
  894. #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
  895. cpu_to_le32(TRB_TYPE(TRB_LINK)))
  896. #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
  897. cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
  898. /*
  899. * TRBS_PER_SEGMENT must be a multiple of 4,
  900. * since the command ring is 64-byte aligned.
  901. * It must also be greater than 16.
  902. */
  903. #define TRBS_PER_SEGMENT 64
  904. /* Allow two commands + a link TRB, along with any reserved command TRBs */
  905. #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
  906. #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
  907. /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
  908. * Change this if you change TRBS_PER_SEGMENT!
  909. */
  910. #define SEGMENT_SHIFT 10
  911. /* TRB buffer pointers can't cross 64KB boundaries */
  912. #define TRB_MAX_BUFF_SHIFT 16
  913. #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
  914. struct xhci_segment {
  915. union xhci_trb *trbs;
  916. /* private to HCD */
  917. struct xhci_segment *next;
  918. };
  919. struct xhci_ring {
  920. struct xhci_segment *first_seg;
  921. union xhci_trb *enqueue;
  922. struct xhci_segment *enq_seg;
  923. union xhci_trb *dequeue;
  924. struct xhci_segment *deq_seg;
  925. /*
  926. * Write the cycle state into the TRB cycle field to give ownership of
  927. * the TRB to the host controller (if we are the producer), or to check
  928. * if we own the TRB (if we are the consumer). See section 4.9.1.
  929. */
  930. volatile u32 cycle_state;
  931. unsigned int num_segs;
  932. };
  933. struct xhci_erst_entry {
  934. /* 64-bit event ring segment address */
  935. __le64 seg_addr;
  936. __le32 seg_size;
  937. /* Set to zero */
  938. __le32 rsvd;
  939. };
  940. struct xhci_erst {
  941. struct xhci_erst_entry *entries;
  942. unsigned int num_entries;
  943. /* Num entries the ERST can contain */
  944. unsigned int erst_size;
  945. };
  946. struct xhci_scratchpad {
  947. u64 *sp_array;
  948. };
  949. /*
  950. * Each segment table entry is 4*32bits long. 1K seems like an ok size:
  951. * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
  952. * meaning 64 ring segments.
  953. * Initial allocated size of the ERST, in number of entries */
  954. #define ERST_NUM_SEGS 1
  955. /* Initial number of event segment rings allocated */
  956. #define ERST_ENTRIES 1
  957. /* Initial allocated size of the ERST, in number of entries */
  958. #define ERST_SIZE 64
  959. /* Poll every 60 seconds */
  960. #define POLL_TIMEOUT 60
  961. /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
  962. #define XHCI_STOP_EP_CMD_TIMEOUT 5
  963. /* XXX: Make these module parameters */
  964. struct xhci_virt_ep {
  965. struct xhci_ring *ring;
  966. unsigned int ep_state;
  967. #define SET_DEQ_PENDING (1 << 0)
  968. #define EP_HALTED (1 << 1) /* For stall handling */
  969. #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
  970. /* Transitioning the endpoint to using streams, don't enqueue URBs */
  971. #define EP_GETTING_STREAMS (1 << 3)
  972. #define EP_HAS_STREAMS (1 << 4)
  973. /* Transitioning the endpoint to not using streams, don't enqueue URBs */
  974. #define EP_GETTING_NO_STREAMS (1 << 5)
  975. };
  976. #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
  977. struct xhci_virt_device {
  978. struct usb_device *udev;
  979. /*
  980. * Commands to the hardware are passed an "input context" that
  981. * tells the hardware what to change in its data structures.
  982. * The hardware will return changes in an "output context" that
  983. * software must allocate for the hardware. We need to keep
  984. * track of input and output contexts separately because
  985. * these commands might fail and we don't trust the hardware.
  986. */
  987. struct xhci_container_ctx *out_ctx;
  988. /* Used for addressing devices and configuration changes */
  989. struct xhci_container_ctx *in_ctx;
  990. /* Rings saved to ensure old alt settings can be re-instated */
  991. #define XHCI_MAX_RINGS_CACHED 31
  992. struct xhci_virt_ep eps[31];
  993. };
  994. /* TODO: copied from ehci.h - can be refactored? */
  995. /* xHCI spec says all registers are little endian */
  996. static inline unsigned int xhci_readl(uint32_t volatile *regs)
  997. {
  998. return readl(regs);
  999. }
  1000. static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
  1001. {
  1002. writel(val, regs);
  1003. }
  1004. /*
  1005. * Registers should always be accessed with double word or quad word accesses.
  1006. * Some xHCI implementations may support 64-bit address pointers. Registers
  1007. * with 64-bit address pointers should be written to with dword accesses by
  1008. * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
  1009. * xHCI implementations that do not support 64-bit address pointers will ignore
  1010. * the high dword, and write order is irrelevant.
  1011. */
  1012. static inline u64 xhci_readq(__le64 volatile *regs)
  1013. {
  1014. __u32 *ptr = (__u32 *)regs;
  1015. u64 val_lo = readl(ptr);
  1016. u64 val_hi = readl(ptr + 1);
  1017. return val_lo + (val_hi << 32);
  1018. }
  1019. static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
  1020. {
  1021. __u32 *ptr = (__u32 *)regs;
  1022. u32 val_lo = lower_32_bits(val);
  1023. /* FIXME */
  1024. u32 val_hi = upper_32_bits(val);
  1025. writel(val_lo, ptr);
  1026. writel(val_hi, ptr + 1);
  1027. }
  1028. int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
  1029. struct xhci_hcor **ret_hcor);
  1030. void xhci_hcd_stop(int index);
  1031. /*************************************************************
  1032. EXTENDED CAPABILITY DEFINITIONS
  1033. *************************************************************/
  1034. /* Up to 16 ms to halt an HC */
  1035. #define XHCI_MAX_HALT_USEC (16*1000)
  1036. /* HC not running - set to 1 when run/stop bit is cleared. */
  1037. #define XHCI_STS_HALT (1 << 0)
  1038. /* HCCPARAMS offset from PCI base address */
  1039. #define XHCI_HCC_PARAMS_OFFSET 0x10
  1040. /* HCCPARAMS contains the first extended capability pointer */
  1041. #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
  1042. /* Command and Status registers offset from the Operational Registers address */
  1043. #define XHCI_CMD_OFFSET 0x00
  1044. #define XHCI_STS_OFFSET 0x04
  1045. #define XHCI_MAX_EXT_CAPS 50
  1046. /* Capability Register */
  1047. /* bits 7:0 - how long is the Capabilities register */
  1048. #define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff)
  1049. /* Extended capability register fields */
  1050. #define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff)
  1051. #define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff)
  1052. #define XHCI_EXT_CAPS_VAL(p) ((p) >> 16)
  1053. /* Extended capability IDs - ID 0 reserved */
  1054. #define XHCI_EXT_CAPS_LEGACY 1
  1055. #define XHCI_EXT_CAPS_PROTOCOL 2
  1056. #define XHCI_EXT_CAPS_PM 3
  1057. #define XHCI_EXT_CAPS_VIRT 4
  1058. #define XHCI_EXT_CAPS_ROUTE 5
  1059. /* IDs 6-9 reserved */
  1060. #define XHCI_EXT_CAPS_DEBUG 10
  1061. /* USB Legacy Support Capability - section 7.1.1 */
  1062. #define XHCI_HC_BIOS_OWNED (1 << 16)
  1063. #define XHCI_HC_OS_OWNED (1 << 24)
  1064. /* USB Legacy Support Capability - section 7.1.1 */
  1065. /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
  1066. #define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
  1067. /* USB Legacy Support Control and Status Register - section 7.1.2 */
  1068. /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
  1069. #define XHCI_LEGACY_CONTROL_OFFSET (0x04)
  1070. /* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
  1071. #define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17))
  1072. /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
  1073. #define XHCI_L1C (1 << 16)
  1074. /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
  1075. #define XHCI_HLC (1 << 19)
  1076. /* command register values to disable interrupts and halt the HC */
  1077. /* start/stop HC execution - do not write unless HC is halted*/
  1078. #define XHCI_CMD_RUN (1 << 0)
  1079. /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
  1080. #define XHCI_CMD_EIE (1 << 2)
  1081. /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
  1082. #define XHCI_CMD_HSEIE (1 << 3)
  1083. /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
  1084. #define XHCI_CMD_EWE (1 << 10)
  1085. #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
  1086. /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
  1087. #define XHCI_STS_CNR (1 << 11)
  1088. struct xhci_ctrl {
  1089. #if CONFIG_IS_ENABLED(DM_USB)
  1090. struct udevice *dev;
  1091. #endif
  1092. struct xhci_hccr *hccr; /* R/O registers, not need for volatile */
  1093. struct xhci_hcor *hcor;
  1094. struct xhci_doorbell_array *dba;
  1095. struct xhci_run_regs *run_regs;
  1096. struct xhci_device_context_array *dcbaa \
  1097. __attribute__ ((aligned(ARCH_DMA_MINALIGN)));
  1098. struct xhci_ring *event_ring;
  1099. struct xhci_ring *cmd_ring;
  1100. struct xhci_ring *transfer_ring;
  1101. struct xhci_segment *seg;
  1102. struct xhci_intr_reg *ir_set;
  1103. struct xhci_erst erst;
  1104. struct xhci_erst_entry entry[ERST_NUM_SEGS];
  1105. struct xhci_scratchpad *scratchpad;
  1106. struct xhci_virt_device *devs[MAX_HC_SLOTS];
  1107. int rootdev;
  1108. u16 hci_version;
  1109. u32 quirks;
  1110. #define XHCI_MTK_HOST BIT(0)
  1111. };
  1112. #if CONFIG_IS_ENABLED(DM_USB)
  1113. #define xhci_to_dev(_ctrl) _ctrl->dev
  1114. #else
  1115. #define xhci_to_dev(_ctrl) NULL
  1116. #endif
  1117. unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb);
  1118. struct xhci_input_control_ctx
  1119. *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
  1120. struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
  1121. struct xhci_container_ctx *ctx);
  1122. struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
  1123. struct xhci_container_ctx *ctx,
  1124. unsigned int ep_index);
  1125. void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
  1126. struct xhci_container_ctx *in_ctx,
  1127. struct xhci_container_ctx *out_ctx,
  1128. unsigned int ep_index);
  1129. void xhci_slot_copy(struct xhci_ctrl *ctrl,
  1130. struct xhci_container_ctx *in_ctx,
  1131. struct xhci_container_ctx *out_ctx);
  1132. void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
  1133. struct usb_device *udev, int hop_portnr);
  1134. void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr,
  1135. u32 slot_id, u32 ep_index, trb_type cmd);
  1136. void xhci_acknowledge_event(struct xhci_ctrl *ctrl);
  1137. union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected);
  1138. int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
  1139. int length, void *buffer);
  1140. int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe,
  1141. struct devrequest *req, int length, void *buffer);
  1142. int xhci_check_maxpacket(struct usb_device *udev);
  1143. void xhci_flush_cache(uintptr_t addr, u32 type_len);
  1144. void xhci_inval_cache(uintptr_t addr, u32 type_len);
  1145. void xhci_cleanup(struct xhci_ctrl *ctrl);
  1146. struct xhci_ring *xhci_ring_alloc(struct xhci_ctrl *ctrl, unsigned int num_segs,
  1147. bool link_trbs);
  1148. int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id);
  1149. int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
  1150. struct xhci_hcor *hcor);
  1151. /**
  1152. * xhci_deregister() - Unregister an XHCI controller
  1153. *
  1154. * @dev: Controller device
  1155. * @return 0 if registered, -ve on error
  1156. */
  1157. int xhci_deregister(struct udevice *dev);
  1158. /**
  1159. * xhci_register() - Register a new XHCI controller
  1160. *
  1161. * @dev: Controller device
  1162. * @hccr: Host controller control registers
  1163. * @hcor: Not sure what this means
  1164. * @return 0 if registered, -ve on error
  1165. */
  1166. int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
  1167. struct xhci_hcor *hcor);
  1168. extern struct dm_usb_ops xhci_usb_ops;
  1169. struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev);
  1170. static inline dma_addr_t xhci_virt_to_bus(struct xhci_ctrl *ctrl, void *addr)
  1171. {
  1172. return dev_phys_to_bus(xhci_to_dev(ctrl), virt_to_phys(addr));
  1173. }
  1174. static inline void *xhci_bus_to_virt(struct xhci_ctrl *ctrl, dma_addr_t addr)
  1175. {
  1176. return phys_to_virt(dev_bus_to_phys(xhci_to_dev(ctrl), addr));
  1177. }
  1178. #endif /* HOST_XHCI_H_ */