xhci-mem.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB HOST XHCI Controller stack
  4. *
  5. * Based on xHCI host controller driver in linux-kernel
  6. * by Sarah Sharp.
  7. *
  8. * Copyright (C) 2008 Intel Corp.
  9. * Author: Sarah Sharp
  10. *
  11. * Copyright (C) 2013 Samsung Electronics Co.Ltd
  12. * Authors: Vivek Gautam <gautam.vivek@samsung.com>
  13. * Vikas Sajjan <vikas.sajjan@samsung.com>
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <dm.h>
  18. #include <log.h>
  19. #include <asm/byteorder.h>
  20. #include <usb.h>
  21. #include <malloc.h>
  22. #include <asm/cache.h>
  23. #include <linux/bug.h>
  24. #include <linux/errno.h>
  25. #include <usb/xhci.h>
  26. #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
  27. /**
  28. * flushes the address passed till the length
  29. *
  30. * @param addr pointer to memory region to be flushed
  31. * @param len the length of the cache line to be flushed
  32. * @return none
  33. */
  34. void xhci_flush_cache(uintptr_t addr, u32 len)
  35. {
  36. BUG_ON((void *)addr == NULL || len == 0);
  37. flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
  38. ALIGN(addr + len, CACHELINE_SIZE));
  39. }
  40. /**
  41. * invalidates the address passed till the length
  42. *
  43. * @param addr pointer to memory region to be invalidates
  44. * @param len the length of the cache line to be invalidated
  45. * @return none
  46. */
  47. void xhci_inval_cache(uintptr_t addr, u32 len)
  48. {
  49. BUG_ON((void *)addr == NULL || len == 0);
  50. invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
  51. ALIGN(addr + len, CACHELINE_SIZE));
  52. }
  53. /**
  54. * frees the "segment" pointer passed
  55. *
  56. * @param ptr pointer to "segement" to be freed
  57. * @return none
  58. */
  59. static void xhci_segment_free(struct xhci_segment *seg)
  60. {
  61. free(seg->trbs);
  62. seg->trbs = NULL;
  63. free(seg);
  64. }
  65. /**
  66. * frees the "ring" pointer passed
  67. *
  68. * @param ptr pointer to "ring" to be freed
  69. * @return none
  70. */
  71. static void xhci_ring_free(struct xhci_ring *ring)
  72. {
  73. struct xhci_segment *seg;
  74. struct xhci_segment *first_seg;
  75. BUG_ON(!ring);
  76. first_seg = ring->first_seg;
  77. seg = first_seg->next;
  78. while (seg != first_seg) {
  79. struct xhci_segment *next = seg->next;
  80. xhci_segment_free(seg);
  81. seg = next;
  82. }
  83. xhci_segment_free(first_seg);
  84. free(ring);
  85. }
  86. /**
  87. * Free the scratchpad buffer array and scratchpad buffers
  88. *
  89. * @ctrl host controller data structure
  90. * @return none
  91. */
  92. static void xhci_scratchpad_free(struct xhci_ctrl *ctrl)
  93. {
  94. if (!ctrl->scratchpad)
  95. return;
  96. ctrl->dcbaa->dev_context_ptrs[0] = 0;
  97. free(xhci_bus_to_virt(ctrl, le64_to_cpu(ctrl->scratchpad->sp_array[0])));
  98. free(ctrl->scratchpad->sp_array);
  99. free(ctrl->scratchpad);
  100. ctrl->scratchpad = NULL;
  101. }
  102. /**
  103. * frees the "xhci_container_ctx" pointer passed
  104. *
  105. * @param ptr pointer to "xhci_container_ctx" to be freed
  106. * @return none
  107. */
  108. static void xhci_free_container_ctx(struct xhci_container_ctx *ctx)
  109. {
  110. free(ctx->bytes);
  111. free(ctx);
  112. }
  113. /**
  114. * frees the virtual devices for "xhci_ctrl" pointer passed
  115. *
  116. * @param ptr pointer to "xhci_ctrl" whose virtual devices are to be freed
  117. * @return none
  118. */
  119. static void xhci_free_virt_devices(struct xhci_ctrl *ctrl)
  120. {
  121. int i;
  122. int slot_id;
  123. struct xhci_virt_device *virt_dev;
  124. /*
  125. * refactored here to loop through all virt_dev
  126. * Slot ID 0 is reserved
  127. */
  128. for (slot_id = 0; slot_id < MAX_HC_SLOTS; slot_id++) {
  129. virt_dev = ctrl->devs[slot_id];
  130. if (!virt_dev)
  131. continue;
  132. ctrl->dcbaa->dev_context_ptrs[slot_id] = 0;
  133. for (i = 0; i < 31; ++i)
  134. if (virt_dev->eps[i].ring)
  135. xhci_ring_free(virt_dev->eps[i].ring);
  136. if (virt_dev->in_ctx)
  137. xhci_free_container_ctx(virt_dev->in_ctx);
  138. if (virt_dev->out_ctx)
  139. xhci_free_container_ctx(virt_dev->out_ctx);
  140. free(virt_dev);
  141. /* make sure we are pointing to NULL */
  142. ctrl->devs[slot_id] = NULL;
  143. }
  144. }
  145. /**
  146. * frees all the memory allocated
  147. *
  148. * @param ptr pointer to "xhci_ctrl" to be cleaned up
  149. * @return none
  150. */
  151. void xhci_cleanup(struct xhci_ctrl *ctrl)
  152. {
  153. xhci_ring_free(ctrl->event_ring);
  154. xhci_ring_free(ctrl->cmd_ring);
  155. xhci_scratchpad_free(ctrl);
  156. xhci_free_virt_devices(ctrl);
  157. free(ctrl->erst.entries);
  158. free(ctrl->dcbaa);
  159. memset(ctrl, '\0', sizeof(struct xhci_ctrl));
  160. }
  161. /**
  162. * Malloc the aligned memory
  163. *
  164. * @param size size of memory to be allocated
  165. * @return allocates the memory and returns the aligned pointer
  166. */
  167. static void *xhci_malloc(unsigned int size)
  168. {
  169. void *ptr;
  170. size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE);
  171. ptr = memalign(cacheline_size, ALIGN(size, cacheline_size));
  172. BUG_ON(!ptr);
  173. memset(ptr, '\0', size);
  174. xhci_flush_cache((uintptr_t)ptr, size);
  175. return ptr;
  176. }
  177. /**
  178. * Make the prev segment point to the next segment.
  179. * Change the last TRB in the prev segment to be a Link TRB which points to the
  180. * address of the next segment. The caller needs to set any Link TRB
  181. * related flags, such as End TRB, Toggle Cycle, and no snoop.
  182. *
  183. * @param prev pointer to the previous segment
  184. * @param next pointer to the next segment
  185. * @param link_trbs flag to indicate whether to link the trbs or NOT
  186. * @return none
  187. */
  188. static void xhci_link_segments(struct xhci_ctrl *ctrl, struct xhci_segment *prev,
  189. struct xhci_segment *next, bool link_trbs)
  190. {
  191. u32 val;
  192. u64 val_64 = 0;
  193. if (!prev || !next)
  194. return;
  195. prev->next = next;
  196. if (link_trbs) {
  197. val_64 = xhci_virt_to_bus(ctrl, next->trbs);
  198. prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
  199. cpu_to_le64(val_64);
  200. /*
  201. * Set the last TRB in the segment to
  202. * have a TRB type ID of Link TRB
  203. */
  204. val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
  205. val &= ~TRB_TYPE_BITMASK;
  206. val |= TRB_TYPE(TRB_LINK);
  207. prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
  208. }
  209. }
  210. /**
  211. * Initialises the Ring's enqueue,dequeue,enq_seg pointers
  212. *
  213. * @param ring pointer to the RING to be intialised
  214. * @return none
  215. */
  216. static void xhci_initialize_ring_info(struct xhci_ring *ring)
  217. {
  218. /*
  219. * The ring is empty, so the enqueue pointer == dequeue pointer
  220. */
  221. ring->enqueue = ring->first_seg->trbs;
  222. ring->enq_seg = ring->first_seg;
  223. ring->dequeue = ring->enqueue;
  224. ring->deq_seg = ring->first_seg;
  225. /*
  226. * The ring is initialized to 0. The producer must write 1 to the
  227. * cycle bit to handover ownership of the TRB, so PCS = 1.
  228. * The consumer must compare CCS to the cycle bit to
  229. * check ownership, so CCS = 1.
  230. */
  231. ring->cycle_state = 1;
  232. }
  233. /**
  234. * Allocates a generic ring segment from the ring pool, sets the dma address,
  235. * initializes the segment to zero, and sets the private next pointer to NULL.
  236. * Section 4.11.1.1:
  237. * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  238. *
  239. * @param none
  240. * @return pointer to the newly allocated SEGMENT
  241. */
  242. static struct xhci_segment *xhci_segment_alloc(void)
  243. {
  244. struct xhci_segment *seg;
  245. seg = malloc(sizeof(struct xhci_segment));
  246. BUG_ON(!seg);
  247. seg->trbs = xhci_malloc(SEGMENT_SIZE);
  248. seg->next = NULL;
  249. return seg;
  250. }
  251. /**
  252. * Create a new ring with zero or more segments.
  253. * TODO: current code only uses one-time-allocated single-segment rings
  254. * of 1KB anyway, so we might as well get rid of all the segment and
  255. * linking code (and maybe increase the size a bit, e.g. 4KB).
  256. *
  257. *
  258. * Link each segment together into a ring.
  259. * Set the end flag and the cycle toggle bit on the last segment.
  260. * See section 4.9.2 and figures 15 and 16 of XHCI spec rev1.0.
  261. *
  262. * @param num_segs number of segments in the ring
  263. * @param link_trbs flag to indicate whether to link the trbs or NOT
  264. * @return pointer to the newly created RING
  265. */
  266. struct xhci_ring *xhci_ring_alloc(struct xhci_ctrl *ctrl, unsigned int num_segs,
  267. bool link_trbs)
  268. {
  269. struct xhci_ring *ring;
  270. struct xhci_segment *prev;
  271. ring = malloc(sizeof(struct xhci_ring));
  272. BUG_ON(!ring);
  273. if (num_segs == 0)
  274. return ring;
  275. ring->first_seg = xhci_segment_alloc();
  276. BUG_ON(!ring->first_seg);
  277. num_segs--;
  278. prev = ring->first_seg;
  279. while (num_segs > 0) {
  280. struct xhci_segment *next;
  281. next = xhci_segment_alloc();
  282. BUG_ON(!next);
  283. xhci_link_segments(ctrl, prev, next, link_trbs);
  284. prev = next;
  285. num_segs--;
  286. }
  287. xhci_link_segments(ctrl, prev, ring->first_seg, link_trbs);
  288. if (link_trbs) {
  289. /* See section 4.9.2.1 and 6.4.4.1 */
  290. prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
  291. cpu_to_le32(LINK_TOGGLE);
  292. }
  293. xhci_initialize_ring_info(ring);
  294. return ring;
  295. }
  296. /**
  297. * Set up the scratchpad buffer array and scratchpad buffers
  298. *
  299. * @ctrl host controller data structure
  300. * @return -ENOMEM if buffer allocation fails, 0 on success
  301. */
  302. static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
  303. {
  304. struct xhci_hccr *hccr = ctrl->hccr;
  305. struct xhci_hcor *hcor = ctrl->hcor;
  306. struct xhci_scratchpad *scratchpad;
  307. uint64_t val_64;
  308. int num_sp;
  309. uint32_t page_size;
  310. void *buf;
  311. int i;
  312. num_sp = HCS_MAX_SCRATCHPAD(xhci_readl(&hccr->cr_hcsparams2));
  313. if (!num_sp)
  314. return 0;
  315. scratchpad = malloc(sizeof(*scratchpad));
  316. if (!scratchpad)
  317. goto fail_sp;
  318. ctrl->scratchpad = scratchpad;
  319. scratchpad->sp_array = xhci_malloc(num_sp * sizeof(u64));
  320. if (!scratchpad->sp_array)
  321. goto fail_sp2;
  322. val_64 = xhci_virt_to_bus(ctrl, scratchpad->sp_array);
  323. ctrl->dcbaa->dev_context_ptrs[0] = cpu_to_le64(val_64);
  324. xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[0],
  325. sizeof(ctrl->dcbaa->dev_context_ptrs[0]));
  326. page_size = xhci_readl(&hcor->or_pagesize) & 0xffff;
  327. for (i = 0; i < 16; i++) {
  328. if ((0x1 & page_size) != 0)
  329. break;
  330. page_size = page_size >> 1;
  331. }
  332. BUG_ON(i == 16);
  333. page_size = 1 << (i + 12);
  334. buf = memalign(page_size, num_sp * page_size);
  335. if (!buf)
  336. goto fail_sp3;
  337. memset(buf, '\0', num_sp * page_size);
  338. xhci_flush_cache((uintptr_t)buf, num_sp * page_size);
  339. for (i = 0; i < num_sp; i++) {
  340. val_64 = xhci_virt_to_bus(ctrl, buf + i * page_size);
  341. scratchpad->sp_array[i] = cpu_to_le64(val_64);
  342. }
  343. xhci_flush_cache((uintptr_t)scratchpad->sp_array,
  344. sizeof(u64) * num_sp);
  345. return 0;
  346. fail_sp3:
  347. free(scratchpad->sp_array);
  348. fail_sp2:
  349. free(scratchpad);
  350. ctrl->scratchpad = NULL;
  351. fail_sp:
  352. return -ENOMEM;
  353. }
  354. /**
  355. * Allocates the Container context
  356. *
  357. * @param ctrl Host controller data structure
  358. * @param type type of XHCI Container Context
  359. * @return NULL if failed else pointer to the context on success
  360. */
  361. static struct xhci_container_ctx
  362. *xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, int type)
  363. {
  364. struct xhci_container_ctx *ctx;
  365. ctx = malloc(sizeof(struct xhci_container_ctx));
  366. BUG_ON(!ctx);
  367. BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
  368. ctx->type = type;
  369. ctx->size = (MAX_EP_CTX_NUM + 1) *
  370. CTX_SIZE(xhci_readl(&ctrl->hccr->cr_hccparams));
  371. if (type == XHCI_CTX_TYPE_INPUT)
  372. ctx->size += CTX_SIZE(xhci_readl(&ctrl->hccr->cr_hccparams));
  373. ctx->bytes = xhci_malloc(ctx->size);
  374. return ctx;
  375. }
  376. /**
  377. * Allocating virtual device
  378. *
  379. * @param udev pointer to USB deivce structure
  380. * @return 0 on success else -1 on failure
  381. */
  382. int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id)
  383. {
  384. u64 byte_64 = 0;
  385. struct xhci_virt_device *virt_dev;
  386. /* Slot ID 0 is reserved */
  387. if (ctrl->devs[slot_id]) {
  388. printf("Virt dev for slot[%d] already allocated\n", slot_id);
  389. return -EEXIST;
  390. }
  391. ctrl->devs[slot_id] = malloc(sizeof(struct xhci_virt_device));
  392. if (!ctrl->devs[slot_id]) {
  393. puts("Failed to allocate virtual device\n");
  394. return -ENOMEM;
  395. }
  396. memset(ctrl->devs[slot_id], 0, sizeof(struct xhci_virt_device));
  397. virt_dev = ctrl->devs[slot_id];
  398. /* Allocate the (output) device context that will be used in the HC. */
  399. virt_dev->out_ctx = xhci_alloc_container_ctx(ctrl,
  400. XHCI_CTX_TYPE_DEVICE);
  401. if (!virt_dev->out_ctx) {
  402. puts("Failed to allocate out context for virt dev\n");
  403. return -ENOMEM;
  404. }
  405. /* Allocate the (input) device context for address device command */
  406. virt_dev->in_ctx = xhci_alloc_container_ctx(ctrl,
  407. XHCI_CTX_TYPE_INPUT);
  408. if (!virt_dev->in_ctx) {
  409. puts("Failed to allocate in context for virt dev\n");
  410. return -ENOMEM;
  411. }
  412. /* Allocate endpoint 0 ring */
  413. virt_dev->eps[0].ring = xhci_ring_alloc(ctrl, 1, true);
  414. byte_64 = xhci_virt_to_bus(ctrl, virt_dev->out_ctx->bytes);
  415. /* Point to output device context in dcbaa. */
  416. ctrl->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(byte_64);
  417. xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[slot_id],
  418. sizeof(__le64));
  419. return 0;
  420. }
  421. /**
  422. * Allocates the necessary data structures
  423. * for XHCI host controller
  424. *
  425. * @param ctrl Host controller data structure
  426. * @param hccr pointer to HOST Controller Control Registers
  427. * @param hcor pointer to HOST Controller Operational Registers
  428. * @return 0 if successful else -1 on failure
  429. */
  430. int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
  431. struct xhci_hcor *hcor)
  432. {
  433. uint64_t val_64;
  434. uint64_t trb_64;
  435. uint32_t val;
  436. uint64_t deq;
  437. int i;
  438. struct xhci_segment *seg;
  439. /* DCBAA initialization */
  440. ctrl->dcbaa = xhci_malloc(sizeof(struct xhci_device_context_array));
  441. if (ctrl->dcbaa == NULL) {
  442. puts("unable to allocate DCBA\n");
  443. return -ENOMEM;
  444. }
  445. val_64 = xhci_virt_to_bus(ctrl, ctrl->dcbaa);
  446. /* Set the pointer in DCBAA register */
  447. xhci_writeq(&hcor->or_dcbaap, val_64);
  448. /* Command ring control pointer register initialization */
  449. ctrl->cmd_ring = xhci_ring_alloc(ctrl, 1, true);
  450. /* Set the address in the Command Ring Control register */
  451. trb_64 = xhci_virt_to_bus(ctrl, ctrl->cmd_ring->first_seg->trbs);
  452. val_64 = xhci_readq(&hcor->or_crcr);
  453. val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
  454. (trb_64 & (u64) ~CMD_RING_RSVD_BITS) |
  455. ctrl->cmd_ring->cycle_state;
  456. xhci_writeq(&hcor->or_crcr, val_64);
  457. /* write the address of db register */
  458. val = xhci_readl(&hccr->cr_dboff);
  459. val &= DBOFF_MASK;
  460. ctrl->dba = (struct xhci_doorbell_array *)((char *)hccr + val);
  461. /* write the address of runtime register */
  462. val = xhci_readl(&hccr->cr_rtsoff);
  463. val &= RTSOFF_MASK;
  464. ctrl->run_regs = (struct xhci_run_regs *)((char *)hccr + val);
  465. /* writting the address of ir_set structure */
  466. ctrl->ir_set = &ctrl->run_regs->ir_set[0];
  467. /* Event ring does not maintain link TRB */
  468. ctrl->event_ring = xhci_ring_alloc(ctrl, ERST_NUM_SEGS, false);
  469. ctrl->erst.entries = xhci_malloc(sizeof(struct xhci_erst_entry) *
  470. ERST_NUM_SEGS);
  471. ctrl->erst.num_entries = ERST_NUM_SEGS;
  472. for (val = 0, seg = ctrl->event_ring->first_seg;
  473. val < ERST_NUM_SEGS;
  474. val++) {
  475. struct xhci_erst_entry *entry = &ctrl->erst.entries[val];
  476. trb_64 = xhci_virt_to_bus(ctrl, seg->trbs);
  477. entry->seg_addr = cpu_to_le64(trb_64);
  478. entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
  479. entry->rsvd = 0;
  480. seg = seg->next;
  481. }
  482. xhci_flush_cache((uintptr_t)ctrl->erst.entries,
  483. ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
  484. deq = xhci_virt_to_bus(ctrl, ctrl->event_ring->dequeue);
  485. /* Update HC event ring dequeue pointer */
  486. xhci_writeq(&ctrl->ir_set->erst_dequeue,
  487. (u64)deq & (u64)~ERST_PTR_MASK);
  488. /* set ERST count with the number of entries in the segment table */
  489. val = xhci_readl(&ctrl->ir_set->erst_size);
  490. val &= ERST_SIZE_MASK;
  491. val |= ERST_NUM_SEGS;
  492. xhci_writel(&ctrl->ir_set->erst_size, val);
  493. /* this is the event ring segment table pointer */
  494. val_64 = xhci_readq(&ctrl->ir_set->erst_base);
  495. val_64 &= ERST_PTR_MASK;
  496. val_64 |= xhci_virt_to_bus(ctrl, ctrl->erst.entries) & ~ERST_PTR_MASK;
  497. xhci_writeq(&ctrl->ir_set->erst_base, val_64);
  498. /* set up the scratchpad buffer array and scratchpad buffers */
  499. xhci_scratchpad_alloc(ctrl);
  500. /* initializing the virtual devices to NULL */
  501. for (i = 0; i < MAX_HC_SLOTS; ++i)
  502. ctrl->devs[i] = NULL;
  503. /*
  504. * Just Zero'ing this register completely,
  505. * or some spurious Device Notification Events
  506. * might screw things here.
  507. */
  508. xhci_writel(&hcor->or_dnctrl, 0x0);
  509. return 0;
  510. }
  511. /**
  512. * Give the input control context for the passed container context
  513. *
  514. * @param ctx pointer to the context
  515. * @return pointer to the Input control context data
  516. */
  517. struct xhci_input_control_ctx
  518. *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx)
  519. {
  520. BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
  521. return (struct xhci_input_control_ctx *)ctx->bytes;
  522. }
  523. /**
  524. * Give the slot context for the passed container context
  525. *
  526. * @param ctrl Host controller data structure
  527. * @param ctx pointer to the context
  528. * @return pointer to the slot control context data
  529. */
  530. struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
  531. struct xhci_container_ctx *ctx)
  532. {
  533. if (ctx->type == XHCI_CTX_TYPE_DEVICE)
  534. return (struct xhci_slot_ctx *)ctx->bytes;
  535. return (struct xhci_slot_ctx *)
  536. (ctx->bytes + CTX_SIZE(xhci_readl(&ctrl->hccr->cr_hccparams)));
  537. }
  538. /**
  539. * Gets the EP context from based on the ep_index
  540. *
  541. * @param ctrl Host controller data structure
  542. * @param ctx context container
  543. * @param ep_index index of the endpoint
  544. * @return pointer to the End point context
  545. */
  546. struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
  547. struct xhci_container_ctx *ctx,
  548. unsigned int ep_index)
  549. {
  550. /* increment ep index by offset of start of ep ctx array */
  551. ep_index++;
  552. if (ctx->type == XHCI_CTX_TYPE_INPUT)
  553. ep_index++;
  554. return (struct xhci_ep_ctx *)
  555. (ctx->bytes +
  556. (ep_index * CTX_SIZE(xhci_readl(&ctrl->hccr->cr_hccparams))));
  557. }
  558. /**
  559. * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
  560. * Useful when you want to change one particular aspect of the endpoint
  561. * and then issue a configure endpoint command.
  562. *
  563. * @param ctrl Host controller data structure
  564. * @param in_ctx contains the input context
  565. * @param out_ctx contains the input context
  566. * @param ep_index index of the end point
  567. * @return none
  568. */
  569. void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
  570. struct xhci_container_ctx *in_ctx,
  571. struct xhci_container_ctx *out_ctx,
  572. unsigned int ep_index)
  573. {
  574. struct xhci_ep_ctx *out_ep_ctx;
  575. struct xhci_ep_ctx *in_ep_ctx;
  576. out_ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
  577. in_ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  578. in_ep_ctx->ep_info = out_ep_ctx->ep_info;
  579. in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
  580. in_ep_ctx->deq = out_ep_ctx->deq;
  581. in_ep_ctx->tx_info = out_ep_ctx->tx_info;
  582. }
  583. /**
  584. * Copy output xhci_slot_ctx to the input xhci_slot_ctx.
  585. * Useful when you want to change one particular aspect of the endpoint
  586. * and then issue a configure endpoint command.
  587. * Only the context entries field matters, but
  588. * we'll copy the whole thing anyway.
  589. *
  590. * @param ctrl Host controller data structure
  591. * @param in_ctx contains the inpout context
  592. * @param out_ctx contains the inpout context
  593. * @return none
  594. */
  595. void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx,
  596. struct xhci_container_ctx *out_ctx)
  597. {
  598. struct xhci_slot_ctx *in_slot_ctx;
  599. struct xhci_slot_ctx *out_slot_ctx;
  600. in_slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  601. out_slot_ctx = xhci_get_slot_ctx(ctrl, out_ctx);
  602. in_slot_ctx->dev_info = out_slot_ctx->dev_info;
  603. in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
  604. in_slot_ctx->tt_info = out_slot_ctx->tt_info;
  605. in_slot_ctx->dev_state = out_slot_ctx->dev_state;
  606. }
  607. /**
  608. * Setup an xHCI virtual device for a Set Address command
  609. *
  610. * @param udev pointer to the Device Data Structure
  611. * @return returns negative value on failure else 0 on success
  612. */
  613. void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
  614. struct usb_device *udev, int hop_portnr)
  615. {
  616. struct xhci_virt_device *virt_dev;
  617. struct xhci_ep_ctx *ep0_ctx;
  618. struct xhci_slot_ctx *slot_ctx;
  619. u32 port_num = 0;
  620. u64 trb_64 = 0;
  621. int slot_id = udev->slot_id;
  622. int speed = udev->speed;
  623. int route = 0;
  624. #if CONFIG_IS_ENABLED(DM_USB)
  625. struct usb_device *dev = udev;
  626. struct usb_hub_device *hub;
  627. #endif
  628. virt_dev = ctrl->devs[slot_id];
  629. BUG_ON(!virt_dev);
  630. /* Extract the EP0 and Slot Ctrl */
  631. ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0);
  632. slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
  633. /* Only the control endpoint is valid - one endpoint context */
  634. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
  635. #if CONFIG_IS_ENABLED(DM_USB)
  636. /* Calculate the route string for this device */
  637. port_num = dev->portnr;
  638. while (!usb_hub_is_root_hub(dev->dev)) {
  639. hub = dev_get_uclass_priv(dev->dev);
  640. /*
  641. * Each hub in the topology is expected to have no more than
  642. * 15 ports in order for the route string of a device to be
  643. * unique. SuperSpeed hubs are restricted to only having 15
  644. * ports, but FS/LS/HS hubs are not. The xHCI specification
  645. * says that if the port number the device is greater than 15,
  646. * that portion of the route string shall be set to 15.
  647. */
  648. if (port_num > 15)
  649. port_num = 15;
  650. route |= port_num << (hub->hub_depth * 4);
  651. dev = dev_get_parent_priv(dev->dev);
  652. port_num = dev->portnr;
  653. dev = dev_get_parent_priv(dev->dev->parent);
  654. }
  655. debug("route string %x\n", route);
  656. #endif
  657. slot_ctx->dev_info |= cpu_to_le32(route);
  658. switch (speed) {
  659. case USB_SPEED_SUPER:
  660. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
  661. break;
  662. case USB_SPEED_HIGH:
  663. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
  664. break;
  665. case USB_SPEED_FULL:
  666. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
  667. break;
  668. case USB_SPEED_LOW:
  669. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
  670. break;
  671. default:
  672. /* Speed was set earlier, this shouldn't happen. */
  673. BUG();
  674. }
  675. #if CONFIG_IS_ENABLED(DM_USB)
  676. /* Set up TT fields to support FS/LS devices */
  677. if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
  678. struct udevice *parent = udev->dev;
  679. dev = udev;
  680. do {
  681. port_num = dev->portnr;
  682. dev = dev_get_parent_priv(parent);
  683. if (usb_hub_is_root_hub(dev->dev))
  684. break;
  685. parent = dev->dev->parent;
  686. } while (dev->speed != USB_SPEED_HIGH);
  687. if (!usb_hub_is_root_hub(dev->dev)) {
  688. hub = dev_get_uclass_priv(dev->dev);
  689. if (hub->tt.multi)
  690. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  691. slot_ctx->tt_info |= cpu_to_le32(TT_PORT(port_num));
  692. slot_ctx->tt_info |= cpu_to_le32(TT_SLOT(dev->slot_id));
  693. }
  694. }
  695. #endif
  696. port_num = hop_portnr;
  697. debug("port_num = %d\n", port_num);
  698. slot_ctx->dev_info2 |=
  699. cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) <<
  700. ROOT_HUB_PORT_SHIFT));
  701. /* Step 4 - ring already allocated */
  702. /* Step 5 */
  703. ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
  704. debug("SPEED = %d\n", speed);
  705. switch (speed) {
  706. case USB_SPEED_SUPER:
  707. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
  708. debug("Setting Packet size = 512bytes\n");
  709. break;
  710. case USB_SPEED_HIGH:
  711. /* USB core guesses at a 64-byte max packet first for FS devices */
  712. case USB_SPEED_FULL:
  713. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
  714. debug("Setting Packet size = 64bytes\n");
  715. break;
  716. case USB_SPEED_LOW:
  717. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
  718. debug("Setting Packet size = 8bytes\n");
  719. break;
  720. default:
  721. /* New speed? */
  722. BUG();
  723. }
  724. /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
  725. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
  726. trb_64 = xhci_virt_to_bus(ctrl, virt_dev->eps[0].ring->first_seg->trbs);
  727. ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);
  728. /*
  729. * xHCI spec 6.2.3:
  730. * software shall set 'Average TRB Length' to 8 for control endpoints.
  731. */
  732. ep0_ctx->tx_info = cpu_to_le32(EP_AVG_TRB_LENGTH(8));
  733. /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
  734. xhci_flush_cache((uintptr_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
  735. xhci_flush_cache((uintptr_t)slot_ctx, sizeof(struct xhci_slot_ctx));
  736. }