xhci-dwc3.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. *
  5. * DWC3 controller driver
  6. *
  7. * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
  8. */
  9. #include <clk.h>
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <generic-phy.h>
  13. #include <log.h>
  14. #include <reset.h>
  15. #include <usb.h>
  16. #include <dwc3-uboot.h>
  17. #include <linux/delay.h>
  18. #include <usb/xhci.h>
  19. #include <asm/io.h>
  20. #include <linux/usb/dwc3.h>
  21. #include <linux/usb/otg.h>
  22. struct xhci_dwc3_plat {
  23. struct clk_bulk clks;
  24. struct phy_bulk phys;
  25. struct reset_ctl_bulk resets;
  26. };
  27. void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
  28. {
  29. clrsetbits_le32(&dwc3_reg->g_ctl,
  30. DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
  31. DWC3_GCTL_PRTCAPDIR(mode));
  32. }
  33. static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
  34. {
  35. /* Assert USB3 PHY reset */
  36. setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  37. /* Assert USB2 PHY reset */
  38. setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  39. mdelay(100);
  40. /* Clear USB3 PHY reset */
  41. clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  42. /* Clear USB2 PHY reset */
  43. clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  44. }
  45. void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
  46. {
  47. /* Before Resetting PHY, put Core in Reset */
  48. setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  49. /* reset USB3 phy - if required */
  50. dwc3_phy_reset(dwc3_reg);
  51. mdelay(100);
  52. /* After PHYs are stable we can take Core out of reset state */
  53. clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  54. }
  55. int dwc3_core_init(struct dwc3 *dwc3_reg)
  56. {
  57. u32 reg;
  58. u32 revision;
  59. unsigned int dwc3_hwparams1;
  60. revision = readl(&dwc3_reg->g_snpsid);
  61. /* This should read as U3 followed by revision number */
  62. if ((revision & DWC3_GSNPSID_MASK) != 0x55330000 &&
  63. (revision & DWC3_GSNPSID_MASK) != 0x33310000) {
  64. puts("this is not a DesignWare USB3 DRD Core\n");
  65. return -1;
  66. }
  67. dwc3_core_soft_reset(dwc3_reg);
  68. dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
  69. reg = readl(&dwc3_reg->g_ctl);
  70. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  71. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  72. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
  73. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  74. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  75. break;
  76. default:
  77. debug("No power optimization available\n");
  78. }
  79. /*
  80. * WORKAROUND: DWC3 revisions <1.90a have a bug
  81. * where the device can fail to connect at SuperSpeed
  82. * and falls back to high-speed mode which causes
  83. * the device to enter a Connect/Disconnect loop
  84. */
  85. if ((revision & DWC3_REVISION_MASK) < 0x190a)
  86. reg |= DWC3_GCTL_U2RSTECN;
  87. writel(reg, &dwc3_reg->g_ctl);
  88. return 0;
  89. }
  90. void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
  91. {
  92. setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
  93. GFLADJ_30MHZ(val));
  94. }
  95. #if CONFIG_IS_ENABLED(DM_USB)
  96. static int xhci_dwc3_reset_init(struct udevice *dev,
  97. struct xhci_dwc3_plat *plat)
  98. {
  99. int ret;
  100. ret = reset_get_bulk(dev, &plat->resets);
  101. if (ret == -ENOTSUPP || ret == -ENOENT)
  102. return 0;
  103. else if (ret)
  104. return ret;
  105. ret = reset_deassert_bulk(&plat->resets);
  106. if (ret) {
  107. reset_release_bulk(&plat->resets);
  108. return ret;
  109. }
  110. return 0;
  111. }
  112. static int xhci_dwc3_clk_init(struct udevice *dev,
  113. struct xhci_dwc3_plat *plat)
  114. {
  115. int ret;
  116. ret = clk_get_bulk(dev, &plat->clks);
  117. if (ret == -ENOSYS || ret == -ENOENT)
  118. return 0;
  119. if (ret)
  120. return ret;
  121. ret = clk_enable_bulk(&plat->clks);
  122. if (ret) {
  123. clk_release_bulk(&plat->clks);
  124. return ret;
  125. }
  126. return 0;
  127. }
  128. static int xhci_dwc3_probe(struct udevice *dev)
  129. {
  130. struct xhci_hcor *hcor;
  131. struct xhci_hccr *hccr;
  132. struct dwc3 *dwc3_reg;
  133. enum usb_dr_mode dr_mode;
  134. struct xhci_dwc3_plat *plat = dev_get_plat(dev);
  135. const char *phy;
  136. u32 reg;
  137. int ret;
  138. ret = xhci_dwc3_reset_init(dev, plat);
  139. if (ret)
  140. return ret;
  141. ret = xhci_dwc3_clk_init(dev, plat);
  142. if (ret)
  143. return ret;
  144. hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
  145. hcor = (struct xhci_hcor *)((uintptr_t)hccr +
  146. HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
  147. ret = dwc3_setup_phy(dev, &plat->phys);
  148. if (ret && (ret != -ENOTSUPP))
  149. return ret;
  150. dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
  151. dwc3_core_init(dwc3_reg);
  152. /* Set dwc3 usb2 phy config */
  153. reg = readl(&dwc3_reg->g_usb2phycfg[0]);
  154. phy = dev_read_string(dev, "phy_type");
  155. if (phy && strcmp(phy, "utmi_wide") == 0) {
  156. reg |= DWC3_GUSB2PHYCFG_PHYIF;
  157. reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
  158. reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
  159. }
  160. if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
  161. reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  162. if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
  163. reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  164. if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
  165. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  166. writel(reg, &dwc3_reg->g_usb2phycfg[0]);
  167. dr_mode = usb_get_dr_mode(dev_ofnode(dev));
  168. if (dr_mode == USB_DR_MODE_UNKNOWN)
  169. /* by default set dual role mode to HOST */
  170. dr_mode = USB_DR_MODE_HOST;
  171. dwc3_set_mode(dwc3_reg, dr_mode);
  172. return xhci_register(dev, hccr, hcor);
  173. }
  174. static int xhci_dwc3_remove(struct udevice *dev)
  175. {
  176. struct xhci_dwc3_plat *plat = dev_get_plat(dev);
  177. dwc3_shutdown_phy(dev, &plat->phys);
  178. clk_release_bulk(&plat->clks);
  179. reset_release_bulk(&plat->resets);
  180. return xhci_deregister(dev);
  181. }
  182. static const struct udevice_id xhci_dwc3_ids[] = {
  183. { .compatible = "snps,dwc3" },
  184. { }
  185. };
  186. U_BOOT_DRIVER(xhci_dwc3) = {
  187. .name = "xhci-dwc3",
  188. .id = UCLASS_USB,
  189. .of_match = xhci_dwc3_ids,
  190. .probe = xhci_dwc3_probe,
  191. .remove = xhci_dwc3_remove,
  192. .ops = &xhci_usb_ops,
  193. .priv_auto = sizeof(struct xhci_ctrl),
  194. .plat_auto = sizeof(struct xhci_dwc3_plat),
  195. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  196. };
  197. #endif