ehci-mx6.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  4. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <log.h>
  9. #include <usb.h>
  10. #include <errno.h>
  11. #include <wait_bit.h>
  12. #include <asm/global_data.h>
  13. #include <linux/compiler.h>
  14. #include <linux/delay.h>
  15. #include <usb/ehci-ci.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/mach-imx/sys_proto.h>
  21. #include <dm.h>
  22. #include <asm/mach-types.h>
  23. #include <power/regulator.h>
  24. #include <linux/usb/otg.h>
  25. #include <linux/usb/phy.h>
  26. #include "ehci.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #define USB_OTGREGS_OFFSET 0x000
  29. #define USB_H1REGS_OFFSET 0x200
  30. #define USB_H2REGS_OFFSET 0x400
  31. #define USB_H3REGS_OFFSET 0x600
  32. #define USB_OTHERREGS_OFFSET 0x800
  33. #define USB_H1_CTRL_OFFSET 0x04
  34. #define USBPHY_CTRL 0x00000030
  35. #define USBPHY_CTRL_SET 0x00000034
  36. #define USBPHY_CTRL_CLR 0x00000038
  37. #define USBPHY_CTRL_TOG 0x0000003c
  38. #define USBPHY_PWD 0x00000000
  39. #define USBPHY_CTRL_SFTRST 0x80000000
  40. #define USBPHY_CTRL_CLKGATE 0x40000000
  41. #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
  42. #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
  43. #define USBPHY_CTRL_OTG_ID 0x08000000
  44. #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
  45. #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
  46. #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
  47. #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
  48. #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
  49. #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
  50. #define USBNC_OFFSET 0x200
  51. #define USBNC_PHY_STATUS_OFFSET 0x23C
  52. #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
  53. #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
  54. #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
  55. #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
  56. #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
  57. /* USBCMD */
  58. #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
  59. #define UCMD_RESET (1 << 1) /* controller reset */
  60. /* If this is not defined, assume MX6/MX7/MX8M SoC default */
  61. #ifndef CONFIG_MXC_USB_PORTSC
  62. #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  63. #endif
  64. /* Base address for this IP block is 0x02184800 */
  65. struct usbnc_regs {
  66. u32 ctrl[4]; /* otg/host1-3 */
  67. u32 uh2_hsic_ctrl;
  68. u32 uh3_hsic_ctrl;
  69. u32 otg_phy_ctrl_0;
  70. u32 uh1_phy_ctrl_0;
  71. u32 reserve1[4];
  72. u32 phy_cfg1;
  73. u32 phy_cfg2;
  74. u32 reserve2;
  75. u32 phy_status;
  76. u32 reserve3[4];
  77. u32 adp_cfg1;
  78. u32 adp_cfg2;
  79. u32 adp_status;
  80. };
  81. #if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
  82. static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
  83. int anatop_bits_index)
  84. {
  85. void __iomem *chrg_detect;
  86. void __iomem *pll_480_ctrl_clr;
  87. void __iomem *pll_480_ctrl_set;
  88. if (!is_mx6())
  89. return;
  90. switch (anatop_bits_index) {
  91. case 0:
  92. chrg_detect = &anatop->usb1_chrg_detect;
  93. pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
  94. pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
  95. break;
  96. case 1:
  97. chrg_detect = &anatop->usb2_chrg_detect;
  98. pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
  99. pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
  100. break;
  101. default:
  102. return;
  103. }
  104. /*
  105. * Some phy and power's special controls
  106. * 1. The external charger detector needs to be disabled
  107. * or the signal at DP will be poor
  108. * 2. The PLL's power and output to usb
  109. * is totally controlled by IC, so the Software only needs
  110. * to enable them at initializtion.
  111. */
  112. writel(ANADIG_USB2_CHRG_DETECT_EN_B |
  113. ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
  114. chrg_detect);
  115. writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
  116. pll_480_ctrl_clr);
  117. writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
  118. ANADIG_USB2_PLL_480_CTRL_POWER |
  119. ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
  120. pll_480_ctrl_set);
  121. }
  122. #else
  123. static void __maybe_unused
  124. usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
  125. #endif
  126. #if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
  127. static void usb_power_config_mx7(struct usbnc_regs *usbnc)
  128. {
  129. void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
  130. if (!is_mx7())
  131. return;
  132. /*
  133. * Clear the ACAENB to enable usb_otg_id detection,
  134. * otherwise it is the ACA detection enabled.
  135. */
  136. clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
  137. }
  138. #else
  139. static void __maybe_unused
  140. usb_power_config_mx7(void *usbnc) { }
  141. #endif
  142. #if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
  143. static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
  144. {
  145. if (!is_mx7ulp())
  146. return;
  147. writel(ANADIG_USB2_CHRG_DETECT_EN_B |
  148. ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
  149. &usbphy->usb1_chrg_detect);
  150. scg_enable_usb_pll(true);
  151. }
  152. #else
  153. static void __maybe_unused
  154. usb_power_config_mx7ulp(void *usbphy) { }
  155. #endif
  156. #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
  157. static const unsigned phy_bases[] = {
  158. USB_PHY0_BASE_ADDR,
  159. #if defined(USB_PHY1_BASE_ADDR)
  160. USB_PHY1_BASE_ADDR,
  161. #endif
  162. };
  163. #if !defined(CONFIG_PHY)
  164. static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
  165. {
  166. phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
  167. writel(USBPHY_CTRL_CLKGATE, phy_reg);
  168. }
  169. /* Return 0 : host node, <>0 : device mode */
  170. static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
  171. {
  172. void __iomem *phy_ctrl;
  173. void __iomem *usb_cmd;
  174. int ret;
  175. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  176. usb_cmd = (void __iomem *)&ehci->usbcmd;
  177. /* Stop then Reset */
  178. clrbits_le32(usb_cmd, UCMD_RUN_STOP);
  179. ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
  180. if (ret)
  181. return ret;
  182. setbits_le32(usb_cmd, UCMD_RESET);
  183. ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
  184. if (ret)
  185. return ret;
  186. /* Reset USBPHY module */
  187. setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
  188. udelay(10);
  189. /* Remove CLKGATE and SFTRST */
  190. clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
  191. udelay(10);
  192. /* Power up the PHY */
  193. writel(0, phy_reg + USBPHY_PWD);
  194. /* enable FS/LS device */
  195. setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
  196. USBPHY_CTRL_ENUTMILEVEL3);
  197. return 0;
  198. }
  199. #endif
  200. int usb_phy_mode(int port)
  201. {
  202. void __iomem *phy_reg;
  203. void __iomem *phy_ctrl;
  204. u32 val;
  205. phy_reg = (void __iomem *)phy_bases[port];
  206. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  207. val = readl(phy_ctrl);
  208. if (val & USBPHY_CTRL_OTG_ID)
  209. return USB_INIT_DEVICE;
  210. else
  211. return USB_INIT_HOST;
  212. }
  213. #elif defined(CONFIG_MX7)
  214. int usb_phy_mode(int port)
  215. {
  216. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  217. (0x10000 * port) + USBNC_OFFSET);
  218. void __iomem *status = (void __iomem *)(&usbnc->phy_status);
  219. u32 val;
  220. val = readl(status);
  221. if (val & USBNC_PHYSTATUS_ID_DIG)
  222. return USB_INIT_DEVICE;
  223. else
  224. return USB_INIT_HOST;
  225. }
  226. #endif
  227. #if !defined(CONFIG_PHY)
  228. /* Should be done in the MXS PHY driver */
  229. static void usb_oc_config(struct usbnc_regs *usbnc, int index)
  230. {
  231. void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
  232. #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
  233. /* mx6qarm2 seems to required a different setting*/
  234. clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  235. #else
  236. setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  237. #endif
  238. setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
  239. /* Set power polarity to high active */
  240. #ifdef CONFIG_MXC_USB_OTG_HACTIVE
  241. setbits_le32(ctrl, UCTRL_PWR_POL);
  242. #else
  243. clrbits_le32(ctrl, UCTRL_PWR_POL);
  244. #endif
  245. }
  246. #endif
  247. #if !CONFIG_IS_ENABLED(DM_USB)
  248. /**
  249. * board_usb_phy_mode - override usb phy mode
  250. * @port: usb host/otg port
  251. *
  252. * Target board specific, override usb_phy_mode.
  253. * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
  254. * left disconnected in this case usb_phy_mode will not be able to identify
  255. * the phy mode that usb port is used.
  256. * Machine file overrides board_usb_phy_mode.
  257. *
  258. * Return: USB_INIT_DEVICE or USB_INIT_HOST
  259. */
  260. int __weak board_usb_phy_mode(int port)
  261. {
  262. return usb_phy_mode(port);
  263. }
  264. /**
  265. * board_ehci_hcd_init - set usb vbus voltage
  266. * @port: usb otg port
  267. *
  268. * Target board specific, setup iomux pad to setup supply vbus voltage
  269. * for usb otg port. Machine board file overrides board_ehci_hcd_init
  270. *
  271. * Return: 0 Success
  272. */
  273. int __weak board_ehci_hcd_init(int port)
  274. {
  275. return 0;
  276. }
  277. /**
  278. * board_ehci_power - enables/disables usb vbus voltage
  279. * @port: usb otg port
  280. * @on: on/off vbus voltage
  281. *
  282. * Enables/disables supply vbus voltage for usb otg port.
  283. * Machine board file overrides board_ehci_power
  284. *
  285. * Return: 0 Success
  286. */
  287. int __weak board_ehci_power(int port, int on)
  288. {
  289. return 0;
  290. }
  291. int ehci_hcd_init(int index, enum usb_init_type init,
  292. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  293. {
  294. enum usb_init_type type;
  295. #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
  296. u32 controller_spacing = 0x200;
  297. struct anatop_regs __iomem *anatop =
  298. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  299. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  300. USB_OTHERREGS_OFFSET);
  301. #elif defined(CONFIG_MX7)
  302. u32 controller_spacing = 0x10000;
  303. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  304. (0x10000 * index) + USBNC_OFFSET);
  305. #elif defined(CONFIG_MX7ULP)
  306. u32 controller_spacing = 0x10000;
  307. struct usbphy_regs __iomem *usbphy =
  308. (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
  309. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  310. (0x10000 * index) + USBNC_OFFSET);
  311. #endif
  312. struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
  313. (controller_spacing * index));
  314. int ret;
  315. if (index > 3)
  316. return -EINVAL;
  317. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  318. if (usb_fused((ulong)ehci)) {
  319. printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
  320. (ulong)ehci);
  321. return -ENODEV;
  322. }
  323. }
  324. enable_usboh3_clk(1);
  325. mdelay(1);
  326. /* Do board specific initialization */
  327. ret = board_ehci_hcd_init(index);
  328. if (ret) {
  329. enable_usboh3_clk(0);
  330. return ret;
  331. }
  332. #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
  333. usb_power_config_mx6(anatop, index);
  334. #elif defined (CONFIG_MX7)
  335. usb_power_config_mx7(usbnc);
  336. #elif defined (CONFIG_MX7ULP)
  337. usb_power_config_mx7ulp(usbphy);
  338. #endif
  339. usb_oc_config(usbnc, index);
  340. #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
  341. if (index < ARRAY_SIZE(phy_bases)) {
  342. usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
  343. usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
  344. }
  345. #endif
  346. type = board_usb_phy_mode(index);
  347. if (hccr && hcor) {
  348. *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
  349. *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
  350. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  351. }
  352. if ((type == init) || (type == USB_INIT_DEVICE))
  353. board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
  354. if (type != init)
  355. return -ENODEV;
  356. if (type == USB_INIT_DEVICE)
  357. return 0;
  358. setbits_le32(&ehci->usbmode, CM_HOST);
  359. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  360. setbits_le32(&ehci->portsc, USB_EN);
  361. mdelay(10);
  362. return 0;
  363. }
  364. int ehci_hcd_stop(int index)
  365. {
  366. return 0;
  367. }
  368. #else
  369. struct ehci_mx6_priv_data {
  370. struct ehci_ctrl ctrl;
  371. struct usb_ehci *ehci;
  372. struct udevice *vbus_supply;
  373. struct clk clk;
  374. struct phy phy;
  375. enum usb_init_type init_type;
  376. enum usb_phy_interface phy_type;
  377. #if !defined(CONFIG_PHY)
  378. int portnr;
  379. void __iomem *phy_addr;
  380. void __iomem *misc_addr;
  381. void __iomem *anatop_addr;
  382. #endif
  383. };
  384. static u32 mx6_portsc(enum usb_phy_interface phy_type)
  385. {
  386. switch (phy_type) {
  387. case USBPHY_INTERFACE_MODE_UTMI:
  388. return PORT_PTS_UTMI;
  389. case USBPHY_INTERFACE_MODE_UTMIW:
  390. return PORT_PTS_UTMI | PORT_PTS_PTW;
  391. case USBPHY_INTERFACE_MODE_ULPI:
  392. return PORT_PTS_ULPI;
  393. case USBPHY_INTERFACE_MODE_SERIAL:
  394. return PORT_PTS_SERIAL;
  395. case USBPHY_INTERFACE_MODE_HSIC:
  396. return PORT_PTS_HSIC;
  397. default:
  398. return CONFIG_MXC_USB_PORTSC;
  399. }
  400. }
  401. static int mx6_init_after_reset(struct ehci_ctrl *dev)
  402. {
  403. struct ehci_mx6_priv_data *priv = dev->priv;
  404. enum usb_init_type type = priv->init_type;
  405. struct usb_ehci *ehci = priv->ehci;
  406. #if !defined(CONFIG_PHY)
  407. usb_power_config_mx6(priv->anatop_addr, priv->portnr);
  408. usb_power_config_mx7(priv->misc_addr);
  409. usb_power_config_mx7ulp(priv->phy_addr);
  410. usb_oc_config(priv->misc_addr, priv->portnr);
  411. #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
  412. usb_internal_phy_clock_gate(priv->phy_addr, 1);
  413. usb_phy_enable(ehci, priv->phy_addr);
  414. #endif
  415. #endif
  416. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  417. if (priv->vbus_supply) {
  418. int ret;
  419. ret = regulator_set_enable(priv->vbus_supply,
  420. (type == USB_INIT_DEVICE) ?
  421. false : true);
  422. if (ret && ret != -ENOSYS) {
  423. printf("Error enabling VBUS supply (ret=%i)\n", ret);
  424. return ret;
  425. }
  426. }
  427. #endif
  428. if (type == USB_INIT_DEVICE)
  429. return 0;
  430. setbits_le32(&ehci->usbmode, CM_HOST);
  431. writel(mx6_portsc(priv->phy_type), &ehci->portsc);
  432. setbits_le32(&ehci->portsc, USB_EN);
  433. mdelay(10);
  434. return 0;
  435. }
  436. static const struct ehci_ops mx6_ehci_ops = {
  437. .init_after_reset = mx6_init_after_reset
  438. };
  439. static int ehci_usb_phy_mode(struct udevice *dev)
  440. {
  441. struct usb_plat *plat = dev_get_plat(dev);
  442. void *__iomem addr = dev_read_addr_ptr(dev);
  443. void *__iomem phy_ctrl, *__iomem phy_status;
  444. const void *blob = gd->fdt_blob;
  445. int offset = dev_of_offset(dev), phy_off;
  446. u32 val;
  447. /*
  448. * About fsl,usbphy, Refer to
  449. * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
  450. */
  451. if (is_mx6() || is_mx7ulp() || is_imxrt()) {
  452. phy_off = fdtdec_lookup_phandle(blob,
  453. offset,
  454. "fsl,usbphy");
  455. if (phy_off < 0)
  456. return -EINVAL;
  457. addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
  458. "reg");
  459. if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
  460. return -EINVAL;
  461. phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
  462. val = readl(phy_ctrl);
  463. if (val & USBPHY_CTRL_OTG_ID)
  464. plat->init_type = USB_INIT_DEVICE;
  465. else
  466. plat->init_type = USB_INIT_HOST;
  467. } else if (is_mx7()) {
  468. phy_status = (void __iomem *)(addr +
  469. USBNC_PHY_STATUS_OFFSET);
  470. val = readl(phy_status);
  471. if (val & USBNC_PHYSTATUS_ID_DIG)
  472. plat->init_type = USB_INIT_DEVICE;
  473. else
  474. plat->init_type = USB_INIT_HOST;
  475. } else {
  476. return -EINVAL;
  477. }
  478. return 0;
  479. }
  480. static int ehci_usb_of_to_plat(struct udevice *dev)
  481. {
  482. struct usb_plat *plat = dev_get_plat(dev);
  483. enum usb_dr_mode dr_mode;
  484. dr_mode = usb_get_dr_mode(dev_ofnode(dev));
  485. switch (dr_mode) {
  486. case USB_DR_MODE_HOST:
  487. plat->init_type = USB_INIT_HOST;
  488. break;
  489. case USB_DR_MODE_PERIPHERAL:
  490. plat->init_type = USB_INIT_DEVICE;
  491. break;
  492. case USB_DR_MODE_OTG:
  493. case USB_DR_MODE_UNKNOWN:
  494. return ehci_usb_phy_mode(dev);
  495. };
  496. return 0;
  497. }
  498. static int mx6_parse_dt_addrs(struct udevice *dev)
  499. {
  500. #if !defined(CONFIG_PHY)
  501. struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
  502. int phy_off, misc_off;
  503. const void *blob = gd->fdt_blob;
  504. int offset = dev_of_offset(dev);
  505. void *__iomem addr;
  506. phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
  507. if (phy_off < 0) {
  508. phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
  509. if (phy_off < 0)
  510. return -EINVAL;
  511. }
  512. misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
  513. if (misc_off < 0)
  514. return -EINVAL;
  515. addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
  516. if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
  517. addr = NULL;
  518. priv->phy_addr = addr;
  519. addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
  520. if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
  521. return -EINVAL;
  522. priv->misc_addr = addr;
  523. #if defined(CONFIG_MX6)
  524. int anatop_off, ret, devnump;
  525. ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
  526. phy_off, &devnump);
  527. if (ret < 0)
  528. return ret;
  529. priv->portnr = devnump;
  530. /* Resolve ANATOP offset through USB PHY node */
  531. anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
  532. if (anatop_off < 0)
  533. return -EINVAL;
  534. addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
  535. if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
  536. return -EINVAL;
  537. priv->anatop_addr = addr;
  538. #endif
  539. #endif
  540. return 0;
  541. }
  542. static int ehci_usb_probe(struct udevice *dev)
  543. {
  544. struct usb_plat *plat = dev_get_plat(dev);
  545. struct usb_ehci *ehci = dev_read_addr_ptr(dev);
  546. struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
  547. enum usb_init_type type = plat->init_type;
  548. struct ehci_hccr *hccr;
  549. struct ehci_hcor *hcor;
  550. int ret;
  551. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  552. if (usb_fused((ulong)ehci)) {
  553. printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
  554. (ulong)ehci);
  555. return -ENODEV;
  556. }
  557. }
  558. ret = mx6_parse_dt_addrs(dev);
  559. if (ret)
  560. return ret;
  561. priv->ehci = ehci;
  562. priv->init_type = type;
  563. priv->phy_type = usb_get_phy_mode(dev_ofnode(dev));
  564. #if CONFIG_IS_ENABLED(CLK)
  565. ret = clk_get_by_index(dev, 0, &priv->clk);
  566. if (ret < 0)
  567. return ret;
  568. ret = clk_enable(&priv->clk);
  569. if (ret)
  570. return ret;
  571. #else
  572. /* Compatibility with DM_USB and !CLK */
  573. enable_usboh3_clk(1);
  574. mdelay(1);
  575. #endif
  576. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  577. ret = device_get_supply_regulator(dev, "vbus-supply",
  578. &priv->vbus_supply);
  579. if (ret)
  580. debug("%s: No vbus supply\n", dev->name);
  581. #endif
  582. #if !defined(CONFIG_PHY)
  583. usb_power_config_mx6(priv->anatop_addr, priv->portnr);
  584. usb_power_config_mx7(priv->misc_addr);
  585. usb_power_config_mx7ulp(priv->phy_addr);
  586. usb_oc_config(priv->misc_addr, priv->portnr);
  587. #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
  588. usb_internal_phy_clock_gate(priv->phy_addr, 1);
  589. usb_phy_enable(ehci, priv->phy_addr);
  590. #endif
  591. #endif
  592. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  593. if (priv->vbus_supply) {
  594. ret = regulator_set_enable(priv->vbus_supply,
  595. (type == USB_INIT_DEVICE) ?
  596. false : true);
  597. if (ret && ret != -ENOSYS) {
  598. printf("Error enabling VBUS supply (ret=%i)\n", ret);
  599. goto err_clk;
  600. }
  601. }
  602. #endif
  603. if (priv->init_type == USB_INIT_HOST) {
  604. setbits_le32(&ehci->usbmode, CM_HOST);
  605. writel(mx6_portsc(priv->phy_type), &ehci->portsc);
  606. setbits_le32(&ehci->portsc, USB_EN);
  607. }
  608. mdelay(10);
  609. #if defined(CONFIG_PHY)
  610. ret = ehci_setup_phy(dev, &priv->phy, 0);
  611. if (ret)
  612. goto err_regulator;
  613. #endif
  614. hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
  615. hcor = (struct ehci_hcor *)((uintptr_t)hccr +
  616. HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
  617. ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
  618. if (ret)
  619. goto err_phy;
  620. return ret;
  621. err_phy:
  622. #if defined(CONFIG_PHY)
  623. ehci_shutdown_phy(dev, &priv->phy);
  624. err_regulator:
  625. #endif
  626. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  627. if (priv->vbus_supply)
  628. regulator_set_enable(priv->vbus_supply, false);
  629. err_clk:
  630. #endif
  631. #if CONFIG_IS_ENABLED(CLK)
  632. clk_disable(&priv->clk);
  633. #else
  634. /* Compatibility with DM_USB and !CLK */
  635. enable_usboh3_clk(0);
  636. #endif
  637. return ret;
  638. }
  639. int ehci_usb_remove(struct udevice *dev)
  640. {
  641. struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
  642. ehci_deregister(dev);
  643. #if defined(CONFIG_PHY)
  644. ehci_shutdown_phy(dev, &priv->phy);
  645. #endif
  646. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  647. if (priv->vbus_supply)
  648. regulator_set_enable(priv->vbus_supply, false);
  649. #endif
  650. #if CONFIG_IS_ENABLED(CLK)
  651. clk_disable(&priv->clk);
  652. #endif
  653. return 0;
  654. }
  655. static const struct udevice_id mx6_usb_ids[] = {
  656. { .compatible = "fsl,imx27-usb" },
  657. { .compatible = "fsl,imx7d-usb" },
  658. { .compatible = "fsl,imxrt-usb" },
  659. { }
  660. };
  661. U_BOOT_DRIVER(usb_mx6) = {
  662. .name = "ehci_mx6",
  663. .id = UCLASS_USB,
  664. .of_match = mx6_usb_ids,
  665. .of_to_plat = ehci_usb_of_to_plat,
  666. .probe = ehci_usb_probe,
  667. .remove = ehci_usb_remove,
  668. .ops = &ehci_usb_ops,
  669. .plat_auto = sizeof(struct usb_plat),
  670. .priv_auto = sizeof(struct ehci_mx6_priv_data),
  671. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  672. };
  673. #endif