phy-sun50i-usb3.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Allwinner sun50i(H6) USB 3.0 phy driver
  4. *
  5. * Copyright (C) 2020 Samuel Holland <samuel@sholland.org>
  6. *
  7. * Based on the Linux driver, which is:
  8. *
  9. * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
  10. *
  11. * Based on phy-sun9i-usb.c, which is:
  12. *
  13. * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
  14. *
  15. * Based on code from Allwinner BSP, which is:
  16. *
  17. * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
  18. */
  19. #include <asm/io.h>
  20. #include <clk.h>
  21. #include <dm.h>
  22. #include <dm/device_compat.h>
  23. #include <generic-phy.h>
  24. #include <linux/bitops.h>
  25. #include <reset.h>
  26. /* Interface Status and Control Registers */
  27. #define SUNXI_ISCR 0x00
  28. #define SUNXI_PIPE_CLOCK_CONTROL 0x14
  29. #define SUNXI_PHY_TUNE_LOW 0x18
  30. #define SUNXI_PHY_TUNE_HIGH 0x1c
  31. #define SUNXI_PHY_EXTERNAL_CONTROL 0x20
  32. /* USB2.0 Interface Status and Control Register */
  33. #define SUNXI_ISCR_FORCE_VBUS (3 << 12)
  34. /* PIPE Clock Control Register */
  35. #define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6)
  36. /* PHY External Control Register */
  37. #define SUNXI_PEC_EXTERN_VBUS (3 << 1)
  38. #define SUNXI_PEC_SSC_EN (1 << 24)
  39. #define SUNXI_PEC_REF_SSP_EN (1 << 26)
  40. /* PHY Tune High Register */
  41. #define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19)
  42. #define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19)
  43. #define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13)
  44. #define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13)
  45. #define SUNXI_TX_SWING_FULL(n) ((n) << 6)
  46. #define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6)
  47. #define SUNXI_LOS_BIAS(n) ((n) << 3)
  48. #define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
  49. #define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
  50. #define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0)
  51. struct sun50i_usb3_phy_priv {
  52. void __iomem *regs;
  53. struct reset_ctl reset;
  54. struct clk clk;
  55. };
  56. static void sun50i_usb3_phy_open(struct sun50i_usb3_phy_priv *phy)
  57. {
  58. u32 val;
  59. val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
  60. val |= SUNXI_PEC_EXTERN_VBUS;
  61. val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
  62. writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
  63. val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
  64. val |= SUNXI_PCC_PIPE_CLK_OPEN;
  65. writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
  66. val = readl(phy->regs + SUNXI_ISCR);
  67. val |= SUNXI_ISCR_FORCE_VBUS;
  68. writel(val, phy->regs + SUNXI_ISCR);
  69. /*
  70. * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
  71. * registers are directly taken from the BSP USB3 driver from
  72. * Allwiner.
  73. */
  74. writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
  75. val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
  76. val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
  77. SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
  78. SUNXI_TX_DEEMPH_3P5DB_MASK);
  79. val |= SUNXI_TXVBOOSTLVL(0x7);
  80. val |= SUNXI_LOS_BIAS(0x7);
  81. val |= SUNXI_TX_SWING_FULL(0x55);
  82. val |= SUNXI_TX_DEEMPH_6DB(0x20);
  83. val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
  84. writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
  85. }
  86. static int sun50i_usb3_phy_init(struct phy *phy)
  87. {
  88. struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev);
  89. int ret;
  90. ret = clk_prepare_enable(&priv->clk);
  91. if (ret)
  92. return ret;
  93. ret = reset_deassert(&priv->reset);
  94. if (ret) {
  95. clk_disable_unprepare(&priv->clk);
  96. return ret;
  97. }
  98. sun50i_usb3_phy_open(priv);
  99. return 0;
  100. }
  101. static int sun50i_usb3_phy_exit(struct phy *phy)
  102. {
  103. struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev);
  104. reset_assert(&priv->reset);
  105. clk_disable_unprepare(&priv->clk);
  106. return 0;
  107. }
  108. static const struct phy_ops sun50i_usb3_phy_ops = {
  109. .init = sun50i_usb3_phy_init,
  110. .exit = sun50i_usb3_phy_exit,
  111. };
  112. static int sun50i_usb3_phy_probe(struct udevice *dev)
  113. {
  114. struct sun50i_usb3_phy_priv *priv = dev_get_priv(dev);
  115. int ret;
  116. ret = clk_get_by_index(dev, 0, &priv->clk);
  117. if (ret) {
  118. dev_err(dev, "failed to get phy clock\n");
  119. return ret;
  120. }
  121. ret = reset_get_by_index(dev, 0, &priv->reset);
  122. if (ret) {
  123. dev_err(dev, "failed to get reset control\n");
  124. return ret;
  125. }
  126. priv->regs = (void __iomem *)dev_read_addr(dev);
  127. if (IS_ERR(priv->regs))
  128. return PTR_ERR(priv->regs);
  129. return 0;
  130. }
  131. static const struct udevice_id sun50i_usb3_phy_ids[] = {
  132. { .compatible = "allwinner,sun50i-h6-usb3-phy" },
  133. { },
  134. };
  135. U_BOOT_DRIVER(sun50i_usb3_phy) = {
  136. .name = "sun50i-usb3-phy",
  137. .id = UCLASS_PHY,
  138. .of_match = sun50i_usb3_phy_ids,
  139. .ops = &sun50i_usb3_phy_ops,
  140. .probe = sun50i_usb3_phy_probe,
  141. .priv_auto = sizeof(struct sun50i_usb3_phy_priv),
  142. };