// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ #include #include #include #include #include #include #include #include #include #include #include #define SYS_IOMUX_DOEN(gpio, oen) \ clrsetbits_le32(SYS_IOMUX_BASE+GPIO_OFFSET(gpio), \ GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \ (oen) << GPIO_SHIFT(gpio)) #define SYS_IOMUX_DOUT(gpio, gpo) \ clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DOUT + GPIO_OFFSET(gpio),\ GPIO_DOUT_MASK << GPIO_SHIFT(gpio),\ ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio)) #define SYS_IOMUX_DIN(gpio, gpi)\ clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DIN + GPIO_OFFSET(gpi),\ GPIO_DIN_MASK << GPIO_SHIFT(gpi),\ ((gpio+2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) #define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) do {\ SYS_IOMUX_DOEN(gpio, oen);\ SYS_IOMUX_DOUT(gpio, gpo);\ SYS_IOMUX_DIN(gpio, gpi); }while(0) #define SYS_CLOCK_ENABLE(clk) \ setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK) static void sys_reset_clear(ulong assert, ulong status, u32 rst) { volatile u32 value; clrbits_le32(SYS_CRG_BASE + assert, BIT(rst)); do{ value = in_le32(SYS_CRG_BASE + status); }while((value & BIT(rst)) != BIT(rst)); } static void jh7110_timer_init(void) { SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT); SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT); SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT); SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT); SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT); sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT); sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT); sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT); sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT); sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT); } static void jh7110_gmac_init(int id) { switch (id) { case 0: clrsetbits_le32(AON_SYSCON_BASE + AON_SYSCFG_12, GMAC5_0_SEL_I_MASK, BIT(GMAC5_0_SEL_I_SHIFT) & GMAC5_0_SEL_I_MASK); break; case 1: clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_144, GMAC5_1_SEL_I_MASK, BIT(GMAC5_1_SEL_I_SHIFT) & GMAC5_1_SEL_I_MASK); break; default: break; } } static void jh7110_usb_init(void) { clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, USB_MODE_STRAP_MASK, (2<