Ashok Reddy Soma
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e32d891659
watchdog: versal: Include header file needed for dev_ functions
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2 years ago |
Michal Simek
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9b7aac7536
clk: zynq: Add dummy clock enable function
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3 years ago |
Simon Glass
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8b85dfc675
dm: Avoid accessing seq directly
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3 years ago |
Simon Glass
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8a8d24bdf1
dm: treewide: Rename ..._platdata variables to just ..._plat
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3 years ago |
Simon Glass
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d1998a9fde
dm: treewide: Rename ofdata_to_platdata() to of_to_plat()
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3 years ago |
Simon Glass
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c69cda25c9
dm: treewide: Rename dev_get_platdata() to dev_get_plat()
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3 years ago |
Simon Glass
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caa4daa2ae
dm: treewide: Rename 'platdata' variables to just 'plat'
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3 years ago |
Simon Glass
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41575d8e4c
dm: treewide: Rename auto_alloc_size members to be shorter
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3 years ago |
Ashok Reddy Soma
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5028358a6a
watchdog: versal: Add support for Xilinx window watchdog
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4 years ago |