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@@ -4,21 +4,41 @@
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*
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* Copyright 2011, 2013 Freescale Semiconductor, Inc.
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* author Andy Fleming
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+ * Copyright (c) 2019 Michael Walle <michael@walle.cc>
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*/
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#include <common.h>
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#include <phy.h>
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+#include <dm/device_compat.h>
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+#include <linux/bitfield.h>
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+#include <dt-bindings/net/qca-ar803x.h>
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#define AR803x_PHY_DEBUG_ADDR_REG 0x1d
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#define AR803x_PHY_DEBUG_DATA_REG 0x1e
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+/* Debug registers */
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+#define AR803x_DEBUG_REG_0 0x0
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+#define AR803x_RGMII_RX_CLK_DLY BIT(15)
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+
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#define AR803x_DEBUG_REG_5 0x5
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#define AR803x_RGMII_TX_CLK_DLY BIT(8)
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-#define AR803x_DEBUG_REG_0 0x0
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-#define AR803x_RGMII_RX_CLK_DLY BIT(15)
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+#define AR803x_DEBUG_REG_1F 0x1f
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+#define AR803x_PLL_ON BIT(2)
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+#define AR803x_RGMII_1V8 BIT(3)
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/* CLK_25M register is at MMD 7, address 0x8016 */
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#define AR803x_CLK_25M_SEL_REG 0x8016
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+
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+#define AR803x_CLK_25M_MASK GENMASK(4, 2)
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+#define AR803x_CLK_25M_25MHZ_XTAL 0
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+#define AR803x_CLK_25M_25MHZ_DSP 1
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+#define AR803x_CLK_25M_50MHZ_PLL 2
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+#define AR803x_CLK_25M_50MHZ_DSP 3
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+#define AR803x_CLK_25M_62_5MHZ_PLL 4
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+#define AR803x_CLK_25M_62_5MHZ_DSP 5
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+#define AR803x_CLK_25M_125MHZ_PLL 6
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+#define AR803x_CLK_25M_125MHZ_DSP 7
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+
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/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
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#define AR8035_CLK_25M_FREQ_25M (0 | 0)
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#define AR8035_CLK_25M_FREQ_50M (0 | BIT(3))
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@@ -26,10 +46,23 @@
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#define AR8035_CLK_25M_FREQ_125M (BIT(4) | BIT(3))
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#define AR8035_CLK_25M_MASK GENMASK(4, 3)
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+#define AR803x_CLK_25M_DR_MASK GENMASK(8, 7)
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+#define AR803x_CLK_25M_DR_FULL 0
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+#define AR803x_CLK_25M_DR_HALF 1
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+#define AR803x_CLK_25M_DR_QUARTER 2
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+
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#define AR8021_PHY_ID 0x004dd040
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#define AR8031_PHY_ID 0x004dd074
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#define AR8035_PHY_ID 0x004dd072
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+struct ar803x_priv {
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+ int flags;
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+#define AR803x_FLAG_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */
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+#define AR803x_FLAG_RGMII_1V8 BIT(1) /* use 1.8V RGMII I/O voltage */
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+ u16 clk_25m_reg;
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+ u16 clk_25m_mask;
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+};
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+
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static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg)
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{
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int ret;
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@@ -113,14 +146,193 @@ static int ar803x_delay_config(struct phy_device *phydev)
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return ret;
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}
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+static int ar803x_regs_config(struct phy_device *phydev)
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+{
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+ struct ar803x_priv *priv = phydev->priv;
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+ u16 set = 0, clear = 0;
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+ int val;
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+ int ret;
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+
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+ /* no configuration available */
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+ if (!priv)
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+ return 0;
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+
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+ /*
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+ * Only supported on the AR8031, AR8035 has strappings for the PLL mode
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+ * as well as the RGMII voltage.
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+ */
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+ if (phydev->drv->uid == AR8031_PHY_ID) {
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+ if (priv->flags & AR803x_FLAG_KEEP_PLL_ENABLED)
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+ set |= AR803x_PLL_ON;
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+ else
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+ clear |= AR803x_PLL_ON;
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+
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+ if (priv->flags & AR803x_FLAG_RGMII_1V8)
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+ set |= AR803x_RGMII_1V8;
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+ else
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+ clear |= AR803x_RGMII_1V8;
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+
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+ ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_1F, clear,
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+ set);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ /* save the write access if the mask is empty */
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+ if (priv->clk_25m_mask) {
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+ val = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
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+ if (val < 0)
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+ return val;
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+ val &= ~priv->clk_25m_mask;
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+ val |= priv->clk_25m_reg;
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+ ret = phy_write_mmd(phydev, MDIO_MMD_AN,
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+ AR803x_CLK_25M_SEL_REG, val);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static int ar803x_of_init(struct phy_device *phydev)
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+{
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+#if defined(CONFIG_DM_ETH)
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+ struct ar803x_priv *priv;
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+ ofnode node, vddio_reg_node;
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+ u32 strength, freq, min_uV, max_uV;
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+ int sel;
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+
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+ node = phy_get_ofnode(phydev);
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+ if (!ofnode_valid(node))
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+ return -EINVAL;
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+
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+ priv = malloc(sizeof(*priv));
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+ if (!priv)
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+ return -ENOMEM;
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+ memset(priv, 0, sizeof(*priv));
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+
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+ phydev->priv = priv;
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+
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+ debug("%s: found PHY node: %s\n", __func__, ofnode_get_name(node));
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+
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+ if (ofnode_read_bool(node, "qca,keep-pll-enabled"))
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+ priv->flags |= AR803x_FLAG_KEEP_PLL_ENABLED;
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+
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+ /*
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+ * We can't use the regulator framework because the regulator is
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+ * a subnode of the PHY. So just read the two properties we are
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+ * interested in.
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+ */
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+ vddio_reg_node = ofnode_find_subnode(node, "vddio-regulator");
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+ if (ofnode_valid(vddio_reg_node)) {
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+ min_uV = ofnode_read_u32_default(vddio_reg_node,
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+ "regulator-min-microvolt", 0);
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+ max_uV = ofnode_read_u32_default(vddio_reg_node,
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+ "regulator-max-microvolt", 0);
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+
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+ if (min_uV != max_uV) {
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+ free(priv);
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+ return -EINVAL;
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+ }
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+
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+ switch (min_uV) {
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+ case 1500000:
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+ break;
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+ case 1800000:
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+ priv->flags |= AR803x_FLAG_RGMII_1V8;
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+ break;
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+ default:
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+ free(priv);
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+ return -EINVAL;
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+ }
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+ }
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+
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+ /*
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+ * Get the CLK_25M frequency from the device tree. Only XTAL and PLL
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+ * sources are supported right now. There is also the possibilty to use
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+ * the DSP as frequency reference, this is used for synchronous
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+ * ethernet.
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+ */
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+ if (!ofnode_read_u32(node, "qca,clk-out-frequency", &freq)) {
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+ switch (freq) {
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+ case 25000000:
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+ sel = AR803x_CLK_25M_25MHZ_XTAL;
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+ break;
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+ case 50000000:
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+ sel = AR803x_CLK_25M_50MHZ_PLL;
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+ break;
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+ case 62500000:
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+ sel = AR803x_CLK_25M_62_5MHZ_PLL;
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+ break;
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+ case 125000000:
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+ sel = AR803x_CLK_25M_125MHZ_PLL;
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+ break;
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+ default:
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+ dev_err(phydev->dev,
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+ "invalid qca,clk-out-frequency\n");
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+ free(priv);
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+ return -EINVAL;
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+ }
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+
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+ priv->clk_25m_mask |= AR803x_CLK_25M_MASK;
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+ priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_MASK, sel);
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+ /*
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+ * Fixup for the AR8035 which only has two bits. The two
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+ * remaining bits map to the same frequencies.
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+ */
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+ if (phydev->drv->uid == AR8035_PHY_ID) {
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+ u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
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+
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+ priv->clk_25m_mask &= ~clear;
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+ priv->clk_25m_reg &= ~clear;
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+ }
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+ }
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+
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+ if (phydev->drv->uid == AR8031_PHY_ID &&
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+ !ofnode_read_u32(node, "qca,clk-out-strength", &strength)) {
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+ switch (strength) {
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+ case AR803X_STRENGTH_FULL:
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+ sel = AR803x_CLK_25M_DR_FULL;
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+ break;
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+ case AR803X_STRENGTH_HALF:
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+ sel = AR803x_CLK_25M_DR_HALF;
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+ break;
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+ case AR803X_STRENGTH_QUARTER:
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+ sel = AR803x_CLK_25M_DR_QUARTER;
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+ break;
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+ default:
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+ dev_err(phydev->dev,
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+ "invalid qca,clk-out-strength\n");
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+ free(priv);
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+ return -EINVAL;
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+ }
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+ priv->clk_25m_mask |= AR803x_CLK_25M_DR_MASK;
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+ priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_DR_MASK, sel);
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+ }
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+
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+ debug("%s: flags=%x clk_25m_reg=%04x clk_25m_mask=%04x\n", __func__,
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+ priv->flags, priv->clk_25m_reg, priv->clk_25m_mask);
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+#endif
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+
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+ return 0;
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+}
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+
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static int ar8031_config(struct phy_device *phydev)
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{
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int ret;
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+ ret = ar803x_of_init(phydev);
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+ if (ret < 0)
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+ return ret;
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+
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ret = ar803x_delay_config(phydev);
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if (ret < 0)
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return ret;
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+ ret = ar803x_regs_config(phydev);
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+ if (ret < 0)
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+ return ret;
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+
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phydev->supported = phydev->drv->features;
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genphy_config_aneg(phydev);
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@@ -134,6 +346,10 @@ static int ar8035_config(struct phy_device *phydev)
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int ret;
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int regval;
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+ ret = ar803x_of_init(phydev);
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+ if (ret < 0)
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+ return ret;
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+
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/* Configure CLK_25M output clock at 125 MHz */
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regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
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regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
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@@ -144,6 +360,10 @@ static int ar8035_config(struct phy_device *phydev)
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if (ret < 0)
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return ret;
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+ ret = ar803x_regs_config(phydev);
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+ if (ret < 0)
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+ return ret;
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+
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phydev->supported = phydev->drv->features;
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genphy_config_aneg(phydev);
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