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@@ -0,0 +1,1707 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
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+ * Copyright 2019 NXP Semiconductors
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+ * Andy Fleming
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+ * Yangbo Lu <yangbo.lu@nxp.com>
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+ *
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+ * Based vaguely on the pxa mmc code:
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+ * (C) Copyright 2003
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+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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+ */
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+
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+#include <config.h>
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+#include <common.h>
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+#include <command.h>
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+#include <clk.h>
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+#include <errno.h>
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+#include <hwconfig.h>
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+#include <mmc.h>
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+#include <part.h>
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+#include <power/regulator.h>
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+#include <malloc.h>
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+#include <fsl_esdhc_imx.h>
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+#include <fdt_support.h>
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+#include <asm/io.h>
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+#include <dm.h>
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+#include <asm-generic/gpio.h>
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+#include <dm/pinctrl.h>
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+
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+#if !CONFIG_IS_ENABLED(BLK)
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+#include "mmc_private.h"
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+#endif
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
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+ IRQSTATEN_CINT | \
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+ IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
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+ IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
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+ IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
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+ IRQSTATEN_DINT)
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+#define MAX_TUNING_LOOP 40
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+#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
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+
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+struct fsl_esdhc {
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+ uint dsaddr; /* SDMA system address register */
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+ uint blkattr; /* Block attributes register */
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+ uint cmdarg; /* Command argument register */
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+ uint xfertyp; /* Transfer type register */
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+ uint cmdrsp0; /* Command response 0 register */
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+ uint cmdrsp1; /* Command response 1 register */
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+ uint cmdrsp2; /* Command response 2 register */
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+ uint cmdrsp3; /* Command response 3 register */
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+ uint datport; /* Buffer data port register */
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+ uint prsstat; /* Present state register */
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+ uint proctl; /* Protocol control register */
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+ uint sysctl; /* System Control Register */
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+ uint irqstat; /* Interrupt status register */
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+ uint irqstaten; /* Interrupt status enable register */
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+ uint irqsigen; /* Interrupt signal enable register */
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+ uint autoc12err; /* Auto CMD error status register */
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+ uint hostcapblt; /* Host controller capabilities register */
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+ uint wml; /* Watermark level register */
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+ uint mixctrl; /* For USDHC */
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+ char reserved1[4]; /* reserved */
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+ uint fevt; /* Force event register */
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+ uint admaes; /* ADMA error status register */
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+ uint adsaddr; /* ADMA system address register */
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+ char reserved2[4];
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+ uint dllctrl;
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+ uint dllstat;
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+ uint clktunectrlstatus;
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+ char reserved3[4];
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+ uint strobe_dllctrl;
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+ uint strobe_dllstat;
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+ char reserved4[72];
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+ uint vendorspec;
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+ uint mmcboot;
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+ uint vendorspec2;
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+ uint tuning_ctrl; /* on i.MX6/7/8 */
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+ char reserved5[44];
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+ uint hostver; /* Host controller version register */
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+ char reserved6[4]; /* reserved */
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+ uint dmaerraddr; /* DMA error address register */
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+ char reserved7[4]; /* reserved */
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+ uint dmaerrattr; /* DMA error attribute register */
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+ char reserved8[4]; /* reserved */
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+ uint hostcapblt2; /* Host controller capabilities register 2 */
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+ char reserved9[8]; /* reserved */
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+ uint tcr; /* Tuning control register */
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+ char reserved10[28]; /* reserved */
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+ uint sddirctl; /* SD direction control register */
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+ char reserved11[712];/* reserved */
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+ uint scr; /* eSDHC control register */
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+};
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+
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+struct fsl_esdhc_plat {
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+ struct mmc_config cfg;
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+ struct mmc mmc;
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+};
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+
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+struct esdhc_soc_data {
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+ u32 flags;
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+ u32 caps;
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+};
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+
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+/**
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+ * struct fsl_esdhc_priv
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+ *
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+ * @esdhc_regs: registers of the sdhc controller
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+ * @sdhc_clk: Current clk of the sdhc controller
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+ * @bus_width: bus width, 1bit, 4bit or 8bit
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+ * @cfg: mmc config
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+ * @mmc: mmc
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+ * Following is used when Driver Model is enabled for MMC
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+ * @dev: pointer for the device
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+ * @non_removable: 0: removable; 1: non-removable
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+ * @wp_enable: 1: enable checking wp; 0: no check
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+ * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
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+ * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
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+ * @caps: controller capabilities
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+ * @tuning_step: tuning step setting in tuning_ctrl register
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+ * @start_tuning_tap: the start point for tuning in tuning_ctrl register
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+ * @strobe_dll_delay_target: settings in strobe_dllctrl
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+ * @signal_voltage: indicating the current voltage
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+ * @cd_gpio: gpio for card detection
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+ * @wp_gpio: gpio for write protection
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+ */
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+struct fsl_esdhc_priv {
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+ struct fsl_esdhc *esdhc_regs;
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+ unsigned int sdhc_clk;
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+ struct clk per_clk;
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+ unsigned int clock;
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+ unsigned int mode;
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+ unsigned int bus_width;
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+#if !CONFIG_IS_ENABLED(BLK)
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+ struct mmc *mmc;
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+#endif
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+ struct udevice *dev;
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+ int non_removable;
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+ int wp_enable;
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+ int vs18_enable;
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+ u32 flags;
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+ u32 caps;
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+ u32 tuning_step;
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+ u32 tuning_start_tap;
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+ u32 strobe_dll_delay_target;
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+ u32 signal_voltage;
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+#if IS_ENABLED(CONFIG_DM_REGULATOR)
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+ struct udevice *vqmmc_dev;
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+ struct udevice *vmmc_dev;
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+#endif
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+#ifdef CONFIG_DM_GPIO
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+ struct gpio_desc cd_gpio;
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+ struct gpio_desc wp_gpio;
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+#endif
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+};
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+
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+/* Return the XFERTYP flags for a given command and data packet */
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+static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
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+{
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+ uint xfertyp = 0;
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+
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+ if (data) {
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+ xfertyp |= XFERTYP_DPSEL;
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+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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+ xfertyp |= XFERTYP_DMAEN;
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+#endif
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+ if (data->blocks > 1) {
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+ xfertyp |= XFERTYP_MSBSEL;
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+ xfertyp |= XFERTYP_BCEN;
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+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
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+ xfertyp |= XFERTYP_AC12EN;
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+#endif
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+ }
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+
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+ if (data->flags & MMC_DATA_READ)
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+ xfertyp |= XFERTYP_DTDSEL;
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+ }
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+
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+ if (cmd->resp_type & MMC_RSP_CRC)
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+ xfertyp |= XFERTYP_CCCEN;
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+ if (cmd->resp_type & MMC_RSP_OPCODE)
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+ xfertyp |= XFERTYP_CICEN;
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+ if (cmd->resp_type & MMC_RSP_136)
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+ xfertyp |= XFERTYP_RSPTYP_136;
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+ else if (cmd->resp_type & MMC_RSP_BUSY)
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+ xfertyp |= XFERTYP_RSPTYP_48_BUSY;
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+ else if (cmd->resp_type & MMC_RSP_PRESENT)
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+ xfertyp |= XFERTYP_RSPTYP_48;
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+
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+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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+ xfertyp |= XFERTYP_CMDTYP_ABORT;
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+
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+ return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
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+}
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+
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+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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+/*
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+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
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+ */
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+static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
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+ struct mmc_data *data)
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+{
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+ struct fsl_esdhc *regs = priv->esdhc_regs;
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+ uint blocks;
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+ char *buffer;
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+ uint databuf;
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+ uint size;
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+ uint irqstat;
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+ ulong start;
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+
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+ if (data->flags & MMC_DATA_READ) {
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+ blocks = data->blocks;
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+ buffer = data->dest;
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+ while (blocks) {
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+ start = get_timer(0);
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+ size = data->blocksize;
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+ irqstat = esdhc_read32(®s->irqstat);
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+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
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+ if (get_timer(start) > PIO_TIMEOUT) {
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+ printf("\nData Read Failed in PIO Mode.");
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+ return;
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+ }
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+ }
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+ while (size && (!(irqstat & IRQSTAT_TC))) {
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+ udelay(100); /* Wait before last byte transfer complete */
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+ irqstat = esdhc_read32(®s->irqstat);
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+ databuf = in_le32(®s->datport);
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+ *((uint *)buffer) = databuf;
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+ buffer += 4;
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+ size -= 4;
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+ }
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+ blocks--;
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+ }
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+ } else {
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+ blocks = data->blocks;
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+ buffer = (char *)data->src;
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+ while (blocks) {
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+ start = get_timer(0);
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+ size = data->blocksize;
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+ irqstat = esdhc_read32(®s->irqstat);
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+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
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+ if (get_timer(start) > PIO_TIMEOUT) {
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+ printf("\nData Write Failed in PIO Mode.");
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+ return;
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+ }
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+ }
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+ while (size && (!(irqstat & IRQSTAT_TC))) {
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+ udelay(100); /* Wait before last byte transfer complete */
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+ databuf = *((uint *)buffer);
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+ buffer += 4;
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+ size -= 4;
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+ irqstat = esdhc_read32(®s->irqstat);
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+ out_le32(®s->datport, databuf);
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+ }
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+ blocks--;
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+ }
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+ }
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+}
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+#endif
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+
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+static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
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+ struct mmc_data *data)
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+{
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+ int timeout;
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+ struct fsl_esdhc *regs = priv->esdhc_regs;
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+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
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+ defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
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+ dma_addr_t addr;
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+#endif
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+ uint wml_value;
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+
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+ wml_value = data->blocksize/4;
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+
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+ if (data->flags & MMC_DATA_READ) {
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+ if (wml_value > WML_RD_WML_MAX)
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+ wml_value = WML_RD_WML_MAX_VAL;
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+
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+ esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
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+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
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+ defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
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+ addr = virt_to_phys((void *)(data->dest));
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+ if (upper_32_bits(addr))
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+ printf("Error found for upper 32 bits\n");
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+ else
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+ esdhc_write32(®s->dsaddr, lower_32_bits(addr));
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+#else
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+ esdhc_write32(®s->dsaddr, (u32)data->dest);
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+#endif
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+#endif
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+ } else {
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+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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+ flush_dcache_range((ulong)data->src,
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+ (ulong)data->src+data->blocks
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+ *data->blocksize);
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+#endif
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+ if (wml_value > WML_WR_WML_MAX)
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+ wml_value = WML_WR_WML_MAX_VAL;
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+ if (priv->wp_enable) {
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+ if ((esdhc_read32(®s->prsstat) &
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+ PRSSTAT_WPSPL) == 0) {
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+ printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
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+ return -ETIMEDOUT;
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+ }
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+ } else {
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+#ifdef CONFIG_DM_GPIO
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+ if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
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+ printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
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+ return -ETIMEDOUT;
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+ }
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+#endif
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+ }
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+
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+ esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
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+ wml_value << 16);
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+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
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+ defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
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+ addr = virt_to_phys((void *)(data->src));
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+ if (upper_32_bits(addr))
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+ printf("Error found for upper 32 bits\n");
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+ else
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+ esdhc_write32(®s->dsaddr, lower_32_bits(addr));
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+#else
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+ esdhc_write32(®s->dsaddr, (u32)data->src);
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+#endif
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+#endif
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+ }
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+
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+ esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
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+
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+ /* Calculate the timeout period for data transactions */
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+ /*
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+ * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
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+ * 2)Timeout period should be minimum 0.250sec as per SD Card spec
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+ * So, Number of SD Clock cycles for 0.25sec should be minimum
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+ * (SD Clock/sec * 0.25 sec) SD Clock cycles
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+ * = (mmc->clock * 1/4) SD Clock cycles
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+ * As 1) >= 2)
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+ * => (2^(timeout+13)) >= mmc->clock * 1/4
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+ * Taking log2 both the sides
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+ * => timeout + 13 >= log2(mmc->clock/4)
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+ * Rounding up to next power of 2
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+ * => timeout + 13 = log2(mmc->clock/4) + 1
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+ * => timeout + 13 = fls(mmc->clock/4)
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+ *
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+ * However, the MMC spec "It is strongly recommended for hosts to
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+ * implement more than 500ms timeout value even if the card
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+ * indicates the 250ms maximum busy length." Even the previous
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+ * value of 300ms is known to be insufficient for some cards.
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+ * So, we use
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+ * => timeout + 13 = fls(mmc->clock/2)
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+ */
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+ timeout = fls(mmc->clock/2);
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+ timeout -= 13;
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+
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+ if (timeout > 14)
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+ timeout = 14;
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+
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+ if (timeout < 0)
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+ timeout = 0;
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+
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+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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+ if ((timeout == 4) || (timeout == 8) || (timeout == 12))
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+ timeout++;
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+#endif
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+
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+#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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+ timeout = 0xE;
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+#endif
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+ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
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+
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+ return 0;
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+}
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+
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+static void check_and_invalidate_dcache_range
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+ (struct mmc_cmd *cmd,
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+ struct mmc_data *data) {
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+ unsigned start = 0;
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+ unsigned end = 0;
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+ unsigned size = roundup(ARCH_DMA_MINALIGN,
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+ data->blocks*data->blocksize);
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|
|
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
|
|
|
+ defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
|
|
|
+ dma_addr_t addr;
|
|
|
+
|
|
|
+ addr = virt_to_phys((void *)(data->dest));
|
|
|
+ if (upper_32_bits(addr))
|
|
|
+ printf("Error found for upper 32 bits\n");
|
|
|
+ else
|
|
|
+ start = lower_32_bits(addr);
|
|
|
+#else
|
|
|
+ start = (unsigned)data->dest;
|
|
|
+#endif
|
|
|
+ end = start + size;
|
|
|
+ invalidate_dcache_range(start, end);
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef CONFIG_MCF5441x
|
|
|
+/*
|
|
|
+ * Swaps 32-bit words to little-endian byte order.
|
|
|
+ */
|
|
|
+static inline void sd_swap_dma_buff(struct mmc_data *data)
|
|
|
+{
|
|
|
+ int i, size = data->blocksize >> 2;
|
|
|
+ u32 *buffer = (u32 *)data->dest;
|
|
|
+ u32 sw;
|
|
|
+
|
|
|
+ while (data->blocks--) {
|
|
|
+ for (i = 0; i < size; i++) {
|
|
|
+ sw = __sw32(*buffer);
|
|
|
+ *buffer++ = sw;
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+/*
|
|
|
+ * Sends a command out on the bus. Takes the mmc pointer,
|
|
|
+ * a command pointer, and an optional data pointer.
|
|
|
+ */
|
|
|
+static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|
|
+ struct mmc_cmd *cmd, struct mmc_data *data)
|
|
|
+{
|
|
|
+ int err = 0;
|
|
|
+ uint xfertyp;
|
|
|
+ uint irqstat;
|
|
|
+ u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ unsigned long start;
|
|
|
+
|
|
|
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
|
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
|
|
|
+ return 0;
|
|
|
+#endif
|
|
|
+
|
|
|
+ esdhc_write32(®s->irqstat, -1);
|
|
|
+
|
|
|
+ sync();
|
|
|
+
|
|
|
+ /* Wait for the bus to be idle */
|
|
|
+ while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
|
|
|
+ (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
|
|
|
+ ;
|
|
|
+
|
|
|
+ while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
|
|
|
+ ;
|
|
|
+
|
|
|
+ /* Wait at least 8 SD clock cycles before the next command */
|
|
|
+ /*
|
|
|
+ * Note: This is way more than 8 cycles, but 1ms seems to
|
|
|
+ * resolve timing issues with some cards
|
|
|
+ */
|
|
|
+ udelay(1000);
|
|
|
+
|
|
|
+ /* Set up for a data transfer if we have one */
|
|
|
+ if (data) {
|
|
|
+ err = esdhc_setup_data(priv, mmc, data);
|
|
|
+ if(err)
|
|
|
+ return err;
|
|
|
+
|
|
|
+ if (data->flags & MMC_DATA_READ)
|
|
|
+ check_and_invalidate_dcache_range(cmd, data);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Figure out the transfer arguments */
|
|
|
+ xfertyp = esdhc_xfertyp(cmd, data);
|
|
|
+
|
|
|
+ /* Mask all irqs */
|
|
|
+ esdhc_write32(®s->irqsigen, 0);
|
|
|
+
|
|
|
+ /* Send the command */
|
|
|
+ esdhc_write32(®s->cmdarg, cmd->cmdarg);
|
|
|
+#if defined(CONFIG_FSL_USDHC)
|
|
|
+ esdhc_write32(®s->mixctrl,
|
|
|
+ (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
|
|
|
+ | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
|
|
|
+ esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
|
|
|
+#else
|
|
|
+ esdhc_write32(®s->xfertyp, xfertyp);
|
|
|
+#endif
|
|
|
+
|
|
|
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
|
|
|
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
|
|
|
+ flags = IRQSTAT_BRR;
|
|
|
+
|
|
|
+ /* Wait for the command to complete */
|
|
|
+ start = get_timer(0);
|
|
|
+ while (!(esdhc_read32(®s->irqstat) & flags)) {
|
|
|
+ if (get_timer(start) > 1000) {
|
|
|
+ err = -ETIMEDOUT;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ irqstat = esdhc_read32(®s->irqstat);
|
|
|
+
|
|
|
+ if (irqstat & CMD_ERR) {
|
|
|
+ err = -ECOMM;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (irqstat & IRQSTAT_CTOE) {
|
|
|
+ err = -ETIMEDOUT;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Switch voltage to 1.8V if CMD11 succeeded */
|
|
|
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
|
|
|
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
|
|
+
|
|
|
+ printf("Run CMD11 1.8V switch\n");
|
|
|
+ /* Sleep for 5 ms - max time for card to switch to 1.8V */
|
|
|
+ udelay(5000);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Workaround for ESDHC errata ENGcm03648 */
|
|
|
+ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
|
|
|
+ int timeout = 6000;
|
|
|
+
|
|
|
+ /* Poll on DATA0 line for cmd with busy signal for 600 ms */
|
|
|
+ while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
|
|
|
+ PRSSTAT_DAT0)) {
|
|
|
+ udelay(100);
|
|
|
+ timeout--;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (timeout <= 0) {
|
|
|
+ printf("Timeout waiting for DAT0 to go high!\n");
|
|
|
+ err = -ETIMEDOUT;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Copy the response to the response buffer */
|
|
|
+ if (cmd->resp_type & MMC_RSP_136) {
|
|
|
+ u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
|
|
|
+
|
|
|
+ cmdrsp3 = esdhc_read32(®s->cmdrsp3);
|
|
|
+ cmdrsp2 = esdhc_read32(®s->cmdrsp2);
|
|
|
+ cmdrsp1 = esdhc_read32(®s->cmdrsp1);
|
|
|
+ cmdrsp0 = esdhc_read32(®s->cmdrsp0);
|
|
|
+ cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
|
|
|
+ cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
|
|
|
+ cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
|
|
|
+ cmd->response[3] = (cmdrsp0 << 8);
|
|
|
+ } else
|
|
|
+ cmd->response[0] = esdhc_read32(®s->cmdrsp0);
|
|
|
+
|
|
|
+ /* Wait until all of the blocks are transferred */
|
|
|
+ if (data) {
|
|
|
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
|
|
+ esdhc_pio_read_write(priv, data);
|
|
|
+#else
|
|
|
+ flags = DATA_COMPLETE;
|
|
|
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
|
|
|
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
|
|
|
+ flags = IRQSTAT_BRR;
|
|
|
+ }
|
|
|
+
|
|
|
+ do {
|
|
|
+ irqstat = esdhc_read32(®s->irqstat);
|
|
|
+
|
|
|
+ if (irqstat & IRQSTAT_DTOE) {
|
|
|
+ err = -ETIMEDOUT;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (irqstat & DATA_ERR) {
|
|
|
+ err = -ECOMM;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+ } while ((irqstat & flags) != flags);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Need invalidate the dcache here again to avoid any
|
|
|
+ * cache-fill during the DMA operations such as the
|
|
|
+ * speculative pre-fetching etc.
|
|
|
+ */
|
|
|
+ if (data->flags & MMC_DATA_READ) {
|
|
|
+ check_and_invalidate_dcache_range(cmd, data);
|
|
|
+#ifdef CONFIG_MCF5441x
|
|
|
+ sd_swap_dma_buff(data);
|
|
|
+#endif
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ }
|
|
|
+
|
|
|
+out:
|
|
|
+ /* Reset CMD and DATA portions on error */
|
|
|
+ if (err) {
|
|
|
+ esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
|
|
|
+ SYSCTL_RSTC);
|
|
|
+ while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
|
|
|
+ ;
|
|
|
+
|
|
|
+ if (data) {
|
|
|
+ esdhc_write32(®s->sysctl,
|
|
|
+ esdhc_read32(®s->sysctl) |
|
|
|
+ SYSCTL_RSTD);
|
|
|
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
|
|
|
+ ;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* If this was CMD11, then notify that power cycle is needed */
|
|
|
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
|
|
|
+ printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ esdhc_write32(®s->irqstat, -1);
|
|
|
+
|
|
|
+ return err;
|
|
|
+}
|
|
|
+
|
|
|
+static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
|
|
|
+{
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ int div = 1;
|
|
|
+#ifdef ARCH_MXC
|
|
|
+#ifdef CONFIG_MX53
|
|
|
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
|
|
|
+ int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
|
|
|
+#else
|
|
|
+ int pre_div = 1;
|
|
|
+#endif
|
|
|
+#else
|
|
|
+ int pre_div = 2;
|
|
|
+#endif
|
|
|
+ int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
|
|
|
+ int sdhc_clk = priv->sdhc_clk;
|
|
|
+ uint clk;
|
|
|
+
|
|
|
+ if (clock < mmc->cfg->f_min)
|
|
|
+ clock = mmc->cfg->f_min;
|
|
|
+
|
|
|
+ while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
|
|
|
+ pre_div *= 2;
|
|
|
+
|
|
|
+ while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
|
|
|
+ div++;
|
|
|
+
|
|
|
+ pre_div >>= 1;
|
|
|
+ div -= 1;
|
|
|
+
|
|
|
+ clk = (pre_div << 8) | (div << 4);
|
|
|
+
|
|
|
+#ifdef CONFIG_FSL_USDHC
|
|
|
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
|
|
|
+#else
|
|
|
+ esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
|
|
|
+#endif
|
|
|
+
|
|
|
+ esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
|
|
|
+
|
|
|
+ udelay(10000);
|
|
|
+
|
|
|
+#ifdef CONFIG_FSL_USDHC
|
|
|
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
|
|
|
+#else
|
|
|
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
|
|
|
+#endif
|
|
|
+
|
|
|
+ priv->clock = clock;
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
|
|
+static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
|
|
|
+{
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ u32 value;
|
|
|
+ u32 time_out;
|
|
|
+
|
|
|
+ value = esdhc_read32(®s->sysctl);
|
|
|
+
|
|
|
+ if (enable)
|
|
|
+ value |= SYSCTL_CKEN;
|
|
|
+ else
|
|
|
+ value &= ~SYSCTL_CKEN;
|
|
|
+
|
|
|
+ esdhc_write32(®s->sysctl, value);
|
|
|
+
|
|
|
+ time_out = 20;
|
|
|
+ value = PRSSTAT_SDSTB;
|
|
|
+ while (!(esdhc_read32(®s->prsstat) & value)) {
|
|
|
+ if (time_out == 0) {
|
|
|
+ printf("fsl_esdhc: Internal clock never stabilised.\n");
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ time_out--;
|
|
|
+ mdelay(1);
|
|
|
+ }
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef MMC_SUPPORTS_TUNING
|
|
|
+static int esdhc_change_pinstate(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ switch (priv->mode) {
|
|
|
+ case UHS_SDR50:
|
|
|
+ case UHS_DDR50:
|
|
|
+ ret = pinctrl_select_state(dev, "state_100mhz");
|
|
|
+ break;
|
|
|
+ case UHS_SDR104:
|
|
|
+ case MMC_HS_200:
|
|
|
+ case MMC_HS_400:
|
|
|
+ ret = pinctrl_select_state(dev, "state_200mhz");
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ ret = pinctrl_select_state(dev, "default");
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (ret)
|
|
|
+ printf("%s %d error\n", __func__, priv->mode);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void esdhc_reset_tuning(struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+
|
|
|
+ if (priv->flags & ESDHC_FLAG_USDHC) {
|
|
|
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
|
|
|
+ esdhc_clrbits32(®s->autoc12err,
|
|
|
+ MIX_CTRL_SMPCLK_SEL |
|
|
|
+ MIX_CTRL_EXE_TUNE);
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void esdhc_set_strobe_dll(struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
|
|
|
+ writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * enable strobe dll ctrl and adjust the delay target
|
|
|
+ * for the uSDHC loopback read clock
|
|
|
+ */
|
|
|
+ val = ESDHC_STROBE_DLL_CTRL_ENABLE |
|
|
|
+ (priv->strobe_dll_delay_target <<
|
|
|
+ ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
|
|
|
+ writel(val, ®s->strobe_dllctrl);
|
|
|
+ /* wait 1us to make sure strobe dll status register stable */
|
|
|
+ mdelay(1);
|
|
|
+ val = readl(®s->strobe_dllstat);
|
|
|
+ if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
|
|
|
+ pr_warn("HS400 strobe DLL status REF not lock!\n");
|
|
|
+ if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
|
|
|
+ pr_warn("HS400 strobe DLL status SLV not lock!\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static int esdhc_set_timing(struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ u32 mixctrl;
|
|
|
+
|
|
|
+ mixctrl = readl(®s->mixctrl);
|
|
|
+ mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
|
|
|
+
|
|
|
+ switch (mmc->selected_mode) {
|
|
|
+ case MMC_LEGACY:
|
|
|
+ case SD_LEGACY:
|
|
|
+ esdhc_reset_tuning(mmc);
|
|
|
+ writel(mixctrl, ®s->mixctrl);
|
|
|
+ break;
|
|
|
+ case MMC_HS_400:
|
|
|
+ mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
|
|
|
+ writel(mixctrl, ®s->mixctrl);
|
|
|
+ esdhc_set_strobe_dll(mmc);
|
|
|
+ break;
|
|
|
+ case MMC_HS:
|
|
|
+ case MMC_HS_52:
|
|
|
+ case MMC_HS_200:
|
|
|
+ case SD_HS:
|
|
|
+ case UHS_SDR12:
|
|
|
+ case UHS_SDR25:
|
|
|
+ case UHS_SDR50:
|
|
|
+ case UHS_SDR104:
|
|
|
+ writel(mixctrl, ®s->mixctrl);
|
|
|
+ break;
|
|
|
+ case UHS_DDR50:
|
|
|
+ case MMC_DDR_52:
|
|
|
+ mixctrl |= MIX_CTRL_DDREN;
|
|
|
+ writel(mixctrl, ®s->mixctrl);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ printf("Not supported %d\n", mmc->selected_mode);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ priv->mode = mmc->selected_mode;
|
|
|
+
|
|
|
+ return esdhc_change_pinstate(mmc->dev);
|
|
|
+}
|
|
|
+
|
|
|
+static int esdhc_set_voltage(struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ priv->signal_voltage = mmc->signal_voltage;
|
|
|
+ switch (mmc->signal_voltage) {
|
|
|
+ case MMC_SIGNAL_VOLTAGE_330:
|
|
|
+ if (priv->vs18_enable)
|
|
|
+ return -EIO;
|
|
|
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
|
|
+ if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
|
|
|
+ ret = regulator_set_value(priv->vqmmc_dev, 3300000);
|
|
|
+ if (ret) {
|
|
|
+ printf("Setting to 3.3V error");
|
|
|
+ return -EIO;
|
|
|
+ }
|
|
|
+ /* Wait for 5ms */
|
|
|
+ mdelay(5);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
|
|
+ if (!(esdhc_read32(®s->vendorspec) &
|
|
|
+ ESDHC_VENDORSPEC_VSELECT))
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ return -EAGAIN;
|
|
|
+ case MMC_SIGNAL_VOLTAGE_180:
|
|
|
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
|
|
+ if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
|
|
|
+ ret = regulator_set_value(priv->vqmmc_dev, 1800000);
|
|
|
+ if (ret) {
|
|
|
+ printf("Setting to 1.8V error");
|
|
|
+ return -EIO;
|
|
|
+ }
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
|
|
+ if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ return -EAGAIN;
|
|
|
+ case MMC_SIGNAL_VOLTAGE_120:
|
|
|
+ return -ENOTSUPP;
|
|
|
+ default:
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void esdhc_stop_tuning(struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct mmc_cmd cmd;
|
|
|
+
|
|
|
+ cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
|
|
|
+ cmd.cmdarg = 0;
|
|
|
+ cmd.resp_type = MMC_RSP_R1b;
|
|
|
+
|
|
|
+ dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
|
|
|
+}
|
|
|
+
|
|
|
+static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ struct mmc *mmc = &plat->mmc;
|
|
|
+ u32 irqstaten = readl(®s->irqstaten);
|
|
|
+ u32 irqsigen = readl(®s->irqsigen);
|
|
|
+ int i, ret = -ETIMEDOUT;
|
|
|
+ u32 val, mixctrl;
|
|
|
+
|
|
|
+ /* clock tuning is not needed for upto 52MHz */
|
|
|
+ if (mmc->clock <= 52000000)
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
|
|
|
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
|
|
|
+ val = readl(®s->autoc12err);
|
|
|
+ mixctrl = readl(®s->mixctrl);
|
|
|
+ val &= ~MIX_CTRL_SMPCLK_SEL;
|
|
|
+ mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
|
|
|
+
|
|
|
+ val |= MIX_CTRL_EXE_TUNE;
|
|
|
+ mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
|
|
|
+
|
|
|
+ writel(val, ®s->autoc12err);
|
|
|
+ writel(mixctrl, ®s->mixctrl);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
|
|
|
+ mixctrl = readl(®s->mixctrl);
|
|
|
+ mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
|
|
|
+ writel(mixctrl, ®s->mixctrl);
|
|
|
+
|
|
|
+ writel(IRQSTATEN_BRR, ®s->irqstaten);
|
|
|
+ writel(IRQSTATEN_BRR, ®s->irqsigen);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
|
|
|
+ * of loops reaches 40 times.
|
|
|
+ */
|
|
|
+ for (i = 0; i < MAX_TUNING_LOOP; i++) {
|
|
|
+ u32 ctrl;
|
|
|
+
|
|
|
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
|
|
|
+ if (mmc->bus_width == 8)
|
|
|
+ writel(0x7080, ®s->blkattr);
|
|
|
+ else if (mmc->bus_width == 4)
|
|
|
+ writel(0x7040, ®s->blkattr);
|
|
|
+ } else {
|
|
|
+ writel(0x7040, ®s->blkattr);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
|
|
|
+ val = readl(®s->mixctrl);
|
|
|
+ val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
|
|
|
+ writel(val, ®s->mixctrl);
|
|
|
+
|
|
|
+ /* We are using STD tuning, no need to check return value */
|
|
|
+ mmc_send_tuning(mmc, opcode, NULL);
|
|
|
+
|
|
|
+ ctrl = readl(®s->autoc12err);
|
|
|
+ if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
|
|
|
+ (ctrl & MIX_CTRL_SMPCLK_SEL)) {
|
|
|
+ /*
|
|
|
+ * need to wait some time, make sure sd/mmc fininsh
|
|
|
+ * send out tuning data, otherwise, the sd/mmc can't
|
|
|
+ * response to any command when the card still out
|
|
|
+ * put the tuning data.
|
|
|
+ */
|
|
|
+ mdelay(1);
|
|
|
+ ret = 0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Add 1ms delay for SD and eMMC */
|
|
|
+ mdelay(1);
|
|
|
+ }
|
|
|
+
|
|
|
+ writel(irqstaten, ®s->irqstaten);
|
|
|
+ writel(irqsigen, ®s->irqsigen);
|
|
|
+
|
|
|
+ esdhc_stop_tuning(mmc);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ int ret __maybe_unused;
|
|
|
+
|
|
|
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
|
|
+ /* Select to use peripheral clock */
|
|
|
+ esdhc_clock_control(priv, false);
|
|
|
+ esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
|
|
|
+ esdhc_clock_control(priv, true);
|
|
|
+#endif
|
|
|
+ /* Set the clock speed */
|
|
|
+ if (priv->clock != mmc->clock)
|
|
|
+ set_sysctl(priv, mmc, mmc->clock);
|
|
|
+
|
|
|
+#ifdef MMC_SUPPORTS_TUNING
|
|
|
+ if (mmc->clk_disable) {
|
|
|
+#ifdef CONFIG_FSL_USDHC
|
|
|
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
|
|
|
+#else
|
|
|
+ esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
|
|
|
+#endif
|
|
|
+ } else {
|
|
|
+#ifdef CONFIG_FSL_USDHC
|
|
|
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
|
|
|
+ VENDORSPEC_CKEN);
|
|
|
+#else
|
|
|
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
|
|
|
+#endif
|
|
|
+ }
|
|
|
+
|
|
|
+ if (priv->mode != mmc->selected_mode) {
|
|
|
+ ret = esdhc_set_timing(mmc);
|
|
|
+ if (ret) {
|
|
|
+ printf("esdhc_set_timing error %d\n", ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (priv->signal_voltage != mmc->signal_voltage) {
|
|
|
+ ret = esdhc_set_voltage(mmc);
|
|
|
+ if (ret) {
|
|
|
+ printf("esdhc_set_voltage error %d\n", ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* Set the bus width */
|
|
|
+ esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
|
|
|
+
|
|
|
+ if (mmc->bus_width == 4)
|
|
|
+ esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
|
|
|
+ else if (mmc->bus_width == 8)
|
|
|
+ esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ ulong start;
|
|
|
+
|
|
|
+ /* Reset the entire host controller */
|
|
|
+ esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
|
|
|
+
|
|
|
+ /* Wait until the controller is available */
|
|
|
+ start = get_timer(0);
|
|
|
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
|
|
|
+ if (get_timer(start) > 1000)
|
|
|
+ return -ETIMEDOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+#if defined(CONFIG_FSL_USDHC)
|
|
|
+ /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
|
|
|
+ esdhc_write32(®s->mmcboot, 0x0);
|
|
|
+ /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
|
|
|
+ esdhc_write32(®s->mixctrl, 0x0);
|
|
|
+ esdhc_write32(®s->clktunectrlstatus, 0x0);
|
|
|
+
|
|
|
+ /* Put VEND_SPEC to default value */
|
|
|
+ if (priv->vs18_enable)
|
|
|
+ esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
|
|
|
+ ESDHC_VENDORSPEC_VSELECT));
|
|
|
+ else
|
|
|
+ esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
|
|
|
+
|
|
|
+ /* Disable DLL_CTRL delay line */
|
|
|
+ esdhc_write32(®s->dllctrl, 0x0);
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef ARCH_MXC
|
|
|
+ /* Enable cache snooping */
|
|
|
+ esdhc_write32(®s->scr, 0x00000040);
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef CONFIG_FSL_USDHC
|
|
|
+ esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
|
|
|
+#else
|
|
|
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* Set the initial clock speed */
|
|
|
+ mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
|
|
|
+
|
|
|
+ /* Disable the BRR and BWR bits in IRQSTAT */
|
|
|
+ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
|
|
|
+
|
|
|
+#ifdef CONFIG_MCF5441x
|
|
|
+ esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
|
|
|
+#else
|
|
|
+ /* Put the PROCTL reg back to the default */
|
|
|
+ esdhc_write32(®s->proctl, PROCTL_INIT);
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* Set timout to the maximum value */
|
|
|
+ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
|
|
|
+{
|
|
|
+ struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
+ int timeout = 1000;
|
|
|
+
|
|
|
+#ifdef CONFIG_ESDHC_DETECT_QUIRK
|
|
|
+ if (CONFIG_ESDHC_DETECT_QUIRK)
|
|
|
+ return 1;
|
|
|
+#endif
|
|
|
+
|
|
|
+#if CONFIG_IS_ENABLED(DM_MMC)
|
|
|
+ if (priv->non_removable)
|
|
|
+ return 1;
|
|
|
+#ifdef CONFIG_DM_GPIO
|
|
|
+ if (dm_gpio_is_valid(&priv->cd_gpio))
|
|
|
+ return dm_gpio_get_value(&priv->cd_gpio);
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+
|
|
|
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
|
|
|
+ udelay(1000);
|
|
|
+
|
|
|
+ return timeout > 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int esdhc_reset(struct fsl_esdhc *regs)
|
|
|
+{
|
|
|
+ ulong start;
|
|
|
+
|
|
|
+ /* reset the controller */
|
|
|
+ esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
|
|
|
+
|
|
|
+ /* hardware clears the bit when it is done */
|
|
|
+ start = get_timer(0);
|
|
|
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
|
|
|
+ if (get_timer(start) > 100) {
|
|
|
+ printf("MMC/SD: Reset never completed.\n");
|
|
|
+ return -ETIMEDOUT;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+#if !CONFIG_IS_ENABLED(DM_MMC)
|
|
|
+static int esdhc_getcd(struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
+
|
|
|
+ return esdhc_getcd_common(priv);
|
|
|
+}
|
|
|
+
|
|
|
+static int esdhc_init(struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
+
|
|
|
+ return esdhc_init_common(priv, mmc);
|
|
|
+}
|
|
|
+
|
|
|
+static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
|
|
|
+ struct mmc_data *data)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
+
|
|
|
+ return esdhc_send_cmd_common(priv, mmc, cmd, data);
|
|
|
+}
|
|
|
+
|
|
|
+static int esdhc_set_ios(struct mmc *mmc)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
+
|
|
|
+ return esdhc_set_ios_common(priv, mmc);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct mmc_ops esdhc_ops = {
|
|
|
+ .getcd = esdhc_getcd,
|
|
|
+ .init = esdhc_init,
|
|
|
+ .send_cmd = esdhc_send_cmd,
|
|
|
+ .set_ios = esdhc_set_ios,
|
|
|
+};
|
|
|
+#endif
|
|
|
+
|
|
|
+static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
|
|
|
+ struct fsl_esdhc_plat *plat)
|
|
|
+{
|
|
|
+ struct mmc_config *cfg;
|
|
|
+ struct fsl_esdhc *regs;
|
|
|
+ u32 caps, voltage_caps;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (!priv)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ regs = priv->esdhc_regs;
|
|
|
+
|
|
|
+ /* First reset the eSDHC controller */
|
|
|
+ ret = esdhc_reset(regs);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+#ifdef CONFIG_MCF5441x
|
|
|
+ /* ColdFire, using SDHC_DATA[3] for card detection */
|
|
|
+ esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifndef CONFIG_FSL_USDHC
|
|
|
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
|
|
|
+ | SYSCTL_IPGEN | SYSCTL_CKEN);
|
|
|
+ /* Clearing tuning bits in case ROM has set it already */
|
|
|
+ esdhc_write32(®s->mixctrl, 0);
|
|
|
+ esdhc_write32(®s->autoc12err, 0);
|
|
|
+ esdhc_write32(®s->clktunectrlstatus, 0);
|
|
|
+#else
|
|
|
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
|
|
|
+ VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
|
|
|
+#endif
|
|
|
+
|
|
|
+ if (priv->vs18_enable)
|
|
|
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
|
|
+
|
|
|
+ writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
|
|
|
+ cfg = &plat->cfg;
|
|
|
+#ifndef CONFIG_DM_MMC
|
|
|
+ memset(cfg, '\0', sizeof(*cfg));
|
|
|
+#endif
|
|
|
+
|
|
|
+ voltage_caps = 0;
|
|
|
+ caps = esdhc_read32(®s->hostcapblt);
|
|
|
+
|
|
|
+#ifdef CONFIG_MCF5441x
|
|
|
+ /*
|
|
|
+ * MCF5441x RM declares in more points that sdhc clock speed must
|
|
|
+ * never exceed 25 Mhz. From this, the HS bit needs to be disabled
|
|
|
+ * from host capabilities.
|
|
|
+ */
|
|
|
+ caps &= ~ESDHC_HOSTCAPBLT_HSS;
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
|
|
|
+ caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
|
|
|
+ ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
|
|
|
+#endif
|
|
|
+
|
|
|
+/* T4240 host controller capabilities register should have VS33 bit */
|
|
|
+#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
|
|
+ caps = caps | ESDHC_HOSTCAPBLT_VS33;
|
|
|
+#endif
|
|
|
+
|
|
|
+ if (caps & ESDHC_HOSTCAPBLT_VS18)
|
|
|
+ voltage_caps |= MMC_VDD_165_195;
|
|
|
+ if (caps & ESDHC_HOSTCAPBLT_VS30)
|
|
|
+ voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
|
|
|
+ if (caps & ESDHC_HOSTCAPBLT_VS33)
|
|
|
+ voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
+
|
|
|
+ cfg->name = "FSL_SDHC";
|
|
|
+#if !CONFIG_IS_ENABLED(DM_MMC)
|
|
|
+ cfg->ops = &esdhc_ops;
|
|
|
+#endif
|
|
|
+#ifdef CONFIG_SYS_SD_VOLTAGE
|
|
|
+ cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
|
|
|
+#else
|
|
|
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
+#endif
|
|
|
+ if ((cfg->voltages & voltage_caps) == 0) {
|
|
|
+ printf("voltage not supported by controller\n");
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (priv->bus_width == 8)
|
|
|
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
|
|
|
+ else if (priv->bus_width == 4)
|
|
|
+ cfg->host_caps = MMC_MODE_4BIT;
|
|
|
+
|
|
|
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
|
|
|
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
|
|
|
+ cfg->host_caps |= MMC_MODE_DDR_52MHz;
|
|
|
+#endif
|
|
|
+
|
|
|
+ if (priv->bus_width > 0) {
|
|
|
+ if (priv->bus_width < 8)
|
|
|
+ cfg->host_caps &= ~MMC_MODE_8BIT;
|
|
|
+ if (priv->bus_width < 4)
|
|
|
+ cfg->host_caps &= ~MMC_MODE_4BIT;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (caps & ESDHC_HOSTCAPBLT_HSS)
|
|
|
+ cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
|
+
|
|
|
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
|
|
|
+ if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
|
|
|
+ cfg->host_caps &= ~MMC_MODE_8BIT;
|
|
|
+#endif
|
|
|
+
|
|
|
+ cfg->host_caps |= priv->caps;
|
|
|
+
|
|
|
+ cfg->f_min = 400000;
|
|
|
+ cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
|
|
|
+
|
|
|
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
|
+
|
|
|
+ writel(0, ®s->dllctrl);
|
|
|
+ if (priv->flags & ESDHC_FLAG_USDHC) {
|
|
|
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
|
|
|
+ u32 val = readl(®s->tuning_ctrl);
|
|
|
+
|
|
|
+ val |= ESDHC_STD_TUNING_EN;
|
|
|
+ val &= ~ESDHC_TUNING_START_TAP_MASK;
|
|
|
+ val |= priv->tuning_start_tap;
|
|
|
+ val &= ~ESDHC_TUNING_STEP_MASK;
|
|
|
+ val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
|
|
|
+ writel(val, ®s->tuning_ctrl);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+#if !CONFIG_IS_ENABLED(DM_MMC)
|
|
|
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
|
|
|
+ struct fsl_esdhc_priv *priv)
|
|
|
+{
|
|
|
+ if (!cfg || !priv)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
|
|
|
+ priv->bus_width = cfg->max_bus_width;
|
|
|
+ priv->sdhc_clk = cfg->sdhc_clk;
|
|
|
+ priv->wp_enable = cfg->wp_enable;
|
|
|
+ priv->vs18_enable = cfg->vs18_enable;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+};
|
|
|
+
|
|
|
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_plat *plat;
|
|
|
+ struct fsl_esdhc_priv *priv;
|
|
|
+ struct mmc *mmc;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (!cfg)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
|
|
|
+ if (!priv)
|
|
|
+ return -ENOMEM;
|
|
|
+ plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
|
|
|
+ if (!plat) {
|
|
|
+ free(priv);
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = fsl_esdhc_cfg_to_priv(cfg, priv);
|
|
|
+ if (ret) {
|
|
|
+ debug("%s xlate failure\n", __func__);
|
|
|
+ free(plat);
|
|
|
+ free(priv);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = fsl_esdhc_init(priv, plat);
|
|
|
+ if (ret) {
|
|
|
+ debug("%s init failure\n", __func__);
|
|
|
+ free(plat);
|
|
|
+ free(priv);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ mmc = mmc_create(&plat->cfg, priv);
|
|
|
+ if (!mmc)
|
|
|
+ return -EIO;
|
|
|
+
|
|
|
+ priv->mmc = mmc;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int fsl_esdhc_mmc_init(bd_t *bis)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_cfg *cfg;
|
|
|
+
|
|
|
+ cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
|
|
|
+ cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
|
|
|
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
|
|
|
+ return fsl_esdhc_initialize(bis, cfg);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
|
|
+void mmc_adapter_card_type_ident(void)
|
|
|
+{
|
|
|
+ u8 card_id;
|
|
|
+ u8 value;
|
|
|
+
|
|
|
+ card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
|
|
|
+ gd->arch.sdhc_adapter = card_id;
|
|
|
+
|
|
|
+ switch (card_id) {
|
|
|
+ case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
|
|
|
+ value = QIXIS_READ(brdcfg[5]);
|
|
|
+ value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
|
|
|
+ QIXIS_WRITE(brdcfg[5], value);
|
|
|
+ break;
|
|
|
+ case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
|
|
|
+ value = QIXIS_READ(pwr_ctl[1]);
|
|
|
+ value |= QIXIS_EVDD_BY_SDHC_VS;
|
|
|
+ QIXIS_WRITE(pwr_ctl[1], value);
|
|
|
+ break;
|
|
|
+ case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
|
|
|
+ value = QIXIS_READ(brdcfg[5]);
|
|
|
+ value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
|
|
|
+ QIXIS_WRITE(brdcfg[5], value);
|
|
|
+ break;
|
|
|
+ case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
|
|
|
+ break;
|
|
|
+ case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
|
|
|
+ break;
|
|
|
+ case QIXIS_ESDHC_ADAPTER_TYPE_SD:
|
|
|
+ break;
|
|
|
+ case QIXIS_ESDHC_NO_ADAPTER:
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ }
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef CONFIG_OF_LIBFDT
|
|
|
+__weak int esdhc_status_fixup(void *blob, const char *compat)
|
|
|
+{
|
|
|
+#ifdef CONFIG_FSL_ESDHC_PIN_MUX
|
|
|
+ if (!hwconfig("esdhc")) {
|
|
|
+ do_fixup_by_compat(blob, compat, "status", "disabled",
|
|
|
+ sizeof("disabled"), 1);
|
|
|
+ return 1;
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+void fdt_fixup_esdhc(void *blob, bd_t *bd)
|
|
|
+{
|
|
|
+ const char *compat = "fsl,esdhc";
|
|
|
+
|
|
|
+ if (esdhc_status_fixup(blob, compat))
|
|
|
+ return;
|
|
|
+
|
|
|
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
|
|
+ do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
|
|
|
+ gd->arch.sdhc_clk, 1);
|
|
|
+#else
|
|
|
+ do_fixup_by_compat_u32(blob, compat, "clock-frequency",
|
|
|
+ gd->arch.sdhc_clk, 1);
|
|
|
+#endif
|
|
|
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
|
|
+ do_fixup_by_compat_u32(blob, compat, "adapter-type",
|
|
|
+ (u32)(gd->arch.sdhc_adapter), 1);
|
|
|
+#endif
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#if CONFIG_IS_ENABLED(DM_MMC)
|
|
|
+#ifndef CONFIG_PPC
|
|
|
+#include <asm/arch/clock.h>
|
|
|
+#endif
|
|
|
+__weak void init_clk_usdhc(u32 index)
|
|
|
+{
|
|
|
+}
|
|
|
+
|
|
|
+static int fsl_esdhc_probe(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
|
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
+ const void *fdt = gd->fdt_blob;
|
|
|
+ int node = dev_of_offset(dev);
|
|
|
+ struct esdhc_soc_data *data =
|
|
|
+ (struct esdhc_soc_data *)dev_get_driver_data(dev);
|
|
|
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
|
|
+ struct udevice *vqmmc_dev;
|
|
|
+#endif
|
|
|
+ fdt_addr_t addr;
|
|
|
+ unsigned int val;
|
|
|
+ struct mmc *mmc;
|
|
|
+#if !CONFIG_IS_ENABLED(BLK)
|
|
|
+ struct blk_desc *bdesc;
|
|
|
+#endif
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ addr = dev_read_addr(dev);
|
|
|
+ if (addr == FDT_ADDR_T_NONE)
|
|
|
+ return -EINVAL;
|
|
|
+#ifdef CONFIG_PPC
|
|
|
+ priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
|
|
|
+#else
|
|
|
+ priv->esdhc_regs = (struct fsl_esdhc *)addr;
|
|
|
+#endif
|
|
|
+ priv->dev = dev;
|
|
|
+ priv->mode = -1;
|
|
|
+ if (data) {
|
|
|
+ priv->flags = data->flags;
|
|
|
+ priv->caps = data->caps;
|
|
|
+ }
|
|
|
+
|
|
|
+ val = dev_read_u32_default(dev, "bus-width", -1);
|
|
|
+ if (val == 8)
|
|
|
+ priv->bus_width = 8;
|
|
|
+ else if (val == 4)
|
|
|
+ priv->bus_width = 4;
|
|
|
+ else
|
|
|
+ priv->bus_width = 1;
|
|
|
+
|
|
|
+ val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
|
|
|
+ priv->tuning_step = val;
|
|
|
+ val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
|
|
|
+ ESDHC_TUNING_START_TAP_DEFAULT);
|
|
|
+ priv->tuning_start_tap = val;
|
|
|
+ val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
|
|
|
+ ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
|
|
|
+ priv->strobe_dll_delay_target = val;
|
|
|
+
|
|
|
+ if (dev_read_bool(dev, "non-removable")) {
|
|
|
+ priv->non_removable = 1;
|
|
|
+ } else {
|
|
|
+ priv->non_removable = 0;
|
|
|
+#ifdef CONFIG_DM_GPIO
|
|
|
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
|
|
|
+ GPIOD_IS_IN);
|
|
|
+#endif
|
|
|
+ }
|
|
|
+
|
|
|
+ if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
|
|
|
+ priv->wp_enable = 1;
|
|
|
+ } else {
|
|
|
+ priv->wp_enable = 0;
|
|
|
+#ifdef CONFIG_DM_GPIO
|
|
|
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
|
|
|
+ GPIOD_IS_IN);
|
|
|
+#endif
|
|
|
+ }
|
|
|
+
|
|
|
+ priv->vs18_enable = 0;
|
|
|
+
|
|
|
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
|
|
+ /*
|
|
|
+ * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
|
|
|
+ * otherwise, emmc will work abnormally.
|
|
|
+ */
|
|
|
+ ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
|
|
|
+ if (ret) {
|
|
|
+ dev_dbg(dev, "no vqmmc-supply\n");
|
|
|
+ } else {
|
|
|
+ ret = regulator_set_enable(vqmmc_dev, true);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "fail to enable vqmmc-supply\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (regulator_get_value(vqmmc_dev) == 1800000)
|
|
|
+ priv->vs18_enable = 1;
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
|
|
|
+ priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * TODO:
|
|
|
+ * Because lack of clk driver, if SDHC clk is not enabled,
|
|
|
+ * need to enable it first before this driver is invoked.
|
|
|
+ *
|
|
|
+ * we use MXC_ESDHC_CLK to get clk freq.
|
|
|
+ * If one would like to make this function work,
|
|
|
+ * the aliases should be provided in dts as this:
|
|
|
+ *
|
|
|
+ * aliases {
|
|
|
+ * mmc0 = &usdhc1;
|
|
|
+ * mmc1 = &usdhc2;
|
|
|
+ * mmc2 = &usdhc3;
|
|
|
+ * mmc3 = &usdhc4;
|
|
|
+ * };
|
|
|
+ * Then if your board only supports mmc2 and mmc3, but we can
|
|
|
+ * correctly get the seq as 2 and 3, then let mxc_get_clock
|
|
|
+ * work as expected.
|
|
|
+ */
|
|
|
+
|
|
|
+ init_clk_usdhc(dev->seq);
|
|
|
+
|
|
|
+ if (IS_ENABLED(CONFIG_CLK)) {
|
|
|
+ /* Assigned clock already set clock */
|
|
|
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
|
|
|
+ if (ret) {
|
|
|
+ printf("Failed to get per_clk\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ ret = clk_enable(&priv->per_clk);
|
|
|
+ if (ret) {
|
|
|
+ printf("Failed to enable per_clk\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ priv->sdhc_clk = clk_get_rate(&priv->per_clk);
|
|
|
+ } else {
|
|
|
+#ifndef CONFIG_PPC
|
|
|
+ priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
|
|
|
+#else
|
|
|
+ priv->sdhc_clk = gd->arch.sdhc_clk;
|
|
|
+#endif
|
|
|
+ if (priv->sdhc_clk <= 0) {
|
|
|
+ dev_err(dev, "Unable to get clk for %s\n", dev->name);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = fsl_esdhc_init(priv, plat);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "fsl_esdhc_init failure\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ mmc = &plat->mmc;
|
|
|
+ mmc->cfg = &plat->cfg;
|
|
|
+ mmc->dev = dev;
|
|
|
+#if !CONFIG_IS_ENABLED(BLK)
|
|
|
+ mmc->priv = priv;
|
|
|
+
|
|
|
+ /* Setup dsr related values */
|
|
|
+ mmc->dsr_imp = 0;
|
|
|
+ mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
|
|
|
+ /* Setup the universal parts of the block interface just once */
|
|
|
+ bdesc = mmc_get_blk_desc(mmc);
|
|
|
+ bdesc->if_type = IF_TYPE_MMC;
|
|
|
+ bdesc->removable = 1;
|
|
|
+ bdesc->devnum = mmc_get_next_devnum();
|
|
|
+ bdesc->block_read = mmc_bread;
|
|
|
+ bdesc->block_write = mmc_bwrite;
|
|
|
+ bdesc->block_erase = mmc_berase;
|
|
|
+
|
|
|
+ /* setup initial part type */
|
|
|
+ bdesc->part_type = mmc->cfg->part_type;
|
|
|
+ mmc_list_add(mmc);
|
|
|
+#endif
|
|
|
+
|
|
|
+ upriv->mmc = mmc;
|
|
|
+
|
|
|
+ return esdhc_init_common(priv, mmc);
|
|
|
+}
|
|
|
+
|
|
|
+#if CONFIG_IS_ENABLED(DM_MMC)
|
|
|
+static int fsl_esdhc_get_cd(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
+
|
|
|
+ return esdhc_getcd_common(priv);
|
|
|
+}
|
|
|
+
|
|
|
+static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
|
|
|
+ struct mmc_data *data)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
+
|
|
|
+ return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
|
|
|
+}
|
|
|
+
|
|
|
+static int fsl_esdhc_set_ios(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
|
|
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
+
|
|
|
+ return esdhc_set_ios_common(priv, &plat->mmc);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct dm_mmc_ops fsl_esdhc_ops = {
|
|
|
+ .get_cd = fsl_esdhc_get_cd,
|
|
|
+ .send_cmd = fsl_esdhc_send_cmd,
|
|
|
+ .set_ios = fsl_esdhc_set_ios,
|
|
|
+#ifdef MMC_SUPPORTS_TUNING
|
|
|
+ .execute_tuning = fsl_esdhc_execute_tuning,
|
|
|
+#endif
|
|
|
+};
|
|
|
+#endif
|
|
|
+
|
|
|
+static struct esdhc_soc_data usdhc_imx7d_data = {
|
|
|
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
|
|
|
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
|
|
|
+ | ESDHC_FLAG_HS400,
|
|
|
+ .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
|
|
|
+ MMC_MODE_HS_52MHz | MMC_MODE_HS,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct udevice_id fsl_esdhc_ids[] = {
|
|
|
+ { .compatible = "fsl,imx53-esdhc", },
|
|
|
+ { .compatible = "fsl,imx6ul-usdhc", },
|
|
|
+ { .compatible = "fsl,imx6sx-usdhc", },
|
|
|
+ { .compatible = "fsl,imx6sl-usdhc", },
|
|
|
+ { .compatible = "fsl,imx6q-usdhc", },
|
|
|
+ { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
|
|
|
+ { .compatible = "fsl,imx7ulp-usdhc", },
|
|
|
+ { .compatible = "fsl,esdhc", },
|
|
|
+ { /* sentinel */ }
|
|
|
+};
|
|
|
+
|
|
|
+#if CONFIG_IS_ENABLED(BLK)
|
|
|
+static int fsl_esdhc_bind(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
|
|
+
|
|
|
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+U_BOOT_DRIVER(fsl_esdhc) = {
|
|
|
+ .name = "fsl-esdhc-mmc",
|
|
|
+ .id = UCLASS_MMC,
|
|
|
+ .of_match = fsl_esdhc_ids,
|
|
|
+ .ops = &fsl_esdhc_ops,
|
|
|
+#if CONFIG_IS_ENABLED(BLK)
|
|
|
+ .bind = fsl_esdhc_bind,
|
|
|
+#endif
|
|
|
+ .probe = fsl_esdhc_probe,
|
|
|
+ .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
|
|
|
+ .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
|
|
|
+};
|
|
|
+#endif
|