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@@ -14,21 +14,34 @@
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#define DC_CTRL_CACHE_DISABLE (1 << 0)
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#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
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#define DC_CTRL_FLUSH_STATUS (1 << 8)
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+#define CACHE_VER_NUM_MASK 0xF
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int icache_status(void)
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{
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+ /* If no cache in CPU exit immediately */
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+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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+ return 0;
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+
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return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
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IC_CTRL_CACHE_DISABLE;
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}
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void icache_enable(void)
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{
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+ /* If no cache in CPU exit immediately */
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+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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+ return;
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+
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
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~IC_CTRL_CACHE_DISABLE);
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}
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void icache_disable(void)
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{
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+ /* If no cache in CPU exit immediately */
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+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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+ return;
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+
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
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IC_CTRL_CACHE_DISABLE);
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}
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@@ -43,24 +56,40 @@ void invalidate_icache_all(void)
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int dcache_status(void)
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{
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+ /* If no cache in CPU exit immediately */
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+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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+ return 0;
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+
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return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
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DC_CTRL_CACHE_DISABLE;
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}
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void dcache_enable(void)
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{
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+ /* If no cache in CPU exit immediately */
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+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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+ return;
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+
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
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~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
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}
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void dcache_disable(void)
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{
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+ /* If no cache in CPU exit immediately */
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+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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+ return;
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+
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
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DC_CTRL_CACHE_DISABLE);
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}
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void flush_dcache_all(void)
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{
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+ /* If no cache in CPU exit immediately */
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+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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+ return;
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+
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/* Do flush of entire cache */
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write_aux_reg(ARC_AUX_DC_FLSH, 1);
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