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@@ -1603,6 +1603,7 @@ static const unsigned int canfd1_data_mux[] = {
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CANFD1_TX_MARK, CANFD1_RX_MARK,
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};
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+#ifdef CONFIG_PINCTRL_PFC_R8A77990
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/* - DRIF0 --------------------------------------------------------------- */
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static const unsigned int drif0_ctrl_a_pins[] = {
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/* CLK, SYNC */
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@@ -1795,6 +1796,7 @@ static const unsigned int drif3_data1_b_pins[] = {
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static const unsigned int drif3_data1_b_mux[] = {
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RIF3_D1_B_MARK,
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};
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+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
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/* - DU --------------------------------------------------------------------- */
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static const unsigned int du_rgb666_pins[] = {
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@@ -2818,6 +2820,57 @@ static const unsigned int pwm6_b_mux[] = {
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PWM6_B_MARK,
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};
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+/* - QSPI0 ------------------------------------------------------------------ */
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+static const unsigned int qspi0_ctrl_pins[] = {
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+ /* QSPI0_SPCLK, QSPI0_SSL */
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+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
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+};
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+static const unsigned int qspi0_ctrl_mux[] = {
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+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
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+};
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+static const unsigned int qspi0_data2_pins[] = {
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+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
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+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
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+};
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+static const unsigned int qspi0_data2_mux[] = {
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+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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+};
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+static const unsigned int qspi0_data4_pins[] = {
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+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
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+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
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+ /* QSPI0_IO2, QSPI0_IO3 */
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+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
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+};
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+static const unsigned int qspi0_data4_mux[] = {
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+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
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+};
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+/* - QSPI1 ------------------------------------------------------------------ */
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+static const unsigned int qspi1_ctrl_pins[] = {
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+ /* QSPI1_SPCLK, QSPI1_SSL */
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+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
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+};
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+static const unsigned int qspi1_ctrl_mux[] = {
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+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
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+};
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+static const unsigned int qspi1_data2_pins[] = {
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+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
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+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
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+};
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+static const unsigned int qspi1_data2_mux[] = {
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+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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+};
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+static const unsigned int qspi1_data4_pins[] = {
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+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
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+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
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+ /* QSPI1_IO2, QSPI1_IO3 */
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+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
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+};
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+static const unsigned int qspi1_data4_mux[] = {
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+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
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+};
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+
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/* - SCIF0 ------------------------------------------------------------------ */
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static const unsigned int scif0_data_a_pins[] = {
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/* RX, TX */
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@@ -3770,8 +3823,10 @@ static const unsigned int vin5_clk_b_mux[] = {
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};
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static const struct {
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- struct sh_pfc_pin_group common[247];
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+ struct sh_pfc_pin_group common[253];
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+#ifdef CONFIG_PINCTRL_PFC_R8A77990
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struct sh_pfc_pin_group automotive[21];
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+#endif
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} pinmux_groups = {
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.common = {
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SH_PFC_PIN_GROUP(audio_clk_a),
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@@ -3916,6 +3971,12 @@ static const struct {
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SH_PFC_PIN_GROUP(pwm5_b),
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SH_PFC_PIN_GROUP(pwm6_a),
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SH_PFC_PIN_GROUP(pwm6_b),
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+ SH_PFC_PIN_GROUP(qspi0_ctrl),
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+ SH_PFC_PIN_GROUP(qspi0_data2),
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+ SH_PFC_PIN_GROUP(qspi0_data4),
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+ SH_PFC_PIN_GROUP(qspi1_ctrl),
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+ SH_PFC_PIN_GROUP(qspi1_data2),
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+ SH_PFC_PIN_GROUP(qspi1_data4),
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SH_PFC_PIN_GROUP(scif0_data_a),
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SH_PFC_PIN_GROUP(scif0_clk_a),
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SH_PFC_PIN_GROUP(scif0_ctrl_a),
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@@ -4022,6 +4083,7 @@ static const struct {
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SH_PFC_PIN_GROUP(vin5_clk_a),
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SH_PFC_PIN_GROUP(vin5_clk_b),
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},
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+#ifdef CONFIG_PINCTRL_PFC_R8A77990
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.automotive = {
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SH_PFC_PIN_GROUP(drif0_ctrl_a),
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SH_PFC_PIN_GROUP(drif0_data0_a),
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@@ -4045,6 +4107,7 @@ static const struct {
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SH_PFC_PIN_GROUP(drif3_data0_b),
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SH_PFC_PIN_GROUP(drif3_data1_b),
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}
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+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
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};
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static const char * const audio_clk_groups[] = {
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@@ -4098,6 +4161,7 @@ static const char * const canfd1_groups[] = {
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"canfd1_data",
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};
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+#ifdef CONFIG_PINCTRL_PFC_R8A77990
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static const char * const drif0_groups[] = {
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"drif0_ctrl_a",
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"drif0_data0_a",
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@@ -4130,6 +4194,7 @@ static const char * const drif3_groups[] = {
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"drif3_data0_b",
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"drif3_data1_b",
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};
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+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
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static const char * const du_groups[] = {
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"du_rgb666",
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@@ -4315,6 +4380,18 @@ static const char * const pwm6_groups[] = {
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"pwm6_b",
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};
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+static const char * const qspi0_groups[] = {
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+ "qspi0_ctrl",
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+ "qspi0_data2",
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+ "qspi0_data4",
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+};
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+
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+static const char * const qspi1_groups[] = {
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+ "qspi1_ctrl",
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+ "qspi1_data2",
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+ "qspi1_data4",
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+};
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+
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static const char * const scif0_groups[] = {
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"scif0_data_a",
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"scif0_clk_a",
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@@ -4469,8 +4546,10 @@ static const char * const vin5_groups[] = {
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};
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static const struct {
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- struct sh_pfc_function common[47];
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+ struct sh_pfc_function common[49];
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+#ifdef CONFIG_PINCTRL_PFC_R8A77990
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struct sh_pfc_function automotive[4];
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+#endif
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} pinmux_functions = {
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.common = {
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SH_PFC_FUNCTION(audio_clk),
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@@ -4504,6 +4583,8 @@ static const struct {
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SH_PFC_FUNCTION(pwm4),
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SH_PFC_FUNCTION(pwm5),
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SH_PFC_FUNCTION(pwm6),
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+ SH_PFC_FUNCTION(qspi0),
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+ SH_PFC_FUNCTION(qspi1),
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SH_PFC_FUNCTION(scif0),
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SH_PFC_FUNCTION(scif1),
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SH_PFC_FUNCTION(scif2),
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@@ -4521,12 +4602,14 @@ static const struct {
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SH_PFC_FUNCTION(vin4),
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SH_PFC_FUNCTION(vin5),
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},
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+#ifdef CONFIG_PINCTRL_PFC_R8A77990
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.automotive = {
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SH_PFC_FUNCTION(drif0),
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SH_PFC_FUNCTION(drif1),
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SH_PFC_FUNCTION(drif2),
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SH_PFC_FUNCTION(drif3),
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}
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+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
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};
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static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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