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@@ -277,6 +277,16 @@ config SYS_FSL_SDHC_CLK_DIV
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clock, in another word SDHC_clk = Platform_clk / this_divider.
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endmenu
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+config RESV_RAM
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+ bool
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+ help
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+ Reserve memory from the top, tracked by gd->arch.resv_ram. This
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+ reserved RAM can be used by special driver that resides in memory
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+ after U-Boot exits. It's up to implementation to allocate and allow
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+ access to this reserved memory. For example, the reserved RAM can
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+ be at the high end of physical memory. The reserve RAM may be
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+ excluded from memory bank(s) passed to OS, or marked as reserved.
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+
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config SYS_FSL_ERRATUM_A008336
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bool
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