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@@ -20,7 +20,6 @@
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#define MODE_BITS_MASK 3
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#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
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-#ifndef CONFIG_SPL_BUILD
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/*
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* convert gpio offset to gpio index taking into account gpio holes
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* into gpio bank
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@@ -147,7 +146,6 @@ static const struct dm_gpio_ops gpio_stm32_ops = {
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.set_value = stm32_gpio_set_value,
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.get_function = stm32_gpio_get_function,
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};
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-#endif
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static int gpio_stm32_probe(struct udevice *dev)
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{
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@@ -162,7 +160,6 @@ static int gpio_stm32_probe(struct udevice *dev)
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priv->regs = (struct stm32_gpio_regs *)addr;
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-#ifndef CONFIG_SPL_BUILD
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct ofnode_phandle_args args;
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const char *name;
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@@ -195,7 +192,7 @@ static int gpio_stm32_probe(struct udevice *dev)
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dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
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(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
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priv->gpio_range);
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-#endif
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+
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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@@ -215,9 +212,7 @@ U_BOOT_DRIVER(gpio_stm32) = {
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.name = "gpio_stm32",
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.id = UCLASS_GPIO,
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.probe = gpio_stm32_probe,
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-#ifndef CONFIG_SPL_BUILD
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.ops = &gpio_stm32_ops,
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-#endif
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.flags = DM_UC_FLAG_SEQ_ALIAS,
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.priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
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};
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