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@@ -403,20 +403,20 @@ static unsigned char spd_read(uchar chip, uint addr)
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}
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/*-----------------------------------------------------------------------------+
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- * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
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+ * dram_init. Initializes the 440SP Memory Queue and DDR SDRAM controller.
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* Note: This routine runs from flash with a stack set up in the chip's
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* sram space. It is important that the routine does not require .sbss, .bss or
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* .data sections. It also cannot call routines that require these sections.
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*-----------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------------
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- * Function: initdram
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+ * Function: dram_init
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* Description: Configures SDRAM memory banks for DDR operation.
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* Auto Memory Configuration option reads the DDR SDRAM EEPROMs
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* via the IIC bus and then configures the DDR SDRAM memory
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* banks appropriately. If Auto Memory Configuration is
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* not used, it is assumed that no DIMM is plugged
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*-----------------------------------------------------------------------------*/
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-int initdram(void)
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+int dram_init(void)
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{
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unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
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unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
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@@ -2855,13 +2855,13 @@ static void test(void)
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#else /* CONFIG_SPD_EEPROM */
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/*-----------------------------------------------------------------------------
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- * Function: initdram
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+ * Function: dram_init
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* Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
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* The configuration is performed using static, compile-
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* time parameters.
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* Configures the PPC405EX(r) and PPC460EX/GT
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*---------------------------------------------------------------------------*/
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-int initdram(void)
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+int dram_init(void)
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{
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unsigned long val;
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