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@@ -34,42 +34,6 @@
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/* CM926EJ-S */
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/* CM1136-EJ-S */
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-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
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-#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */
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- /* - PLL test clock bypassed */
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- /* - bus clock ratio 2 */
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- /* - little endian */
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- /* - vectors at zero */
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-#endif /* CM1022xx */
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-
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-/* Determine CM characteristics */
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-
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-#undef CONFIG_CM_MULTIPLE_SSRAM
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-#undef CONFIG_CM_SPD_DETECT
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-#undef CONFIG_CM_REMAP
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-#undef CONFIG_CM_INIT
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-#undef CONFIG_CM_TCRAM
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-
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-#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
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-#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
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-#endif
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-
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-/* Excalibur core module has reduced functionality */
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-#ifndef CONFIG_CM922T_XA10
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-#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
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-#define OS_SPD 0x00000100 /* Address of SPD data */
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-#define CONFIG_CM_REMAP /* CM supports remapping */
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-#define CONFIG_CM_INIT /* CM has initialization reg */
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-#endif /* NOT EXCALIBUR */
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-
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-#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
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- defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
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- defined(CONFIG_CM1136JF_S)
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-#define CONFIG_CM_TCRAM /* CM has TCRAM */
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-#endif
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-
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-#ifdef CONFIG_CM_SPD_DETECT
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#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
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-#endif
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#endif /* __ARMCOREMODULE_H */
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