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@@ -11,9 +11,18 @@
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#include <asm/arch-rockchip/hardware.h>
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#include <dt-bindings/clock/rk3568-cru.h>
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-#define PMUGRF_BASE 0xfdc20000
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-#define GRF_BASE 0xfdc60000
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-
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+#define PMUGRF_BASE 0xfdc20000
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+#define GRF_BASE 0xfdc60000
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+#define GRF_GPIO1B_DS_2 0x218
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+#define GRF_GPIO1B_DS_3 0x21c
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+#define GRF_GPIO1C_DS_0 0x220
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+#define GRF_GPIO1C_DS_1 0x224
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+#define GRF_GPIO1C_DS_2 0x228
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+#define GRF_GPIO1C_DS_3 0x22c
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+#define SGRF_BASE 0xFDD18000
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+#define SGRF_SOC_CON4 0x10
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+#define EMMC_HPROT_SECURE_CTRL 0x03
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+#define SDMMC0_HPROT_SECURE_CTRL 0x01
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/* PMU_GRF_GPIO0D_IOMUX_L */
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enum {
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GPIO0D1_SHIFT = 4,
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@@ -81,5 +90,17 @@ void board_debug_uart_init(void)
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int arch_cpu_init(void)
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{
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+#ifdef CONFIG_SPL_BUILD
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+ /* Set the emmc sdmmc0 to secure */
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+ rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
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+ | SDMMC0_HPROT_SECURE_CTRL << 4));
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+ /* set the emmc driver strength to level 2 */
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+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
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+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
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+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
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+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
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+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
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+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
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+#endif
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return 0;
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}
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