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@@ -136,6 +136,20 @@
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reg-names = "control";
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};
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+ wdog: wdog@12480000 {
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+ compatible = "starfive,si5-wdt";
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+ reg = <0x0 0x12480000 0x0 0x10000>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <80>;
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+ interrupt-names = "wdog";
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+ clocks = <&clkgen JH7100_CLK_WDT_CORE>,
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+ <&clkgen JH7100_CLK_WDTIMER_APB>;
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+ clock-names = "core_clk", "apb_clk";
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+ clock-frequency = <50000000>;
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+ timeout-sec = <15>;
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+ status = "okay";
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+ };
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+
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plic: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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