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@@ -67,26 +67,37 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
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uint32_t vdctrl0;
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#if CONFIG_IS_ENABLED(CLK)
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- struct clk per_clk;
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+ struct clk clk;
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int ret;
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- ret = clk_get_by_name(dev, "per", &per_clk);
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+ ret = clk_get_by_name(dev, "pix", &clk);
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if (ret) {
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- dev_err(dev, "Failed to get mxs clk: %d\n", ret);
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+ dev_err(dev, "Failed to get mxs pix clk: %d\n", ret);
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return;
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}
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- ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
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+ ret = clk_set_rate(&clk, timings->pixelclock.typ);
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if (ret < 0) {
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- dev_err(dev, "Failed to set mxs clk: %d\n", ret);
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+ dev_err(dev, "Failed to set mxs pix clk: %d\n", ret);
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return;
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}
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- ret = clk_enable(&per_clk);
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+ ret = clk_enable(&clk);
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if (ret < 0) {
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- dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
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+ dev_err(dev, "Failed to enable mxs pix clk: %d\n", ret);
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return;
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}
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+
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+ ret = clk_get_by_name(dev, "axi", &clk);
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+ if (!ret) {
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+ debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
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+ } else {
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+ ret = clk_enable(&clk);
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+ if (ret < 0) {
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+ dev_err(dev, "Failed to enable mxs axi clk: %d\n", ret);
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+ return;
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+ }
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+ }
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#else
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/* Kick in the LCDIF clock */
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mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
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