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@@ -77,6 +77,7 @@
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#define GQSPI_GFIFO_SELECT BIT(0)
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#define GQSPI_FIFO_THRESHOLD 1
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+#define GQSPI_GENFIFO_THRESHOLD 31
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#define SPI_XFER_ON_BOTH 0
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#define SPI_XFER_ON_LOWER 1
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@@ -197,14 +198,15 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
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writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr);
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writel(GQSPI_FIFO_THRESHOLD, ®s->txftr);
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writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr);
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+ writel(GQSPI_GENFIFO_THRESHOLD, ®s->gqfthr);
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writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr);
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+ writel(~GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
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config_reg = readl(®s->confr);
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config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
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GQSPI_CONFIG_MODE_EN_MASK);
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- config_reg |= GQSPI_CONFIG_DMA_MODE |
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- GQSPI_GFIFO_WP_HOLD |
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- GQSPI_DFLT_BAUD_RATE_DIV;
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+ config_reg |= GQSPI_CONFIG_DMA_MODE | GQSPI_GFIFO_WP_HOLD |
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+ GQSPI_DFLT_BAUD_RATE_DIV | GQSPI_GFIFO_STRT_MODE_MASK;
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writel(config_reg, ®s->confr);
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writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
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@@ -242,6 +244,8 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
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u32 config_reg, ier;
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int ret = 0;
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+ writel(gqspi_fifo_reg, ®s->genfifo);
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+
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config_reg = readl(®s->confr);
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/* Manual start if needed */
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config_reg |= GQSPI_STRT_GEN_FIFO;
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@@ -249,16 +253,15 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
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/* Enable interrupts */
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ier = readl(®s->ier);
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- ier |= GQSPI_IXR_GFNFULL_MASK;
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+ ier |= GQSPI_IXR_GFEMTY_MASK;
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writel(ier, ®s->ier);
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- /* Wait until the fifo is not full to write the new command */
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- ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFNFULL_MASK, 1,
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+ /* Wait until the gen fifo is empty to write the new command */
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+ ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
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GQSPI_TIMEOUT, 1);
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if (ret)
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printf("%s Timeout\n", __func__);
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- writel(gqspi_fifo_reg, ®s->genfifo);
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}
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static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
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@@ -572,25 +575,20 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
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u32 gen_fifo_cmd, u32 *buf)
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{
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u32 addr;
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- u32 size, len;
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+ u32 size;
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u32 actuallen = priv->len;
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int ret = 0;
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struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
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writel((unsigned long)buf, &dma_regs->dmadst);
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- writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
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+ writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
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writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
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addr = (unsigned long)buf;
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- size = roundup(priv->len, ARCH_DMA_MINALIGN);
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+ size = roundup(priv->len, GQSPI_DMA_ALIGN);
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flush_dcache_range(addr, addr + size);
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while (priv->len) {
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- len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
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- if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
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- (len % ARCH_DMA_MINALIGN)) {
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- gen_fifo_cmd &= ~GENMASK(7, 0);
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- gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
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- }
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+ zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
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zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
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debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
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