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@@ -72,9 +72,9 @@
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JUNO_RESET_STATUS_PHY | \
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JUNO_RESET_STATUS_RC)
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-void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
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- unsigned long trsl_addr, int window_size,
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- int trsl_param)
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+static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
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+ unsigned long trsl_addr, int window_size,
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+ int trsl_param)
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{
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/* X3PCI_ATR_SRC_ADDR_LOW:
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- bit 0: enable entry,
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@@ -94,7 +94,7 @@ void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
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((u64)1) << window_size, trsl_param);
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}
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-void xr3pci_setup_atr(void)
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+static void xr3pci_setup_atr(void)
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{
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/* setup PCIe to CPU address translation tables */
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unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
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@@ -141,7 +141,7 @@ void xr3pci_setup_atr(void)
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XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
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}
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-void xr3pci_init(void)
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+static void xr3pci_init(void)
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{
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u32 val;
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int timeout = 200;
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@@ -193,5 +193,9 @@ void xr3pci_init(void)
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void vexpress64_pcie_init(void)
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{
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+ /* Initialise and configure the PCIe host bridge. */
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xr3pci_init();
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+
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+ /* Register the now ECAM complaint PCIe host controller with U-Boot. */
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+ pci_init();
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}
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